pinctrl: armada-37xx: Correct PWM pins definitions
Subsystems (4)
PATCH 1/1 pinctrl: armada-37xx: Correct PWM pins definitions
The PWM pins on North Bridge on Armada 37xx can be configured into PWM or GPIO functions. When in PWM function, each pin can also be configured to drive low on 0 and tri-state on 1 (LED mode).
The current definitions handle this by declaring two pin groups for each pin:
- group "pwmN" with functions "pwm" and "gpio"
- group "ledN_od" ("od" for open drain) with functions "led" and "gpio"
This is semantically incorrect. The correct definition for each pin should be one group with three functions: "pwm", "led" and "gpio".
Change the "pwmN" groups to support "led" function.
Remove "ledN_od" groups. This cannot break backwards compatibility with older device trees: no device tree uses it since there is no PWM driver for this SOC yet. Also "ledN_od" groups are not even documented.
--- .../pinctrl/marvell,armada-37xx-pinctrl.txt | 8 ++++---- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt +4 -4
@@ -43,19 +43,19 @@ group emmc_nb group pwm0 - pin 11 (GPIO1-11) - - functions pwm, gpio + - functions pwm, led, gpio group pwm1 - pin 12 - - functions pwm, gpio + - functions pwm, led, gpio group pwm2 - pin 13 - - functions pwm, gpio + - functions pwm, led, gpio group pwm3 - pin 14 - - functions pwm, gpio + - functions pwm, led, gpio group pmic1 - pin 7
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +8 -8
@@ -167,10 +167,14 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {PIN_GRP_GPIO ("jtag" ,20 ,5 ,BIT (0 ),"jtag" ),PIN_GRP_GPIO ("sdio0" ,8 ,3 ,BIT (1 ),"sdio" ),PIN_GRP_GPIO ("emmc_nb" ,27 ,9 ,BIT (2 ),"emmc" ), -PIN_GRP_GPIO ("pwm0" ,11 ,1 ,BIT (3 ),"pwm" ), -PIN_GRP_GPIO ("pwm1" ,12 ,1 ,BIT (4 ),"pwm" ), -PIN_GRP_GPIO ("pwm2" ,13 ,1 ,BIT (5 ),"pwm" ), -PIN_GRP_GPIO ("pwm3" ,14 ,1 ,BIT (6 ),"pwm" ), +PIN_GRP_GPIO_3 ("pwm0" ,11 ,1 ,BIT (3 ) |BIT (20 ),0 ,BIT (20 ),BIT (3 ), +"pwm" ,"led" ), +PIN_GRP_GPIO_3 ("pwm1" ,12 ,1 ,BIT (4 ) |BIT (21 ),0 ,BIT (21 ),BIT (4 ), +"pwm" ,"led" ), +PIN_GRP_GPIO_3 ("pwm2" ,13 ,1 ,BIT (5 ) |BIT (22 ),0 ,BIT (22 ),BIT (5 ), +"pwm" ,"led" ), +PIN_GRP_GPIO_3 ("pwm3" ,14 ,1 ,BIT (6 ) |BIT (23 ),0 ,BIT (23 ),BIT (6 ), +"pwm" ,"led" ),PIN_GRP_GPIO ("pmic1" ,7 ,1 ,BIT (7 ),"pmic" ),PIN_GRP_GPIO ("pmic0" ,6 ,1 ,BIT (8 ),"pmic" ), PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
@@ -184,10 +188,6 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {PIN_GRP_EXTRA ("uart2" ,9 ,2 ,BIT (1 ) |BIT (13 ) |BIT (14 ) |BIT (19 ),BIT (1 ) |BIT (13 ) |BIT (14 ),BIT (1 ) |BIT (19 ), 18, 2, "gpio", "uart"), -PIN_GRP_GPIO_2 ("led0_od" ,11 ,1 ,BIT (20 ),BIT (20 ),0 ,"led" ), -PIN_GRP_GPIO_2 ("led1_od" ,12 ,1 ,BIT (21 ),BIT (21 ),0 ,"led" ), -PIN_GRP_GPIO_2 ("led2_od" ,13 ,1 ,BIT (22 ),BIT (22 ),0 ,"led" ), - PIN_GRP_GPIO_2("led3_od", 14, 1, BIT(23), BIT(23), 0, "led"), };static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
Signature · 1 line
2.31.1
Quoted 13 lines · On Tue, 15 Jun 2021 00:25:27 +0200 Marek Behún <[email protected]> wrote:
The PWM pins on North Bridge on Armada 37xx can be configured into PWM or GPIO functions. When in PWM function, each pin can also be configured to drive low on 0 and tri-state on 1 (LED mode).
The current definitions handle this by declaring two pin groups for each pin:
- group "pwmN" with functions "pwm" and "gpio"
- group "ledN_od" ("od" for open drain) with functions "led" and "gpio"This is semantically incorrect. The correct definition for each pin should be one group with three functions: "pwm", "led" and "gpio".
Quoted 8 lines
Change the "pwmN" groups to support "led" function.
Remove "
ledN_od" groups. This cannot break backwards compatibility with older device trees: no device tree uses it since there is no PWM driver for this SOC yet. Also "ledN_od" groups are not even documented.Signed-off-by Marek Behún <[email protected]>
Should this also have a Fixes tag? (If it is accepted...?)
Quoted 18 lines · Marek Behún
The PWM pins on North Bridge on Armada 37xx can be configured into PWM or GPIO functions. When in PWM function, each pin can also be configured to drive low on 0 and tri-state on 1 (LED mode).
The current definitions handle this by declaring two pin groups for each pin:
- group "pwmN" with functions "pwm" and "gpio"
- group "ledN_od" ("od" for open drain) with functions "led" and "gpio"This is semantically incorrect. The correct definition for each pin should be one group with three functions: "pwm", "led" and "gpio".
Change the "pwmN" groups to support "led" function.
Remove "
ledN_od" groups. This cannot break backwards compatibility with older device trees: no device tree uses it since there is no PWM driver for this SOC yet. Also "ledN_od" groups are not even documented.
Quoted 6 lines
Signed-off-by Marek Behún <[email protected]>--- .../pinctrl/marvell,armada-37xx-pinctrl.txt | 8 ++++---- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-)