RISC-V Smstateen support

PATCH Superseded Mayuresh Chitale 3 participants 10 messages Apr 6, 2022 – Apr 11, 2022 RISC-V

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Mayuresh Chitale

author

2022-04-06 16:57 UTC #0 lore raw

v3 cover RISC-V Smstateen support

This series adds support for the Smstateen specification which provides a mechanism to plug potential covert channels which are opened by extensions which add to processor state that may not get context-switched. Currently access to AIA registers and *envcfg registers is controlled via smstateen.

Changes in v3:
- Fix RV32 compilation issue

Changes in v2:
- Rebase on latest master branch
- Fix indentation issue

Mayuresh Chitale (3):
lib: sbi: Add Smstateen extension defines
lib: sbi: Detect Smstateen CSRs at boot-time
lib: irqchip/imsic: configure mstateen

 include/sbi/riscv_encoding.h | 44 ++++++++++++++++++++++++++++++++++++
 include/sbi/sbi_hart.h       |  4 +++-
 lib/sbi/sbi_hart.c           | 31 +++++++++++++++++++++++++
 3 files changed, 78 insertions(+), 1 deletion(-)

Signature · 1 line

2.17.1

Mayuresh Chitale

author

2022-04-06 16:57 UTC #1 lore raw

PATCH v3 1/3 lib: sbi: Add Smstateen extension defines

Smstateen extension provides a mechanism to plug potential covert channels which are opened by extensions that add to processor state that may not get context-switched.

Signed-off-by Mayuresh Chitale <[email protected]>

---
 include/sbi/riscv_encoding.h | 44 ++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

include/sbi/riscv_encoding.h +44 -0

index c02aa8f..04d5621 100644
@@ -345,6 +345,12 @@
 #define CSR_SIEH			0x114
 #define CSR_SIPH			0x154
 
+/* Supervisor stateen CSRs */
+#define CSR_SSTATEEN0			0x10C
+#define CSR_SSTATEEN1			0x10D
+#define CSR_SSTATEEN2			0x10E
+#define CSR_SSTATEEN3			0x10F
+
 /* ===== Hypervisor-level CSRs ===== */
 
 /* Hypervisor Trap Setup (H-extension) */

@@ -413,6 +419,16 @@
 #define CSR_VSIEH			0x214
 #define CSR_VSIPH			0x254
 
+/* Hypervisor stateen CSRs */
+#define CSR_HSTATEEN0			0x60C
+#define CSR_HSTATEEN0H			0x61C
+#define CSR_HSTATEEN1			0x60D
+#define CSR_HSTATEEN1H			0x61D
+#define CSR_HSTATEEN2			0x60E
+#define CSR_HSTATEEN2H			0x61E
+#define CSR_HSTATEEN3			0x60F
+#define CSR_HSTATEEN3H			0x61F
+
 /* ===== Machine-level CSRs ===== */
 
 /* Machine Information Registers */

@@ -686,6 +702,17 @@
 #define CSR_MVIEN			0x308
 #define CSR_MVIP			0x309
 
+/* Smstateen extension registers */
+/* Machine stateen CSRs */
+#define CSR_MSTATEEN0			0x30C
+#define CSR_MSTATEEN0H			0x31C
+#define CSR_MSTATEEN1			0x30D
+#define CSR_MSTATEEN1H			0x31D
+#define CSR_MSTATEEN2			0x30E
+#define CSR_MSTATEEN2H			0x31E
+#define CSR_MSTATEEN3			0x30F
+#define CSR_MSTATEEN3H			0x31F
+
 /* Machine-Level High-Half CSRs (AIA) */
 #define CSR_MIDELEGH			0x313
 #define CSR_MIEH			0x314

@@ -715,6 +742,23 @@
 #define CAUSE_VIRTUAL_INST_FAULT	0x16
 #define CAUSE_STORE_GUEST_PAGE_FAULT	0x17
 
+/* Common defines for all smstateen */
+#define SMSTATEEN_MAX_COUNT		4
+#define SMSTATEEN0_CS_SHIFT		0
+#define SMSTATEEN0_CS			(_ULL(1) << SMSTATEEN0_CS_SHIFT)
+#define SMSTATEEN0_FCSR_SHIFT		1
+#define SMSTATEEN0_FCSR			(_ULL(1) << SMSTATEEN0_FCSR_SHIFT)
+#define SMSTATEEN0_IMSIC_SHIFT		58
+#define SMSTATEEN0_IMSIC		(_ULL(1) << SMSTATEEN0_IMSIC_SHIFT)
+#define SMSTATEEN0_AIA_SHIFT		59
+#define SMSTATEEN0_AIA			(_ULL(1) << SMSTATEEN0_AIA_SHIFT)
+#define SMSTATEEN0_SVSLCT_SHIFT		60
+#define SMSTATEEN0_SVSLCT		(_ULL(1) << SMSTATEEN0_SVSLCT_SHIFT)
+#define SMSTATEEN0_HSENVCFG_SHIFT	62
+#define SMSTATEEN0_HSENVCFG		(_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
+#define SMSTATEEN_STATEN_SHIFT		63
+#define SMSTATEEN_STATEN		(_ULL(1) << SMSTATEEN_STATEN_SHIFT)
+
 /* ===== Instruction Encodings ===== */
 
 #define INSN_MATCH_LB			0x3

Signature · 1 line

2.17.1

Xiang W

2022-04-07 09:53 UTC #2 lore raw

PATCH v3 1/3 lib: sbi: Add Smstateen extension defines

? 2022-04-06???? 22:27 +0530?Mayuresh Chitale???

Quoted 5 lines

Smstateen extension provides a mechanism to plug potential covert channels which are opened by extensions that add to processor state that may not get context-switched.
Signed-off-by Mayuresh Chitale <[email protected]>

Look good to me

Reviewed-by Xiang W <[email protected]>

Quoted 93 lines

---
?include/sbi/riscv_encoding.h | 44
++++++++++++++++++++++++++++++++++++
?1 file changed, 44 insertions(+)
include/sbi/riscv_encoding.h +0 -0
index c02aa8f..04d5621 100644
@@ -345,6 +345,12 @@
?#define CSR_SIEH???????????????????????0x114
?#define CSR_SIPH???????????????????????0x154
?
include/sbi/riscv_encoding.h +6 -0
+/* Supervisor stateen CSRs */
+#define CSR_SSTATEEN0??????????????????0x10C
+#define CSR_SSTATEEN1??????????????????0x10D
+#define CSR_SSTATEEN2??????????????????0x10E
+#define CSR_SSTATEEN3??????????????????0x10F
+
?/* ===== Hypervisor-level CSRs ===== */
?
?/* Hypervisor Trap Setup (H-extension) */
include/sbi/riscv_encoding.h +0 -0
@@ -413,6 +419,16 @@
?#define CSR_VSIEH??????????????????????0x214
?#define CSR_VSIPH??????????????????????0x254
?
include/sbi/riscv_encoding.h +10 -0
+/* Hypervisor stateen CSRs */
+#define CSR_HSTATEEN0??????????????????0x60C
+#define CSR_HSTATEEN0H?????????????????0x61C
+#define CSR_HSTATEEN1??????????????????0x60D
+#define CSR_HSTATEEN1H?????????????????0x61D
+#define CSR_HSTATEEN2??????????????????0x60E
+#define CSR_HSTATEEN2H?????????????????0x61E
+#define CSR_HSTATEEN3??????????????????0x60F
+#define CSR_HSTATEEN3H?????????????????0x61F
+
?/* ===== Machine-level CSRs ===== */
?
?/* Machine Information Registers */
include/sbi/riscv_encoding.h +0 -0
@@ -686,6 +702,17 @@
?#define CSR_MVIEN??????????????????????0x308
?#define CSR_MVIP???????????????????????0x309
?
include/sbi/riscv_encoding.h +11 -0
+/* Smstateen extension registers */
+/* Machine stateen CSRs */
+#define CSR_MSTATEEN0??????????????????0x30C
+#define CSR_MSTATEEN0H?????????????????0x31C
+#define CSR_MSTATEEN1??????????????????0x30D
+#define CSR_MSTATEEN1H?????????????????0x31D
+#define CSR_MSTATEEN2??????????????????0x30E
+#define CSR_MSTATEEN2H?????????????????0x31E
+#define CSR_MSTATEEN3??????????????????0x30F
+#define CSR_MSTATEEN3H?????????????????0x31F
+
?/* Machine-Level High-Half CSRs (AIA) */
?#define CSR_MIDELEGH???????????????????0x313
?#define CSR_MIEH???????????????????????0x314
include/sbi/riscv_encoding.h +0 -0
@@ -715,6 +742,23 @@
?#define CAUSE_VIRTUAL_INST_FAULT???????0x16
?#define CAUSE_STORE_GUEST_PAGE_FAULT???0x17
?
include/sbi/riscv_encoding.h +4 -0
+/* Common defines for all smstateen */
+#define SMSTATEEN_MAX_COUNT????????????4
+#define SMSTATEEN0_CS_SHIFT????????????0
+#define SMSTATEEN0_CS??????????????????(_ULL(1) <<
SMSTATEEN0_CS_SHIFT)
include/sbi/riscv_encoding.h +2 -0
+#define SMSTATEEN0_FCSR_SHIFT??????????1
+#define SMSTATEEN0_FCSR????????????????????????(_ULL(1) <<
SMSTATEEN0_FCSR_SHIFT)
include/sbi/riscv_encoding.h +2 -0
+#define SMSTATEEN0_IMSIC_SHIFT?????????58
+#define SMSTATEEN0_IMSIC???????????????(_ULL(1) <<
SMSTATEEN0_IMSIC_SHIFT)
include/sbi/riscv_encoding.h +2 -0
+#define SMSTATEEN0_AIA_SHIFT???????????59
+#define SMSTATEEN0_AIA?????????????????(_ULL(1) <<
SMSTATEEN0_AIA_SHIFT)
include/sbi/riscv_encoding.h +2 -0
+#define SMSTATEEN0_SVSLCT_SHIFT????????????????60
+#define SMSTATEEN0_SVSLCT??????????????(_ULL(1) <<
SMSTATEEN0_SVSLCT_SHIFT)
include/sbi/riscv_encoding.h +2 -0
+#define SMSTATEEN0_HSENVCFG_SHIFT??????62
+#define SMSTATEEN0_HSENVCFG????????????(_ULL(1) <<
SMSTATEEN0_HSENVCFG_SHIFT)
include/sbi/riscv_encoding.h +2 -0
+#define SMSTATEEN_STATEN_SHIFT?????????63
+#define SMSTATEEN_STATEN???????????????(_ULL(1) <<
SMSTATEEN_STATEN_SHIFT)
+
?/* ===== Instruction Encodings ===== */
?
?#define INSN_MATCH_LB??????????????????0x3
Signature · 1 line
2.17.1

Anup Patel

Applied

2022-04-11 03:11 UTC #3 lore raw

PATCH v3 1/3 lib: sbi: Add Smstateen extension defines

In reply to Mayuresh Chitale

Quoted 6 lines · Mayuresh Chitale

Smstateen extension provides a mechanism to plug potential covert channels which are opened by extensions that add to processor state that may not get context-switched.
Signed-off-by Mayuresh Chitale <[email protected]>

Looks good to me.

Reviewed-by Anup Patel <[email protected]>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

Quoted 88 lines

---
 include/sbi/riscv_encoding.h | 44 ++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

include/sbi/riscv_encoding.h +44 -1

index c02aa8f..04d5621 100644
@@ -345,6 +345,12 @@
 #define CSR_SIEH                       0x114
 #define CSR_SIPH                       0x154
 
+/* Supervisor stateen CSRs */
+#define CSR_SSTATEEN0                  0x10C
+#define CSR_SSTATEEN1                  0x10D
+#define CSR_SSTATEEN2                  0x10E
+#define CSR_SSTATEEN3                  0x10F
+
 /* ===== Hypervisor-level CSRs ===== */
 
 /* Hypervisor Trap Setup (H-extension) */

@@ -413,6 +419,16 @@
 #define CSR_VSIEH                      0x214
 #define CSR_VSIPH                      0x254
 
+/* Hypervisor stateen CSRs */
+#define CSR_HSTATEEN0                  0x60C
+#define CSR_HSTATEEN0H                 0x61C
+#define CSR_HSTATEEN1                  0x60D
+#define CSR_HSTATEEN1H                 0x61D
+#define CSR_HSTATEEN2                  0x60E
+#define CSR_HSTATEEN2H                 0x61E
+#define CSR_HSTATEEN3                  0x60F
+#define CSR_HSTATEEN3H                 0x61F
+
 /* ===== Machine-level CSRs ===== */
 
 /* Machine Information Registers */

@@ -686,6 +702,17 @@
 #define CSR_MVIEN                      0x308
 #define CSR_MVIP                       0x309
 
+/* Smstateen extension registers */
+/* Machine stateen CSRs */
+#define CSR_MSTATEEN0                  0x30C
+#define CSR_MSTATEEN0H                 0x31C
+#define CSR_MSTATEEN1                  0x30D
+#define CSR_MSTATEEN1H                 0x31D
+#define CSR_MSTATEEN2                  0x30E
+#define CSR_MSTATEEN2H                 0x31E
+#define CSR_MSTATEEN3                  0x30F
+#define CSR_MSTATEEN3H                 0x31F
+
 /* Machine-Level High-Half CSRs (AIA) */
 #define CSR_MIDELEGH                   0x313
 #define CSR_MIEH                       0x314

@@ -715,6 +742,23 @@
 #define CAUSE_VIRTUAL_INST_FAULT       0x16
 #define CAUSE_STORE_GUEST_PAGE_FAULT   0x17
 
+/* Common defines for all smstateen */
+#define SMSTATEEN_MAX_COUNT            4
+#define SMSTATEEN0_CS_SHIFT            0
+#define SMSTATEEN0_CS                  (_ULL(1) << SMSTATEEN0_CS_SHIFT)
+#define SMSTATEEN0_FCSR_SHIFT          1
+#define SMSTATEEN0_FCSR                        (_ULL(1) << SMSTATEEN0_FCSR_SHIFT)
+#define SMSTATEEN0_IMSIC_SHIFT         58
+#define SMSTATEEN0_IMSIC               (_ULL(1) << SMSTATEEN0_IMSIC_SHIFT)
+#define SMSTATEEN0_AIA_SHIFT           59
+#define SMSTATEEN0_AIA                 (_ULL(1) << SMSTATEEN0_AIA_SHIFT)
+#define SMSTATEEN0_SVSLCT_SHIFT                60
+#define SMSTATEEN0_SVSLCT              (_ULL(1) << SMSTATEEN0_SVSLCT_SHIFT)
+#define SMSTATEEN0_HSENVCFG_SHIFT      62
+#define SMSTATEEN0_HSENVCFG            (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
+#define SMSTATEEN_STATEN_SHIFT         63
+#define SMSTATEEN_STATEN               (_ULL(1) << SMSTATEEN_STATEN_SHIFT)
+
 /* ===== Instruction Encodings ===== */
 
 #define INSN_MATCH_LB                  0x3
--

2.17.1

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opensbi at lists.infradead.org
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Mayuresh Chitale

author

2022-04-06 16:57 UTC #4 lore raw

PATCH v3 2/3 lib: sbi: Detect Smstateen CSRs at boot-time

In reply to Mayuresh Chitale

Extend HART feature detection to discover Smstateen CSRs at boot-time and configure mstateen envcfg bit depending on availability of menvcfg CSR.

Signed-off-by Mayuresh Chitale <[email protected]>

---
 include/sbi/sbi_hart.h |  4 +++-
 lib/sbi/sbi_hart.c     | 25 +++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 1 deletion(-)

include/sbi/sbi_hart.h +3 -1

index 57f80bc..be3ad9f 100644
@@ -28,9 +28,11 @@ enum sbi_hart_features {
 	SBI_HART_HAS_AIA = (1 << 5),
 	/** HART has menvcfg CSR */
 	SBI_HART_HAS_MENVCFG = (1 << 6),
+	/** HART has mstateen CSR **/
+	SBI_HART_HAS_SMSTATEEN = (1 << 7),
 
 	/** Last index of Hart features*/
-	SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_MENVCFG,
+	SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_SMSTATEEN,
 };
 
 struct sbi_scratch;

lib/sbi/sbi_hart.c +25 -0

index 6be9286..b0edf38 100644
@@ -43,6 +43,7 @@ static void mstatus_init(struct sbi_scratch *scratch)
 	int cidx;
 	unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
 	uint64_t mhpmevent_init_val = 0;
+	uint64_t mstateen_val;
 
 	/* Enable FPU */
 	if (misa_extension('D') || misa_extension('F'))

@@ -87,6 +88,22 @@ static void mstatus_init(struct sbi_scratch *scratch)
 #endif
 	}
 
+	if (sbi_hart_has_feature(scratch, SBI_HART_HAS_SMSTATEEN)) {
+		mstateen_val = csr_read(CSR_MSTATEEN0);
+#if __riscv_xlen == 32
+		mstateen_val |= ((uint64_t)csr_read(CSR_MSTATEEN0H)) << 32;
+#endif
+		mstateen_val |= SMSTATEEN_STATEN;
+		if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG))
+			mstateen_val |= SMSTATEEN0_HSENVCFG;
+		else
+			mstateen_val &= ~SMSTATEEN0_HSENVCFG;
+		csr_write(CSR_MSTATEEN0, mstateen_val);
+#if __riscv_xlen == 32
+		csr_write(CSR_MSTATEEN0H, mstateen_val >> 32);
+#endif
+	}
+
 	if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG)) {
 		menvcfg_val = csr_read(CSR_MENVCFG);

@@ -348,6 +365,9 @@ static inline char *sbi_hart_feature_id2string(unsigned long feature)
 	case SBI_HART_HAS_MENVCFG:
 		fstr = "menvcfg";
 		break;
+	case SBI_HART_HAS_SMSTATEEN:
+		fstr = "smstateen";
+		break;
 	default:
 		break;
 	}

@@ -584,6 +604,11 @@ __aia_skip:
 	if (!trap.cause)
 		hfeatures->features |= SBI_HART_HAS_MENVCFG;
 
+	/* Detect if hart supports mstateen CSRs */
+	val = csr_read_allowed(CSR_MSTATEEN0, (unsigned long)&trap);
+	if (!trap.cause)
+		hfeatures->features |= SBI_HART_HAS_SMSTATEEN;
+
 	return;
 }

Signature · 1 line

2.17.1

Xiang W

2022-04-07 09:54 UTC #5 lore raw

PATCH v3 2/3 lib: sbi: Detect Smstateen CSRs at boot-time

? 2022-04-06???? 22:27 +0530?Mayuresh Chitale???

Quoted 5 lines

Extend HART feature detection to discover Smstateen CSRs at boot-time and configure mstateen envcfg bit depending on availability of menvcfg CSR.
Signed-off-by Mayuresh Chitale <[email protected]>

Look good to me

Reviewed-by Xiang W <[email protected]>

Quoted 88 lines

---
?include/sbi/sbi_hart.h |? 4 +++- ?lib/sbi/sbi_hart.c???? | 25 +++++++++++++++++++++++++ ?2 files changed, 28 insertions(+), 1 deletion(-)
include/sbi/sbi_hart.h +0 -0
index 57f80bc..be3ad9f 100644
@@ -28,9 +28,11 @@ enum sbi_hart_features {
 ????????SBI_HART_HAS_AIA = (1 << 5),
????????/** HART has menvcfg CSR */ ????????SBI_HART_HAS_MENVCFG = (1 << 6), +???????/** HART has mstateen CSR **/ +???????SBI_HART_HAS_SMSTATEEN = (1 << 7),
?
????????/** Last index of Hart features*/ -???????SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_MENVCFG, +???????SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_SMSTATEEN, ?};
?
?struct sbi_scratch;
lib/sbi/sbi_hart.c +1 -0
index 6be9286..b0edf38 100644
@@ -43,6 +43,7 @@ static void mstatus_init(struct sbi_scratch
 *scratch)
 ????????int cidx;
 ????????unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
 ????????uint64_t mhpmevent_init_val = 0;
+???????uint64_t mstateen_val;
?
????????/* Enable FPU */
????????if (misa_extension('D') || misa_extension('F'))
lib/sbi/sbi_hart.c +0 -0
@@ -87,6 +88,22 @@ static void mstatus_init(struct sbi_scratch
 *scratch)
?#endif
????????}
?
+???????if (sbi_hart_has_feature(scratch, SBI_HART_HAS_SMSTATEEN)) { +???????????????mstateen_val = csr_read(CSR_MSTATEEN0); +#if __riscv_xlen == 32
+???????????????mstateen_val |= ((uint64_t)csr_read(CSR_MSTATEEN0H)) << 32;
+#endif
+???????????????mstateen_val |= SMSTATEEN_STATEN; +???????????????if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG)) +???????????????????????mstateen_val |= SMSTATEEN0_HSENVCFG; +???????????????else
+???????????????????????mstateen_val &= ~SMSTATEEN0_HSENVCFG; +???????????????csr_write(CSR_MSTATEEN0, mstateen_val);
lib/sbi/sbi_hart.c +5 -0
+#if __riscv_xlen == 32
+???????????????csr_write(CSR_MSTATEEN0H, mstateen_val >> 32);
+#endif
+???????}
+
????????if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG)) { ????????????????menvcfg_val = csr_read(CSR_MENVCFG);
?
lib/sbi/sbi_hart.c +0 -0
@@ -348,6 +365,9 @@ static inline char
 *sbi_hart_feature_id2string(unsigned long feature)
????????case SBI_HART_HAS_MENVCFG:
????????????????fstr = "menvcfg";
????????????????break;
+???????case SBI_HART_HAS_SMSTATEEN:
+???????????????fstr = "smstateen";
+???????????????break;
????????default:
????????????????break;
????????}
lib/sbi/sbi_hart.c +0 -0
@@ -584,6 +604,11 @@ __aia_skip:
 ????????if (!trap.cause)
 ????????????????hfeatures->features |= SBI_HART_HAS_MENVCFG;
?
+???????/* Detect if hart supports mstateen CSRs */ +???????val = csr_read_allowed(CSR_MSTATEEN0, (unsigned long)&trap); +???????if (!trap.cause) +???????????????hfeatures->features |= SBI_HART_HAS_SMSTATEEN; +
????????return;
?}
?
Signature · 1 line
2.17.1

Anup Patel

Applied

2022-04-11 03:12 UTC #6 lore raw

PATCH v3 2/3 lib: sbi: Detect Smstateen CSRs at boot-time

In reply to Mayuresh Chitale

Quoted 6 lines · Mayuresh Chitale

Extend HART feature detection to discover Smstateen CSRs at boot-time and configure mstateen envcfg bit depending on availability of menvcfg CSR.
Signed-off-by Mayuresh Chitale <[email protected]>

Looks good to me.

Reviewed-by Anup Patel <[email protected]>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

Quoted 87 lines

---
 include/sbi/sbi_hart.h |  4 +++-
 lib/sbi/sbi_hart.c     | 25 +++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 1 deletion(-)

include/sbi/sbi_hart.h +3 -1

index 57f80bc..be3ad9f 100644
@@ -28,9 +28,11 @@ enum sbi_hart_features {
        SBI_HART_HAS_AIA = (1 << 5),
        /** HART has menvcfg CSR */
        SBI_HART_HAS_MENVCFG = (1 << 6),
+       /** HART has mstateen CSR **/
+       SBI_HART_HAS_SMSTATEEN = (1 << 7),
 
        /** Last index of Hart features*/
-       SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_MENVCFG,
+       SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_SMSTATEEN,
 };
 
 struct sbi_scratch;

lib/sbi/sbi_hart.c +25 -1

index 6be9286..b0edf38 100644
@@ -43,6 +43,7 @@ static void mstatus_init(struct sbi_scratch *scratch)
        int cidx;
        unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
        uint64_t mhpmevent_init_val = 0;
+       uint64_t mstateen_val;
 
        /* Enable FPU */
        if (misa_extension('D') || misa_extension('F'))

@@ -87,6 +88,22 @@ static void mstatus_init(struct sbi_scratch *scratch)
 #endif
        }
 
+       if (sbi_hart_has_feature(scratch, SBI_HART_HAS_SMSTATEEN)) {
+               mstateen_val = csr_read(CSR_MSTATEEN0);
+#if __riscv_xlen == 32
+               mstateen_val |= ((uint64_t)csr_read(CSR_MSTATEEN0H)) << 32;
+#endif
+               mstateen_val |= SMSTATEEN_STATEN;
+               if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG))
+                       mstateen_val |= SMSTATEEN0_HSENVCFG;
+               else
+                       mstateen_val &= ~SMSTATEEN0_HSENVCFG;
+               csr_write(CSR_MSTATEEN0, mstateen_val);
+#if __riscv_xlen == 32
+               csr_write(CSR_MSTATEEN0H, mstateen_val >> 32);
+#endif
+       }
+
        if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG)) {
                menvcfg_val = csr_read(CSR_MENVCFG);

@@ -348,6 +365,9 @@ static inline char *sbi_hart_feature_id2string(unsigned long feature)
        case SBI_HART_HAS_MENVCFG:
                fstr = "menvcfg";
                break;
+       case SBI_HART_HAS_SMSTATEEN:
+               fstr = "smstateen";
+               break;
        default:
                break;
        }

@@ -584,6 +604,11 @@ __aia_skip:
        if (!trap.cause)
                hfeatures->features |= SBI_HART_HAS_MENVCFG;
 
+       /* Detect if hart supports mstateen CSRs */
+       val = csr_read_allowed(CSR_MSTATEEN0, (unsigned long)&trap);
+       if (!trap.cause)
+               hfeatures->features |= SBI_HART_HAS_SMSTATEEN;
+
        return;
 }
 
--

2.17.1

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Mayuresh Chitale

author

2022-04-06 16:57 UTC #7 lore raw

PATCH v3 3/3 lib: irqchip/imsic: configure mstateen

In reply to Mayuresh Chitale

When mstateen registers are implemented, the AIA related configurations need to be done in mstateen for the IMSIC initialization to succeed.

Signed-off-by Mayuresh Chitale <[email protected]>

---
 lib/sbi/sbi_hart.c | 6 ++++++
 1 file changed, 6 insertions(+)

lib/sbi/sbi_hart.c +6 -0

index b0edf38..7b602c3 100644
@@ -98,6 +98,12 @@ static void mstatus_init(struct sbi_scratch *scratch)
 			mstateen_val |= SMSTATEEN0_HSENVCFG;
 		else
 			mstateen_val &= ~SMSTATEEN0_HSENVCFG;
+		if (sbi_hart_has_feature(scratch, SBI_HART_HAS_AIA))
+			mstateen_val |= (SMSTATEEN0_AIA | SMSTATEEN0_SVSLCT |
+					SMSTATEEN0_IMSIC);
+		else
+			mstateen_val &= ~(SMSTATEEN0_AIA | SMSTATEEN0_SVSLCT |
+					SMSTATEEN0_IMSIC);
 		csr_write(CSR_MSTATEEN0, mstateen_val);
 #if __riscv_xlen == 32
 		csr_write(CSR_MSTATEEN0H, mstateen_val >> 32);

Signature · 1 line

2.17.1

Xiang W

2022-04-07 09:55 UTC #8 lore raw

PATCH v3 3/3 lib: irqchip/imsic: configure mstateen

? 2022-04-06???? 22:27 +0530?Mayuresh Chitale???

Quoted 5 lines

When mstateen registers are implemented, the AIA related configurations need to be done in mstateen for the IMSIC initialization to succeed.
Signed-off-by Mayuresh Chitale <[email protected]>

Look good to me

Reviewed-by Xiang W <[email protected]>

Quoted 28 lines

---
?lib/sbi/sbi_hart.c | 6 ++++++
?1 file changed, 6 insertions(+)
lib/sbi/sbi_hart.c +0 -0
index b0edf38..7b602c3 100644
@@ -98,6 +98,12 @@ static void mstatus_init(struct sbi_scratch
 *scratch)
 ????????????????????????mstateen_val |= SMSTATEEN0_HSENVCFG;
????????????????else
????????????????????????mstateen_val &= ~SMSTATEEN0_HSENVCFG; +???????????????if (sbi_hart_has_feature(scratch, SBI_HART_HAS_AIA)) +???????????????????????mstateen_val |= (SMSTATEEN0_AIA | SMSTATEEN0_SVSLCT | +???????????????????????????????????????SMSTATEEN0_IMSIC); +???????????????else
+???????????????????????mstateen_val &= ~(SMSTATEEN0_AIA | SMSTATEEN0_SVSLCT | +???????????????????????????????????????SMSTATEEN0_IMSIC); ????????????????csr_write(CSR_MSTATEEN0, mstateen_val); ?#if __riscv_xlen == 32 ????????????????csr_write(CSR_MSTATEEN0H, mstateen_val >> 32);
Signature · 1 line
2.17.1

Anup Patel

Applied

2022-04-11 03:12 UTC #9 lore raw

PATCH v3 3/3 lib: irqchip/imsic: configure mstateen

In reply to Mayuresh Chitale

Quoted 6 lines · Mayuresh Chitale

When mstateen registers are implemented, the AIA related configurations need to be done in mstateen for the IMSIC initialization to succeed.
Signed-off-by Mayuresh Chitale <[email protected]>

Looks good to me.

Reviewed-by Anup Patel <[email protected]>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

Quoted 29 lines

---
 lib/sbi/sbi_hart.c | 6 ++++++
 1 file changed, 6 insertions(+)

lib/sbi/sbi_hart.c +6 -1

index b0edf38..7b602c3 100644
@@ -98,6 +98,12 @@ static void mstatus_init(struct sbi_scratch *scratch)
                        mstateen_val |= SMSTATEEN0_HSENVCFG;
                else
                        mstateen_val &= ~SMSTATEEN0_HSENVCFG;
+               if (sbi_hart_has_feature(scratch, SBI_HART_HAS_AIA))
+                       mstateen_val |= (SMSTATEEN0_AIA | SMSTATEEN0_SVSLCT |
+                                       SMSTATEEN0_IMSIC);
+               else
+                       mstateen_val &= ~(SMSTATEEN0_AIA | SMSTATEEN0_SVSLCT |
+                                       SMSTATEEN0_IMSIC);
                csr_write(CSR_MSTATEEN0, mstateen_val);
 #if __riscv_xlen == 32
                csr_write(CSR_MSTATEEN0H, mstateen_val >> 32);
--

2.17.1

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