x86: Trust initial offset in architectural TSC-adjust MSRs
PATCH RESEND 1/1 x86: Trust initial offset in architectural TSC-adjust MSRs
When the BIOS configures the architectural TSC-adjust MSRs on secondary sockets to correct a constant inter-chassis offset, after Linux brings the cores online, the TSC sync check later resets the core-local MSR to 0, triggering HPET fallback and leading to performance loss.
Fix this by unconditionally using the initial adjust values read from the MSRs. Trusting the initial offsets in this architectural mechanism is a better approach than special-casing workarounds for specific platforms.
Signed-off-by Daniel J Blueman <[email protected]>
Reviewed-by Steffen Persvold <[email protected]>
Reviewed-by James Cleverdon <[email protected]>
--- arch/x86/kernel/tsc_sync.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-)
arch/x86/kernel/tsc_sync.c +1 -8
@@ -188,17 +188,10 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu)return false;rdmsrl (MSR_IA32_TSC_ADJUST , bootval); - cur->bootval = bootval; + cur->adjusted = cur->bootval = bootval; cur->nextcheck = jiffies +HZ ; cur->warned = false; -/* -* If a non-zero TSC value for socket 0 may be valid then the default -* adjusted value cannot assumed to be zero either. -*/ -if (tsc_async_resets) - cur->adjusted = bootval; -/* * Check whether this CPU is the first in a package to come up. In * this case do not check the boot value against another package
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2.40.1