x86: Trust initial offset in architectural TSC-adjust MSRs
PATCH v2 1/1 x86: Trust initial offset in architectural TSC-adjust MSRs
When the BIOS configures the architectural TSC-adjust MSRs on secondary sockets to correct a constant inter-chassis offset, after Linux brings the cores online, the TSC sync check later resets the core-local MSR to 0, triggering HPET fallback and leading to performance loss.
Fix this by unconditionally using the initial adjust values read from the MSRs. Trusting the initial offsets in this architectural mechanism is a better approach than special-casing workarounds for specific platforms.
---
Changes in v2:
- Maintain comment based on feedback
- Rebase against v6.9-rc4
arch/x86/kernel/tsc_sync.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
arch/x86/kernel/tsc_sync.c +2 -4
@@ -193,11 +193,9 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu) cur->warned = false;/* -* If a non-zero TSC value for socket 0 may be valid then the default -* adjusted value cannot assumed to be zero either. +* The default adjust value cannot be assumed to be zero on any socket. */ -if (tsc_async_resets) - cur->adjusted = bootval; + cur->adjusted = bootval;/* * Check whether this CPU is the first in a package to come up. In
Signature · 1 line
2.40.1
Quoted 33 lines · Daniel J Blueman
When the BIOS configures the architectural TSC-adjust MSRs on secondary sockets to correct a constant inter-chassis offset, after Linux brings the cores online, the TSC sync check later resets the core-local MSR to 0, triggering HPET fallback and leading to performance loss.
Fix this by unconditionally using the initial adjust values read from the MSRs. Trusting the initial offsets in this architectural mechanism is a better approach than special-casing workarounds for specific platforms.
Signed-off-by Daniel J Blueman <[email protected]>Reviewed-by Steffen Persvold <[email protected]>Reviewed-by James Cleverdon <[email protected]>Reviewed-by Dimitri Sivanich <[email protected]>Cc Steve Wahl <[email protected]>Cc Prarit Bhargava <[email protected]>Cc Frank Ramsay <[email protected]>Cc Russ Anderson <[email protected]>---
Changes in v2:
- Maintain comment based on feedback
- Rebase against v6.9-rc4arch/x86/kernel/tsc_sync.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)arch/x86/kernel/tsc_sync.c +0
-0@@ -193,11 +193,9 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu) cur->warned = false;/*
arch/x86/kernel/tsc_sync.c bool tsc_store_and_check_tsc_adjust(bool bootcpu) · line 201
Quoted 10 lines
arch/x86/kernel/tsc_sync.c +2
-4-* If a non-zero TSC value for socket 0 may be valid then the default -* adjusted value cannot assumed to be zero either. +* The default adjust value cannot be assumed to be zero on any socket. */ -if (tsc_async_resets) - cur->adjusted = bootval; + cur->adjusted = bootval;/* * Check whether this CPU is the first in a package to come up. In
This covers the concerns raise by HPE (cc'd) on this patch.
P.
[tip: x86/timers] x86/tsc: Trust initial offset in architectural TSC-adjust MSRs
In reply to Daniel J BluemanThe following commit has been merged into the x86/timers branch of tip:
The following commit has been merged into the x86/timers branch of tip:
Commit-ID: 455f9075f14484f358b3c1d6845b4a438de198a7 Gitweb: https://git.kernel.org/tip/455f9075f14484f358b3c1d6845b4a438de198a7 Author: Daniel J Blueman <[email protected]> AuthorDate: Fri, 19 Apr 2024 16:51:46 +08:00 Committer: Thomas Gleixner <[email protected]> CommitterDate: Mon, 29 Apr 2024 23:27:16 +02:00
x86/tsc: Trust initial offset in architectural TSC-adjust MSRs
When the BIOS configures the architectural TSC-adjust MSRs on secondary sockets to correct a constant inter-chassis offset, after Linux brings the cores online, the TSC sync check later resets the core-local MSR to 0, triggering HPET fallback and leading to performance loss.
Fix this by unconditionally using the initial adjust values read from the MSRs. Trusting the initial offsets in this architectural mechanism is a better approach than special-casing workarounds for specific platforms.
--- arch/x86/kernel/tsc_sync.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
arch/x86/kernel/tsc_sync.c +2 -4
@@ -193,11 +193,9 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu) cur->warned = false;/* -* If a non-zero TSC value for socket 0 may be valid then the default -* adjusted value cannot assumed to be zero either. +* The default adjust value cannot be assumed to be zero on any socket. */ -if (tsc_async_resets) - cur->adjusted = bootval; + cur->adjusted = bootval;/* * Check whether this CPU is the first in a package to come up. In