ARM: dts: aspeed: Add IBM P11 BMC systems
Subsystems (8)
Eddie James
maintainerv6 cover ARM: dts: aspeed: Add IBM P11 BMC systems
Add the Blueridge and Fuji BMC systems. Document many missing FSI related properties, and fix existing warnings. Make some minor fixes in OCC and SCOM drivers for the updated bindings.
Changes since v5:
- Switch from clock-frequency to bus-frequency for common FSI controller properties
- Add reg properties for AST2700 FSI controller
- Fix patternProperties for i2c bus nodes under FSI-based I2C controller
- Add bus-frequency for P11 FSI device tree node
- Change model name from Blueridge to Blueridge 2U
- Add missing reset gpio to led controller on Fuji
- Add Huygens (Rainier with modified FSI wiring)
Eddie James (20):
spi: dt-bindings: Document the IBM FSI-attached SPI controller
dt-bindings: fsi: fsi2spi: Document SPI controller child nodes
dt-bindings: fsi: Document the IBM SCOM engine
dt-bindings: fsi: p9-occ: Convert to json-schema
dt-bindings: fsi: Document the IBM SBEFIFO engine
dt-bindings: fsi: Document the FSI controller common properties
dt-bindings: fsi: ibm,i2cr-fsi-master: Reference common FSI controller
dt-bindings: fsi: ast2600-fsi-master: Convert to json-schema
dt-bindings: fsi: Document the AST2700 FSI controller
dt-bindings: fsi: Document the FSI Hub Controller
dt-bindings: i2c: i2c-fsi: Convert to json-schema
dt-bindings: arm: aspeed: add IBM P11 BMC boards
ARM: dts: aspeed: Add IBM P11 FSI devices
ARM: dts: aspeed: Add IBM P11 Blueridge BMC system
ARM: dts: aspeed: Add IBM P11 Blueridge 4U BMC system
ARM: dts: aspeed: Add IBM P11 Fuji BMC system
ARM: dts: aspeed: Add IBM Huygens BMC system
fsi: occ: Get device number from FSI minor number API
fsi: occ: Find next available child rather than node name match
fsi: scom: Update compatible string to match documentation
.../bindings/arm/aspeed/aspeed.yaml | 2 + .../fsi/aspeed,ast2600-fsi-master.yaml | 121 + .../bindings/fsi/fsi-controller.yaml | 66 + .../bindings/fsi/fsi-master-aspeed.txt | 36 - .../devicetree/bindings/fsi/ibm,fsi2spi.yaml | 36 +- .../bindings/fsi/ibm,i2cr-fsi-master.yaml | 5 +- .../bindings/fsi/ibm,p9-fsi-controller.yaml | 45 + .../devicetree/bindings/fsi/ibm,p9-occ.txt | 16 - .../devicetree/bindings/fsi/ibm,p9-occ.yaml | 40 + .../bindings/fsi/ibm,p9-sbefifo.yaml | 46 + .../devicetree/bindings/fsi/ibm,p9-scom.yaml | 37 + .../devicetree/bindings/i2c/i2c-fsi.txt | 40 - .../devicetree/bindings/i2c/ibm,i2c-fsi.yaml | 76 + .../devicetree/bindings/spi/ibm,spi-fsi.yaml | 55 + MAINTAINERS | 2 +- arch/arm/boot/dts/aspeed/Makefile | 3 + .../aspeed/aspeed-bmc-ibm-blueridge-4u.dts | 21 + .../dts/aspeed/aspeed-bmc-ibm-blueridge.dts | 1691 +++++++ .../boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts | 3881 +++++++++++++++++ .../dts/aspeed/aspeed-bmc-ibm-huygens.dts | 23 + .../arm/boot/dts/aspeed/ibm-power11-quad.dtsi | 1539 +++++++ drivers/fsi/fsi-occ.c | 49 +- drivers/fsi/fsi-scom.c | 1 + 23 files changed, 7694 insertions(+), 137 deletions(-) create mode 100644 Documentation/devicetree/bindings/fsi/aspeed,ast2600-fsi-master.yaml create mode 100644 Documentation/devicetree/bindings/fsi/fsi-controller.yaml delete mode 100644 Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txt create mode 100644 Documentation/devicetree/bindings/fsi/ibm,p9-fsi-controller.yaml delete mode 100644 Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt create mode 100644 Documentation/devicetree/bindings/fsi/ibm,p9-occ.yaml create mode 100644 Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.yaml create mode 100644 Documentation/devicetree/bindings/fsi/ibm,p9-scom.yaml delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-fsi.txt create mode 100644 Documentation/devicetree/bindings/i2c/ibm,i2c-fsi.yaml create mode 100644 Documentation/devicetree/bindings/spi/ibm,spi-fsi.yaml create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge-4u.dts create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-huygens.dts create mode 100644 arch/arm/boot/dts/aspeed/ibm-power11-quad.dtsi
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 1/20 spi: dt-bindings: Document the IBM FSI-attached SPI controller
IBM Power processors have a SPI controller that can be accessed over FSI from a service processor. Document it.
--- .../devicetree/bindings/spi/ibm,spi-fsi.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/ibm,spi-fsi.yaml
Documentation/devicetree/bindings/spi/ibm,spi-fsi.yaml new file +55 -0
@@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/ibm,spi-fsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached SPI Controller + +maintainers: + - Eddie James <[email protected]> + +description: + A SPI controller found on IBM Power processors, accessed over FSI from a + service processor. This node will always be a child node of an ibm,fsi2spi + node. + +properties: + compatible: + enum: + - ibm,spi-fsi + + reg: + maxItems: 1 + +required: + - compatible + - reg + +allOf: + - $ref: spi-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + fsi { + #address-cells = <1>; + #size-cells = <0>; + + spi at 0 { + compatible = "ibm,spi-fsi"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + size = <0x80000>; + address-width = <24>; + pagesize = <256>; + spi-max-frequency = <1000000>; + }; + }; + };
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 2/20 dt-bindings: fsi: fsi2spi: Document SPI controller child nodes
In reply to Eddie JamesThe FSI2SPI bridge has several SPI controllers behind it, which should be documented. Also, therefore the node needs to specify address and size cells.
--- .../devicetree/bindings/fsi/ibm,fsi2spi.yaml | 36 ++++++++++++++++--- 1 file changed, 32 insertions(+), 4 deletions(-)
Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml +32 -4
@@ -9,11 +9,10 @@ title: IBM FSI-attached SPI controllers maintainers: - Eddie James <[email protected]> -description: | +description: This binding describes an FSI CFAM engine called the FSI2SPI. Therefore this - node will always be a child of an FSI CFAM node; see fsi.txt for details on - FSI slave and CFAM nodes. This FSI2SPI engine provides access to a number of - SPI controllers. + node will always be a child of an FSI CFAM node. This FSI2SPI engine provides + access to a number of SPI controllers. properties: compatible:
@@ -24,6 +23,17 @@ properties: items: - description: FSI slave address + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^spi@[0-9a-f]+$": + type: object + $ref: /schemas/spi/ibm,spi-fsi.yaml + required: - compatible - reg
@@ -35,4 +45,22 @@ examples: fsi2spi at 1c00 { compatible = "ibm,fsi2spi"; reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + spi at 0 { + compatible = "ibm,spi-fsi"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <1000000>; + }; + }; };
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 3/20 dt-bindings: fsi: Document the IBM SCOM engine
In reply to Eddie JamesThe SCOM engine provides an interface to the POWER processor PIB (Pervasive Interconnect Bus).
--- .../devicetree/bindings/fsi/ibm,p9-scom.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/fsi/ibm,p9-scom.yaml
Documentation/devicetree/bindings/fsi/ibm,p9-scom.yaml new file +37 -0
@@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/ibm,p9-scom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached SCOM engine + +maintainers: + - Eddie James <[email protected]> + +description: + The SCOM engine is an interface to the POWER processor PIB (Pervasive + Interconnect Bus). This node will always be a child of an FSI CFAM node. + +properties: + compatible: + enum: + - ibm,p9-scom + - ibm,i2cr-scom + + reg: + items: + - description: FSI slave address + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + scom at 1000 { + compatible = "ibm,p9-scom"; + reg = <0x1000 0x400>; + };
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 4/20 dt-bindings: fsi: p9-occ: Convert to json-schema
In reply to Eddie JamesConver to json-schema for the OCC documentation. Also document the fact that the OCC "bridge" device will often have the hwmon node as a child.
--- .../devicetree/bindings/fsi/ibm,p9-occ.txt | 16 -------- .../devicetree/bindings/fsi/ibm,p9-occ.yaml | 40 +++++++++++++++++++ 2 files changed, 40 insertions(+), 16 deletions(-) delete mode 100644 Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt create mode 100644 Documentation/devicetree/bindings/fsi/ibm,p9-occ.yaml
Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt deleted +0 -16
@@ -1,16 +0,0 @@ -Device-tree bindings for FSI-attached POWER9/POWER10 On-Chip Controller (OCC) ------------------------------------------------------------------------------ - -This is the binding for the P9 or P10 On-Chip Controller accessed over FSI from -a service processor. See fsi.txt for details on bindings for FSI slave and CFAM -nodes. The OCC is not an FSI slave device itself, rather it is accessed -through the SBE FIFO. - -Required properties: - - compatible = "ibm,p9-occ" or "ibm,p10-occ" - -Examples: - - occ { - compatible = "ibm,p9-occ"; - };
Documentation/devicetree/bindings/fsi/ibm,p9-occ.yaml new file +40 -0
@@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/ibm,p9-occ.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached On-Chip Controller (OCC) + +maintainers: + - Eddie James <[email protected]> + +description: + The POWER processor On-Chip Controller (OCC) helps manage power and + thermals for the system, accessed through the FSI-attached SBEFIFO + from a service processor. + +properties: + compatible: + enum: + - ibm,p9-occ + - ibm,p10-occ + + hwmon: + type: object + $ref: /schemas/hwmon/ibm,occ-hwmon.yaml + +required: + - compatible + +additionalProperties: false + +examples: + - | + occ { + compatible = "ibm,p9-occ"; + + hwmon { + compatible = "ibm,p9-occ-hwmon"; + }; + };
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 5/20 dt-bindings: fsi: Document the IBM SBEFIFO engine
In reply to Eddie JamesThe SBEFIFO engine provides an interface to the POWER processor Self Boot Engine (SBE).
--- .../bindings/fsi/ibm,p9-sbefifo.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.yaml
Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.yaml new file +46 -0
@@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/ibm,p9-sbefifo.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached SBEFIFO engine + +maintainers: + - Eddie James <[email protected]> + +description: + The SBEFIFO is an FSI CFAM engine that provides an interface to the + POWER processor Self Boot Engine (SBE). This node will always be a child + of an FSI CFAM node. + +properties: + compatible: + enum: + - ibm,p9-sbefifo + - ibm,odyssey-sbefifo + + reg: + items: + - description: FSI slave address + + occ: + type: object + $ref: ibm,p9-occ.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + fsi-slave-engine at 2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + + occ { + compatible = "ibm,p9-occ"; + }; + };
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 6/20 dt-bindings: fsi: Document the FSI controller common properties
In reply to Eddie JamesSince there are multiple FSI controllers documented, the common properties should be documented separately and then referenced from the specific controller documentation. Add bus-frequency for the FSI bus and CFAM local bus frequencies. Add interrupt controller properties.
---
Changes since v5:
- Switch from clock-frequency to bus-frequency
.../bindings/fsi/fsi-controller.yaml | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/fsi/fsi-controller.yaml
Documentation/devicetree/bindings/fsi/fsi-controller.yaml new file +66 -0
@@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/fsi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FSI Controller Common Properties + +maintainers: + - Eddie James <[email protected]> + +description: + FSI (FRU (Field Replaceable Unit) Service Interface) is a two wire bus. The + FSI bus is connected to a CFAM (Common FRU Access Macro) which contains + various engines such as I2C controllers, SPI controllers, etc. + +properties: + "#address-cells": + const: 2 + + "#size-cells": + const: 0 + + '#interrupt-cells': + const: 1 + + bus-frequency: + minimum: 1 + maximum: 200000000 + + interrupt-controller: true + + no-scan-on-init: + $ref: /schemas/types.yaml#/definitions/flag + description: + The FSI controller cannot scan the bus during initialization. + +patternProperties: + "cfam@[0-9a-f],[0-9a-f]": + type: object + properties: + chip-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Processor index, a global unique chip ID which is used to identify + the physical location of the chip in a system specific way. + + bus-frequency: + minimum: 1 + maximum: 100000000 + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + required: + - reg + + additionalProperties: true + +additionalProperties: true
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 7/20 dt-bindings: fsi: ibm,i2cr-fsi-master: Reference common FSI controller
In reply to Eddie JamesRemove the common properties from the I2CR documentation and instead point to the common FSI controller documentation.
--- .../devicetree/bindings/fsi/ibm,i2cr-fsi-master.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/fsi/ibm,i2cr-fsi-master.yaml +4 -1
@@ -26,7 +26,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: fsi-controller.yaml# + +unevaluatedProperties: false examples: - |
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 8/20 dt-bindings: fsi: ast2600-fsi-master: Convert to json-schema
In reply to Eddie JamesConvert to json-schema for the AST2600 FSI master documentation.
--- .../fsi/aspeed,ast2600-fsi-master.yaml | 80 +++++++++++++++++++ .../bindings/fsi/fsi-master-aspeed.txt | 36 --------- 2 files changed, 80 insertions(+), 36 deletions(-) create mode 100644 Documentation/devicetree/bindings/fsi/aspeed,ast2600-fsi-master.yaml delete mode 100644 Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txt
Documentation/devicetree/bindings/fsi/aspeed,ast2600-fsi-master.yaml new file +80 -0
@@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed FSI master + +maintainers: + - Eddie James <[email protected]> + +description: + The AST2600 and later contain two identical FSI masters. They share a + clock and have a separate interrupt line and output pins. + +properties: + compatible: + enum: + - aspeed,ast2600-fsi-master + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + cfam-reset-gpios: + maxItems: 1 + description: + Output GPIO pin for CFAM reset + + fsi-routing-gpios: + maxItems: 1 + description: + Output GPIO pin for setting the FSI mux (internal or cabled) + + fsi-mux-gpios: + maxItems: 1 + description: + Input GPIO pin for detecting the desired FSI mux state + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +allOf: + - $ref: fsi-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/ast2600-clock.h> + #include <dt-bindings/gpio/aspeed-gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + fsi-master at 1e79b000 { + compatible = "aspeed,ast2600-fsi-master"; + reg = <0x1e79b000 0x94>; + #address-cells = <2>; + #size-cells = <0>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi1_default>; + clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; + fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; + fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; + cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + }; + };
Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txt deleted +0 -36
@@ -1,36 +0,0 @@ -Device-tree bindings for AST2600 FSI master -------------------------------------------- - -The AST2600 contains two identical FSI masters. They share a clock and have a -separate interrupt line and output pins. - -Required properties: - - compatible: "aspeed,ast2600-fsi-master" - - reg: base address and length - - clocks: phandle and clock number - - interrupts: platform dependent interrupt description - - pinctrl-0: phandle to pinctrl node - - pinctrl-names: pinctrl state - -Optional properties: - - cfam-reset-gpios: GPIO for CFAM reset - - - fsi-routing-gpios: GPIO for setting the FSI mux (internal or cabled) - - fsi-mux-gpios: GPIO for detecting the desired FSI mux state - - -Examples: - - fsi-master { - compatible = "aspeed,ast2600-fsi-master", "fsi-master"; - reg = <0x1e79b000 0x94>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fsi1_default>; - clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; - - fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; - fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; - - cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - };
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 9/20 dt-bindings: fsi: Document the AST2700 FSI controller
In reply to Eddie JamesAdd the appropriate compatible string, and document the new reg properties of the AST2700 FSI controller, which can directly access the FSI controller registers as well as the FSI link address space.
---
Changes since v5:
- Add the AST2700-specific regs properties since that controller can map the FSI control registers and FSI link space.
.../fsi/aspeed,ast2600-fsi-master.yaml | 47 +++++++++++++++++-- 1 file changed, 44 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/fsi/aspeed,ast2600-fsi-master.yaml +44 -3
@@ -17,9 +17,7 @@ properties: compatible: enum: - aspeed,ast2600-fsi-master - - reg: - maxItems: 1 + - aspeed,ast2700-fsi-master clocks: maxItems: 1
@@ -42,6 +40,30 @@ properties: interrupts: maxItems: 1 +if: + properties: + compatible: + contains: + enum: + - aspeed,ast2600-fsi-master +then: + properties: + reg: + maxItems: 1 +else: + properties: + reg: + minItems: 1 + items: + - description: OPB control registers + - description: FSI controller registers + - description: FSI link address space + reg-names: + items: + - const: opb + - const: ctrl + - const: fsi + required: - compatible - reg
@@ -78,3 +100,22 @@ examples: chip-id = <0>; }; }; + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + fsi-master at 21800000 { + compatible = "aspeed,ast2700-fsi-master"; + reg = <0x0 0x21800000 0x0 0x100>, + <0x0 0x21000000 0x0 0x1000>, + <0x0 0x20000000 0x0 0x1000000>; + reg-names = "opb", "ctrl", "fsi"; + #interrupt-cells = <1>; + interrupt-controller; + interrupts-extended = <&intc 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi0_default>; + clocks = <&syscon 40>; + }; + };
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 10/20 dt-bindings: fsi: Document the FSI Hub Controller
In reply to Eddie JamesDocument the FSI Hub Controller CFAM engine.
--- .../bindings/fsi/ibm,p9-fsi-controller.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/fsi/ibm,p9-fsi-controller.yaml
Documentation/devicetree/bindings/fsi/ibm,p9-fsi-controller.yaml new file +45 -0
@@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/ibm,p9-fsi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached FSI Hub Controller + +maintainers: + - Eddie James <[email protected]> + +description: + The FSI Hub Controller is an FSI controller, providing a number of FSI links, + located on a CFAM. Therefore this node will always be a child of an FSI CFAM + node. + +properties: + compatible: + enum: + - ibm,p9-fsi-controller + + reg: + items: + - description: FSI slave address + +allOf: + - $ref: fsi-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + fsi at 3400 { + compatible = "ibm,p9-fsi-controller"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + }; + };
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 11/20 dt-bindings: i2c: i2c-fsi: Convert to json-schema
In reply to Eddie JamesConvert to json-schema for the FSI-attached I2C controller.
---
Changes since v5:
- Use more specific regex for node names
.../devicetree/bindings/i2c/i2c-fsi.txt | 40 ---------- .../devicetree/bindings/i2c/ibm,i2c-fsi.yaml | 76 +++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 77 insertions(+), 41 deletions(-) delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-fsi.txt create mode 100644 Documentation/devicetree/bindings/i2c/ibm,i2c-fsi.yaml
Documentation/devicetree/bindings/i2c/i2c-fsi.txt deleted +0 -40
@@ -1,40 +0,0 @@ -Device-tree bindings for FSI-attached I2C master and busses ------------------------------------------------------------ - -Required properties: - - compatible = "ibm,i2c-fsi"; - - reg = < address size >; : The FSI CFAM address and address - space size. - - #address-cells = <1>; : Number of address cells in child - nodes. - - #size-cells = <0>; : Number of size cells in child nodes. - - child nodes : Nodes to describe busses off the I2C - master. - -Child node required properties: - - reg = < port number > : The port number on the I2C master. - -Child node optional properties: - - child nodes : Nodes to describe devices on the I2C - bus. - -Examples: - - i2c at 1800 { - compatible = "ibm,i2c-fsi"; - reg = < 0x1800 0x400 >; - #address-cells = <1>; - #size-cells = <0>; - - i2c-bus at 0 { - reg = <0>; - }; - - i2c-bus at 1 { - reg = <1>; - - eeprom at 50 { - compatible = "vendor,dev-name"; - }; - }; - };
Documentation/devicetree/bindings/i2c/ibm,i2c-fsi.yaml new file +76 -0
76 lines not on this page · raw message
MAINTAINERS +1 -1
@@ -8977,7 +8977,7 @@ M: Eddie James <[email protected]> L: linux-i2c at vger.kernel.org L: openbmc at lists.ozlabs.org (moderated for non-subscribers) S: Maintained -F: Documentation/devicetree/bindings/i2c/i2c-fsi.txt +F: Documentation/devicetree/bindings/i2c/ibm,i2c-fsi.yaml F: drivers/i2c/busses/i2c-fsi.c FSI-ATTACHED SPI DRIVER
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 12/20 dt-bindings: arm: aspeed: add IBM P11 BMC boards
In reply to Eddie JamesDocument two new AST2600 BMC boards for IBM P11 systems.
--- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +2 -0
@@ -86,7 +86,9 @@ properties: - facebook,harma-bmc - facebook,minerva-cmc - facebook,yosemite4-bmc + - ibm,blueridge-bmc - ibm,everest-bmc + - ibm,fuji-bmc - ibm,rainier-bmc - ibm,system1-bmc - ibm,tacoma-bmc
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 13/20 ARM: dts: aspeed: Add IBM P11 FSI devices
In reply to Eddie JamesAdd the P11 FSI device tree for use in upcoming BMC systems. Unlike P10, there is no system with only two processors, so only the quad processor FSI layout is necessary.
---
Changes since v5:
- Add bus-frequency
.../arm/boot/dts/aspeed/ibm-power11-quad.dtsi | 1539 +++++++++++++++++ 1 file changed, 1539 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/ibm-power11-quad.dtsi
arch/arm/boot/dts/aspeed/ibm-power11-quad.dtsi new file +1539 -0
@@ -0,0 +1,1539 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2024 IBM Corp. + +/ { + aliases { + i2c100 = &cfam0_i2c0; + i2c101 = &cfam0_i2c1; + i2c110 = &cfam0_i2c10; + i2c111 = &cfam0_i2c11; + i2c112 = &cfam0_i2c12; + i2c113 = &cfam0_i2c13; + i2c114 = &cfam0_i2c14; + i2c115 = &cfam0_i2c15; + i2c202 = &cfam1_i2c2; + i2c203 = &cfam1_i2c3; + i2c210 = &cfam1_i2c10; + i2c211 = &cfam1_i2c11; + i2c214 = &cfam1_i2c14; + i2c215 = &cfam1_i2c15; + i2c216 = &cfam1_i2c16; + i2c217 = &cfam1_i2c17; + i2c300 = &cfam2_i2c0; + i2c301 = &cfam2_i2c1; + i2c310 = &cfam2_i2c10; + i2c311 = &cfam2_i2c11; + i2c312 = &cfam2_i2c12; + i2c313 = &cfam2_i2c13; + i2c314 = &cfam2_i2c14; + i2c315 = &cfam2_i2c15; + i2c402 = &cfam3_i2c2; + i2c403 = &cfam3_i2c3; + i2c410 = &cfam3_i2c10; + i2c411 = &cfam3_i2c11; + i2c414 = &cfam3_i2c14; + i2c415 = &cfam3_i2c15; + i2c416 = &cfam3_i2c16; + i2c417 = &cfam3_i2c17; + + sbefifo100 = &sbefifo100; + sbefifo101 = &sbefifo101; + sbefifo110 = &sbefifo110; + sbefifo111 = &sbefifo111; + sbefifo112 = &sbefifo112; + sbefifo113 = &sbefifo113; + sbefifo114 = &sbefifo114; + sbefifo115 = &sbefifo115; + sbefifo202 = &sbefifo202; + sbefifo203 = &sbefifo203; + sbefifo210 = &sbefifo210; + sbefifo211 = &sbefifo211; + sbefifo214 = &sbefifo214; + sbefifo215 = &sbefifo215; + sbefifo216 = &sbefifo216; + sbefifo217 = &sbefifo217; + sbefifo300 = &sbefifo300; + sbefifo301 = &sbefifo301; + sbefifo310 = &sbefifo310; + sbefifo311 = &sbefifo311; + sbefifo312 = &sbefifo312; + sbefifo313 = &sbefifo313; + sbefifo314 = &sbefifo314; + sbefifo315 = &sbefifo315; + sbefifo402 = &sbefifo402; + sbefifo403 = &sbefifo403; + sbefifo410 = &sbefifo410; + sbefifo411 = &sbefifo411; + sbefifo414 = &sbefifo414; + sbefifo415 = &sbefifo415; + sbefifo416 = &sbefifo416; + sbefifo417 = &sbefifo417; + + scom100 = &scom100; + scom101 = &scom101; + scom110 = &scom110; + scom111 = &scom111; + scom112 = &scom112; + scom113 = &scom113; + scom114 = &scom114; + scom115 = &scom115; + scom202 = &scom202; + scom203 = &scom203; + scom210 = &scom210; + scom211 = &scom211; + scom214 = &scom214; + scom215 = &scom215; + scom216 = &scom216; + scom217 = &scom217; + scom300 = &scom300; + scom301 = &scom301; + scom310 = &scom310; + scom311 = &scom311; + scom312 = &scom312; + scom313 = &scom313; + scom314 = &scom314; + scom315 = &scom315; + scom402 = &scom402; + scom403 = &scom403; + scom410 = &scom410; + scom411 = &scom411; + scom414 = &scom414; + scom415 = &scom415; + scom416 = &scom416; + scom417 = &scom417; + + spi10 = &cfam0_spi0; + spi11 = &cfam0_spi1; + spi12 = &cfam0_spi2; + spi13 = &cfam0_spi3; + spi20 = &cfam1_spi0; + spi21 = &cfam1_spi1; + spi22 = &cfam1_spi2; + spi23 = &cfam1_spi3; + spi30 = &cfam2_spi0; + spi31 = &cfam2_spi1; + spi32 = &cfam2_spi2; + spi33 = &cfam2_spi3; + spi40 = &cfam3_spi0; + spi41 = &cfam3_spi1; + spi42 = &cfam3_spi2; + spi43 = &cfam3_spi3; + }; +}; + +&fsim0 { + #address-cells = <2>; + #size-cells = <0>; + status = "okay"; + bus-frequency = <100000000>; + cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom at 1000 { + compatible = "ibm,p9-scom"; + reg = <0x1000 0x400>; + }; + + i2c at 1800 { + compatible = "ibm,i2c-fsi"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_i2c0: i2c-bus at 0 { + reg = <0>; /* OMI01 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom100: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo100: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c1: i2c-bus at 1 { + reg = <1>; /* OMI23 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom101: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo101: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c10: i2c-bus at a { + reg = <10>; /* OP3A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom110: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo110: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c11: i2c-bus at b { + reg = <11>; /* OP3B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom111: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo111: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c12: i2c-bus at c { + reg = <12>; /* OP4A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom112: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo112: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c13: i2c-bus at d { + reg = <13>; /* OP4B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom113: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo113: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c14: i2c-bus at e { + reg = <14>; /* OP5A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom114: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo114: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c15: i2c-bus at f { + reg = <15>; /* OP5B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom115: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo115: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + }; + + fsi2spi at 1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_spi0: spi at 0 { + compatible = "ibm,spi-fsi"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam0_spi1: spi at 20 { + compatible = "ibm,spi-fsi"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam0_spi2: spi at 40 { + compatible = "ibm,spi-fsi"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam0_spi3: spi at 60 { + compatible = "ibm,spi-fsi"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + }; + + sbefifo at 2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + + occ { + compatible = "ibm,p10-occ"; + + hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub0: fsi at 3400 { + compatible = "ibm,p9-fsi-controller"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; +}; + +&fsi_hub0 { + cfam at 1,0 { + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom at 1000 { + compatible = "ibm,p9-scom"; + reg = <0x1000 0x400>; + }; + + i2c at 1800 { + compatible = "ibm,i2c-fsi"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_i2c2: i2c-bus at 2 { + reg = <2>; /* OMI45 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom202: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo202: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c3: i2c-bus at 3 { + reg = <3>; /* OMI67 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom203: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo203: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c10: i2c-bus at a { + reg = <10>; /* OP3A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom210: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo210: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c11: i2c-bus at b { + reg = <11>; /* OP3B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom211: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo211: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c14: i2c-bus at e { + reg = <14>; /* OP5A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom214: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo214: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c15: i2c-bus at f { + reg = <15>; /* OP5B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom215: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo215: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c16: i2c-bus at 10 { + reg = <16>; /* OP6A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom216: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo216: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c17: i2c-bus at 11 { + reg = <17>; /* OP6B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom217: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo217: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + }; + + fsi2spi at 1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_spi0: spi at 0 { + compatible = "ibm,spi-fsi"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam1_spi1: spi at 20 { + compatible = "ibm,spi-fsi"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam1_spi2: spi at 40 { + compatible = "ibm,spi-fsi"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam1_spi3: spi at 60 { + compatible = "ibm,spi-fsi"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + }; + + sbefifo at 2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + + occ { + compatible = "ibm,p10-occ"; + + hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi at 3400 { + compatible = "ibm,p9-fsi-controller"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + no-scan-on-init; + }; + }; + + cfam at 2,0 { + reg = <2 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <2>; + + scom at 1000 { + compatible = "ibm,p9-scom"; + reg = <0x1000 0x400>; + }; + + i2c at 1800 { + compatible = "ibm,i2c-fsi"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam2_i2c0: i2c-bus at 0 { + reg = <0>; /* OM01 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom300: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo300: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam2_i2c1: i2c-bus at 1 { + reg = <1>; /* OM23 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom301: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo301: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam2_i2c10: i2c-bus at a { + reg = <10>; /* OP3A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom310: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo310: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam2_i2c11: i2c-bus at b { + reg = <11>; /* OP3B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom311: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo311: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam2_i2c12: i2c-bus at c { + reg = <12>; /* OP4A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom312: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo312: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam2_i2c13: i2c-bus at d { + reg = <13>; /* OP4B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom313: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo313: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam2_i2c14: i2c-bus at e { + reg = <14>; /* OP5A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom314: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo314: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam2_i2c15: i2c-bus at f { + reg = <15>; /* OP5B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom315: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo315: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + }; + + fsi2spi at 1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam2_spi0: spi at 0 { + compatible = "ibm,spi-fsi"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam2_spi1: spi at 20 { + compatible = "ibm,spi-fsi"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam2_spi2: spi at 40 { + compatible = "ibm,spi-fsi"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam2_spi3: spi at 60 { + compatible = "ibm,spi-fsi"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + }; + + sbefifo at 2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + + occ { + compatible = "ibm,p10-occ"; + + hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi at 3400 { + compatible = "ibm,p9-fsi-controller"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + no-scan-on-init; + }; + }; + + cfam at 3,0 { + reg = <3 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <3>; + + scom at 1000 { + compatible = "ibm,p9-scom"; + reg = <0x1000 0x400>; + }; + + i2c at 1800 { + compatible = "ibm,i2c-fsi"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam3_i2c2: i2c-bus at 2 { + reg = <2>; /* OM45 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom402: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo402: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam3_i2c3: i2c-bus at 3 { + reg = <3>; /* OM67 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom403: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo403: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam3_i2c10: i2c-bus at a { + reg = <10>; /* OP3A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom410: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo410: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam3_i2c11: i2c-bus at b { + reg = <11>; /* OP3B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom411: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo411: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam3_i2c14: i2c-bus at e { + reg = <14>; /* OP5A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom414: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo414: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam3_i2c15: i2c-bus at f { + reg = <15>; /* OP5B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom415: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo415: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam3_i2c16: i2c-bus at 10 { + reg = <16>; /* OP6A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom416: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo416: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam3_i2c17: i2c-bus at 11 { + reg = <17>; /* OP6B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi at 20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam at 0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom417: scom at 1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo417: sbefifo at 2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + }; + + fsi2spi at 1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam3_spi0: spi at 0 { + compatible = "ibm,spi-fsi"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam3_spi1: spi at 20 { + compatible = "ibm,spi-fsi"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam3_spi2: spi at 40 { + compatible = "ibm,spi-fsi"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam3_spi3: spi at 60 { + compatible = "ibm,spi-fsi"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + }; + + sbefifo at 2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + + occ { + compatible = "ibm,p10-occ"; + + hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi at 3400 { + compatible = "ibm,p9-fsi-controller"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + no-scan-on-init; + }; + }; +};
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 14/20 ARM: dts: aspeed: Add IBM P11 Blueridge BMC system
In reply to Eddie JamesAdd the device tree for the new BMC system. The Blueridge is a P11 system with four processors.
---
Changes since v5:
- Change model from "Blueridge" to "Blueridge 2U"
arch/arm/boot/dts/aspeed/Makefile | 1 + .../dts/aspeed/aspeed-bmc-ibm-blueridge.dts | 1691 +++++++++++++++++ 2 files changed, 1692 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts
arch/arm/boot/dts/aspeed/Makefile +1 -0
@@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-yamp.dtb \ aspeed-bmc-facebook-yosemitev2.dtb \ aspeed-bmc-facebook-yosemite4.dtb \ + aspeed-bmc-ibm-blueridge.dtb \ aspeed-bmc-ibm-bonnell.dtb \ aspeed-bmc-ibm-everest.dtb \ aspeed-bmc-ibm-rainier.dtb \
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts new file +1691 -0
1,691 lines not on this page · raw message
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 15/20 ARM: dts: aspeed: Add IBM P11 Blueridge 4U BMC system
In reply to Eddie JamesThe 4U Blueridge is identical to the Blueridge system but has two extra power supplies.
--- .../aspeed/aspeed-bmc-ibm-blueridge-4u.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge-4u.dts
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge-4u.dts new file +21 -0
@@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2024 IBM Corp. +/dts-v1/; + +#include "aspeed-bmc-ibm-blueridge.dts" + +/ { + model = "Blueridge 4U"; +}; + +&i2c3 { + power-supply at 6a { + compatible = "ibm,cffps"; + reg = <0x6a>; + }; + + power-supply at 6b { + compatible = "ibm,cffps"; + reg = <0x6b>; + }; +};
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 17/20 ARM: dts: aspeed: Add IBM Huygens BMC system
In reply to Eddie JamesThe Huygens is a Rainier with modifed FSI wiring.
--- arch/arm/boot/dts/aspeed/Makefile | 1 + .../dts/aspeed/aspeed-bmc-ibm-huygens.dts | 23 +++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-huygens.dts
arch/arm/boot/dts/aspeed/Makefile +1 -0
@@ -36,6 +36,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-ibm-bonnell.dtb \ aspeed-bmc-ibm-everest.dtb \ aspeed-bmc-ibm-fuji.dtb \ + aspeed-bmc-ibm-huygens.dtb \ aspeed-bmc-ibm-rainier.dtb \ aspeed-bmc-ibm-rainier-1s4u.dtb \ aspeed-bmc-ibm-rainier-4u.dtb \
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-huygens.dts new file +23 -0
@@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2024 IBM Corp. +/dts-v1/; + +#include "aspeed-bmc-ibm-rainier.dts" + +/ { + model = "Huygens"; +}; + +&fsim0 { + /delete-node/ cfam at 0,0; + /delete-property/ cfam-reset-gpios; + + bus-frequency = <100000000>; +}; + +&fsim1 { + #address-cells = <2>; + #size-cells = <0>; + status = "okay"; + bus-frequency = <100000000>; +};
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 18/20 fsi: occ: Get device number from FSI minor number API
In reply to Eddie JamesRemove the IDA indexing for OCC devices and instead use the FSI minor number API. This will make the OCC numbering consistent with other FSI engines and make the "reg" device tree property unnecessary.
--- drivers/fsi/fsi-occ.c | 47 +++++++++---------------------------------- 1 file changed, 9 insertions(+), 38 deletions(-)
drivers/fsi/fsi-occ.c +9 -38
@@ -4,9 +4,9 @@#include <linux/err.h> #include <linux/errno.h> #include <linux/fs.h> +#include <linux/fsi.h> #include <linux/fsi-sbefifo.h> #include <linux/gfp.h> -#include <linux/idr.h> #include <linux/kernel.h> #include <linux/list.h> #include <linux/miscdevice.h>
@@ -44,6 +44,7 @@ struct occ {struct device *sbefifo;char name[32 ];int idx; +dev_t devt;bool platform_hwmon;u8 sequence_number;void *buffer;
@@ -75,8 +76,6 @@ struct occ_client {#define to_client (x) container_of((x), struct occ_client, xfr) -static DEFINE_IDA (occ_ida); -static int occ_open (struct inode *inode,struct file *file) {struct occ_client *client =kzalloc (sizeof (*client),GFP_KERNEL );
@@ -622,7 +621,6 @@ static int occ_unregister_of_child(struct device *dev, void *data)static int occ_probe (struct platform_device *pdev) {int rc; -u32 reg;char child_name[32 ];struct occ *occ;struct platform_device *hwmon_dev =NULL ;
@@ -637,6 +635,10 @@ static int occ_probe(struct platform_device *pdev)if (!occ)return -ENOMEM ; + rc =fsi_get_new_minor (to_fsi_dev (dev->parent), fsi_dev_occ, &occ->devt, &occ->idx); +if (rc) +return rc; +/* SBE words are always four bytes */ occ->buffer =kvmalloc (OCC_MAX_RESP_WORDS *4 ,GFP_KERNEL );if (!occ->buffer)
@@ -651,24 +653,6 @@ static int occ_probe(struct platform_device *pdev)*/ occ->sequence_number = (u8)((jiffies %0xff ) +1 );mutex_init (&occ->occ_lock); - -if (dev->of_node) { - rc =of_property_read_u32 (dev->of_node,"reg" , ®); -if (!rc) { -/* make sure we don't have a duplicate from dts */ - occ->idx =ida_simple_get (&occ_ida, reg, reg +1 , -GFP_KERNEL ); -if (occ->idx <0 ) - occ->idx =ida_simple_get (&occ_ida,1 ,INT_MAX , -GFP_KERNEL ); - }else { - occ->idx =ida_simple_get (&occ_ida,1 ,INT_MAX , -GFP_KERNEL ); - } - }else { - occ->idx =ida_simple_get (&occ_ida,1 ,INT_MAX ,GFP_KERNEL ); - } -platform_set_drvdata (pdev, occ);snprintf (occ->name,sizeof (occ->name),"occ%d" , occ->idx);
@@ -680,7 +664,7 @@ static int occ_probe(struct platform_device *pdev) rc =misc_register (&occ->mdev);if (rc) {dev_err (dev,"failed to register miscdevice: %d\n" , rc); -ida_simple_remove (&occ_ida, occ->idx); +fsi_free_minor (occ->devt);kvfree (occ->buffer);return rc; }
@@ -719,7 +703,7 @@ static int occ_remove(struct platform_device *pdev)else device_for_each_child (&pdev->dev,NULL , occ_unregister_of_child); -ida_simple_remove (&occ_ida, occ->idx); +fsi_free_minor (occ->devt);return 0 ; }
@@ -746,20 +730,7 @@ static struct platform_driver occ_driver = { .remove = occ_remove, }; -static int occ_init (void ) -{ -return platform_driver_register (&occ_driver); -} - -static void occ_exit (void ) -{ -platform_driver_unregister (&occ_driver); - -ida_destroy (&occ_ida); -} - -module_init (occ_init); -module_exit (occ_exit); +module_platform_driver (occ_driver);MODULE_AUTHOR ("Eddie James <[email protected]>" );MODULE_DESCRIPTION ("BMC P9 OCC driver" );
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 19/20 fsi: occ: Find next available child rather than node name match
In reply to Eddie JamesThere's no reason to restrict the creation of the hwmon device to a matching child node name. Just get the first available one. There should only be one child node anyway.
--- drivers/fsi/fsi-occ.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/fsi/fsi-occ.c +1 -1
@@ -669,7 +669,7 @@ static int occ_probe(struct platform_device *pdev)return rc; } - hwmon_node =of_get_child_by_name (dev->of_node, hwmon_dev_info.name); + hwmon_node =of_get_next_available_child (dev->of_node,NULL );if (hwmon_node) {snprintf (child_name,sizeof (child_name),"%s.%d" , hwmon_dev_info.name, occ->idx); hwmon_dev =of_platform_device_create (hwmon_node, child_name, dev);
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 20/20 fsi: scom: Update compatible string to match documentation
In reply to Eddie JamesUse p9-scom instead of fsi2pib.
--- drivers/fsi/fsi-scom.c | 1 + 1 file changed, 1 insertion(+)
drivers/fsi/fsi-scom.c +1 -0
@@ -590,6 +590,7 @@ static int scom_remove(struct device *dev)static const struct of_device_id scom_of_ids[] = { { .compatible ="ibm,fsi2pib" }, + { .compatible ="ibm,p9-scom" }, { } };MODULE_DEVICE_TABLE (of, scom_of_ids);
Signature · 1 line
2.39.3
Eddie James
maintainerPATCH v6 16/20 ARM: dts: aspeed: Add IBM P11 Fuji BMC system
In reply to Eddie JamesAdd the device tree for the new BMC system. The Fuji is a P11 system with eight processors.
---
Changes since v5:
- Add missing reset gpio for led controller on i2c bus 8
arch/arm/boot/dts/aspeed/Makefile | 1 + .../boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts | 3881 +++++++++++++++++ 2 files changed, 3882 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts
arch/arm/boot/dts/aspeed/Makefile +1 -0
@@ -35,6 +35,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-ibm-blueridge.dtb \ aspeed-bmc-ibm-bonnell.dtb \ aspeed-bmc-ibm-everest.dtb \ + aspeed-bmc-ibm-fuji.dtb \ aspeed-bmc-ibm-rainier.dtb \ aspeed-bmc-ibm-rainier-1s4u.dtb \ aspeed-bmc-ibm-rainier-4u.dtb \
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts new file +3881 -0
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2.39.3
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Re: [PATCH v6 06/20] dt-bindings: fsi: Document the FSI controller common properties
In reply to Eddie JamesQuoted 8 lines · Eddie James
Since there are multiple FSI controllers documented, the common properties should be documented separately and then referenced from the specific controller documentation. Add bus-frequency for the FSI bus and CFAM local bus frequencies. Add interrupt controller properties.
Signed-off-by Eddie James <[email protected]>---
Best regards,
Krzysztof
Re: [PATCH v6 11/20] dt-bindings: i2c: i2c-fsi: Convert to json-schema
In reply to Eddie JamesQuoted 7 lines · Eddie James
Convert to json-schema for the FSI-attached I2C controller.
Signed-off-by Eddie James <[email protected]>---
Changes since v5:
- Use more specific regex for node names
Best regards,
Krzysztof
Re: [PATCH v6 03/20] dt-bindings: fsi: Document the IBM SCOM engine
In reply to Eddie JamesQuoted 2 lines
The SCOM engine provides an interface to the POWER processor PIB (Pervasive Interconnect Bus).
Please improve this change description with a corresponding imperative wording.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.9#n94
Regards,
Markus
Re: [PATCH v6 03/20] dt-bindings: fsi: Document the IBM SCOM engine
Quoted 5 lines · Markus Elfring
Quoted 2 lines
The SCOM engine provides an interface to the POWER processor PIB (Pervasive Interconnect Bus).
Please improve this change description with a corresponding imperative wording.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.9#n94
The tense used here is fine.
Re: [v6 03/20] dt-bindings: fsi: Document the IBM SCOM engine
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
The SCOM engine provides an interface to the POWER processor PIB (Pervasive Interconnect Bus).
Please improve this change description with a corresponding imperative wording.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.9#n94The tense used here is fine.
Is the imperative mood preferred for the final commit message (besides the summary phrase)?
Regards,
Markus
kernel test robot
build botRe: [PATCH v6 17/20] ARM: dts: aspeed: Add IBM Huygens BMC system
In reply to Eddie Jameskernel test robot noticed the following build errors:
Hi Eddie,
kernel test robot noticed the following build errors:
[auto build test ERROR on andi-shyti/i2c/i2c-host]
[also build test ERROR on linus/master v6.9 next-20240523] [cannot apply to robh/for-next broonie-spi/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Eddie-James/spi-dt-bindings-Document-the-IBM-FSI-attached-SPI-controller/20240523-033334 base: git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux.git i2c/i2c-host patch link: https://lore.kernel.org/r/20240522192524.3286237-18-eajames%40linux.ibm.com patch subject: [PATCH v6 17/20] ARM: dts: aspeed: Add IBM Huygens BMC system config: arm-randconfig-001-20240523 (https://download.01.org/0day-ci/archive/20240523/202405232008.olE9azVd-lkp at intel.com/config) compiler: arm-linux-gnueabi-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240523/202405232008.olE9azVd-lkp at intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/202405232008.olE9azVd-lkp at intel.com/
All errors (new ones prefixed by >>):
>> Error: arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-huygens.dts:13.2-37 Properties must precede subnodes
FATAL ERROR: Unable to parse input tree
Signature · 2 lines
0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki
Re: [PATCH v6 04/20] dt-bindings: fsi: p9-occ: Convert to json-schema
In reply to Eddie JamesQuoted 1 line
Conver to json-schema for the OCC documentation. ?
Convert?
Regards,
Markus
Re: [PATCH v6 05/20] dt-bindings: fsi: Document the IBM SBEFIFO engine
In reply to Eddie JamesQuoted 2 lines
The SBEFIFO engine provides an interface to the POWER processor Self Boot Engine (SBE).
Under which circumstances will imperative wordings be applied for another improved change description?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.9#n94
Regards,
Markus
Re: [PATCH v6 17/20] ARM: dts: aspeed: Add IBM Huygens BMC system
In reply to Eddie JamesQuoted 1 line
The Huygens is a Rainier with modifed FSI wiring.
Will imperative wordings become helpful for a better commit message here?
Regards,
Markus
Eddie James
maintainerRe: [PATCH v6 17/20] ARM: dts: aspeed: Add IBM Huygens BMC system
Quoted 2 lines · Markus Elfring
Quoted 1 line
The Huygens is a Rainier with modifed FSI wiring.
Will imperative wordings become helpful for a better commit message here?
This statement is a description of hardware. I cannot word that imperatively. The commit message is imperative - "Add Huygens system".
Quoted 3 lines
Regards,
Markus
Eddie James
maintainerRe: [PATCH v6 17/20] ARM: dts: aspeed: Add IBM Huygens BMC system
In reply to kernel test robotQuoted 3 lines · kernel test robot
Hi Eddie,
kernel test robot noticed the following build errors:
Silly mistake. If this patch can be dropped from the series, I can send an updated Huygens DTS after this series is merged, unless I need to do a v7.
Thanks,
Eddie
Quoted 26 lines
[auto build test ERROR on andi-shyti/i2c/i2c-host]
[also build test ERROR on linus/master v6.9 next-20240523] [cannot apply to robh/for-next broonie-spi/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]url: https://github.com/intel-lab-lkp/linux/commits/Eddie-James/spi-dt-bindings-Document-the-IBM-FSI-attached-SPI-controller/20240523-033334 base: git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux.git i2c/i2c-host patch link: https://lore.kernel.org/r/20240522192524.3286237-18-eajames%40linux.ibm.com patch subject: [PATCH v6 17/20] ARM: dts: aspeed: Add IBM Huygens BMC system config: arm-randconfig-001-20240523 (https://download.01.org/0day-ci/archive/20240523/202405232008.olE9azVd-lkp at intel.com/config) compiler: arm-linux-gnueabi-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240523/202405232008.olE9azVd-lkp at intel.com/reproduce)If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/202405232008.olE9azVd-lkp at intel.com/All errors (new ones prefixed by >>):
Quoted 1 line
Quoted 1 line
Error: arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-huygens.dts:13.2-37 Properties must precede subnodes
FATAL ERROR: Unable to parse input tree
Re: [v6 17/20] ARM: dts: aspeed: Add IBM Huygens BMC system
In reply to Eddie JamesQuoted 5 lines
Quoted 2 lines
Quoted 1 line
The Huygens is a Rainier with modifed FSI wiring.
Will imperative wordings become helpful for a better commit message here?
This statement is a description of hardware. I cannot word that imperatively.
Please take another look at corresponding improvement possibilities.
Quoted 1 line
The commit message is imperative - "Add Huygens system".
This information fits to the summary phrase.
Would you like to mention in the changelog that a hardware description should be extended anyhow?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.9#n94
Regards,
Markus
Re: [v6 17/20] ARM: dts: aspeed: Add IBM Huygens BMC system
Markus,
Quoted 9 lines · Markus Elfring
Quoted 5 lines
Quoted 2 lines
Quoted 1 line
The Huygens is a Rainier with modifed FSI wiring.
Will imperative wordings become helpful for a better commit message here?
This statement is a description of hardware. I cannot word that imperatively.
Please take another look at corresponding improvement possibilities.
Quoted 7 lines
Quoted 1 line
The commit message is imperative - "Add Huygens system".
This information fits to the summary phrase.
Would you like to mention in the changelog that a hardware description should be extended anyhow?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.9#n94
You are talking absolute crap here. Stop harassing contributors with your inane comments.
Thanks,
Conor.
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Re: [v6 17/20] ARM: dts: aspeed: Add IBM Huygens BMC system
Quoted 6 lines
Quoted 3 lines
Would you like to mention in the changelog that a hardware description should be extended anyhow?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.9#n94You are talking absolute crap here. Stop harassing contributors with your inane comments.
Why do you interpret my patch review contributions in this direction when the official Linux development documentation provides special advice on affected wording details?
Regards,
Markus
Re: [PATCH v6 17/20] ARM: dts: aspeed: Add IBM Huygens BMC system
In reply to Eddie JamesQuoted 8 lines · Eddie James
Quoted 2 lines · Markus Elfring
Quoted 1 line
The Huygens is a Rainier with modifed FSI wiring.
Will imperative wordings become helpful for a better commit message here?
This statement is a description of hardware. I cannot word that imperatively. The commit message is imperative - "Add Huygens system".
Feel free to ignore all comments coming from Markus (or implement, entirely up to you).
Markus is banned from mailing lists and most of maintainers already ignore him or already marked as spam.
Best regards,
Krzysztof
Re: [v6 17/20] ARM: dts: aspeed: Add IBM Huygens BMC system
Quoted 2 lines
Markus is banned from mailing lists and most of maintainers already ignore him or already marked as spam.
The running patch review can eventually become more constructive despite of recurring communication difficulties.
Regards,
Markus
Re: [v6 17/20] ARM: dts: aspeed: Add IBM Huygens BMC system
In reply to Markus ElfringQuoted 10 lines · Markus Elfring
Quoted 6 lines
Quoted 3 lines
Would you like to mention in the changelog that a hardware description should be extended anyhow?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.9#n94You are talking absolute crap here. Stop harassing contributors with your inane comments.
Why do you interpret my patch review contributions in this direction when the official Linux development documentation provides special advice on affected wording details?
Your "contributions" are garbage in general, and this thread is not an exception. More specifically, you are picking an advice that is inapplicable, transforming it into a question and "contributing" the result.
And your entire modus operandi fits that pattern - you spew random garbage and expect the contributors to spend their time and efforts on checking if your (contents-free) "advice" happens to make any sense.
That. Is. Worthless.
According to people who'd met you in person you *are* a member of our species, and I can't exclude the possibility that in some other environments you might be capable of sentience. Unfortunately, the kernel development is clearly not among those.
Re: [PATCH v6 20/20] fsi: scom: Update compatible string to match documentation
In reply to Eddie JamesRe: [PATCH v6 19/20] fsi: occ: Find next available child rather than node name match
In reply to Eddie JamesRe: [PATCH v6 18/20] fsi: occ: Get device number from FSI minor number API
In reply to Eddie JamesRe: [PATCH v6 17/20] ARM: dts: aspeed: Add IBM Huygens BMC system
In reply to Eddie JamesRe: [v6 17/20] ARM: dts: aspeed: Add IBM Huygens BMC system
In reply to Al ViroQuoted 5 lines
Quoted 3 lines
Why do you interpret my patch review contributions in this direction when the official Linux development documentation provides special advice on affected wording details?
Your "contributions" are garbage in general,
My contributions are also varying (as usual) through the years.
Quoted 1 line
and this thread is not an exception.
It is just another example for involved communication challenges.
Quoted 1 line
More specifically, you are picking an advice
Some development activities are reminders according to known information sources.
Quoted 6 lines
that is inapplicable,
transforming it into a question and "contributing" the result.And your entire modus operandi fits that pattern - you spew random garbage and expect the contributors to spend their time and efforts on checking if your (contents-free) "advice" happens to make any sense.
Do you express special concerns here which can be reconsidered because of advices and requirements from software development guidelines?
?
Quoted 2 lines
Unfortunately, the kernel development is clearly
not among those.
How does such a view fit to an other data representation?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/log/?qt=author&q=Elfring
Regards,
Markus
Re: [PATCH v6 15/20] ARM: dts: aspeed: Add IBM P11 Blueridge 4U BMC system
In reply to Eddie JamesQuoted 8 lines · Eddie James
The 4U Blueridge is identical to the Blueridge system but has two extra power supplies.
Signed-off-by Eddie James <[email protected]>--- .../aspeed/aspeed-bmc-ibm-blueridge-4u.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+)create mode 100644
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge-4u.dts
Ninad Palsule
reviewerPATCH v6 14/20 ARM: dts: aspeed: Add IBM P11 Blueridge BMC system
In reply to Eddie Jamesarch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts line 644
Quoted 8 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts new file +8
-0+ led at 6 { + reg = <6>; + default-state = "keep"; + label = "cpu-vrm1"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; +
Is there a specific reason for skipping led at 7? Its not connected?
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts line 653
Quoted 9 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts new file +9
-0+ led at 8 { + reg = <8>; + default-state = "keep"; + label = "lcd-russel"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + }; +
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Ninad Palsule
reviewerPATCH v6 16/20 ARM: dts: aspeed: Add IBM P11 Fuji BMC system
In reply to Eddie JamesHi Eddie,
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts line 1583
Quoted 8 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts new file +8
-0+ + led at 6 { + reg = <6>; + default-state = "keep"; + label = "opencapi-connector5"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + };
is led at 7 not connected?
Quoted 30 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts new file +30
-0+ + led at 8 { + reg = <8>; + default-state = "keep"; + label = "vrm4"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + + led at 9 { + reg = <9>; + default-state = "keep"; + label = "vrm5"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + + led at 10 { + reg = <10>; + default-state = "keep"; + label = "vrm6"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + + led at 11 { + reg = <11>; + default-state = "keep"; + label = "vrm7"; + retain-state-shutdown;
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts line 1623
Quoted 10 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts new file +10
-0+ type = <PCA955X_TYPE_LED>; + }; + + led at 12 { + reg = <12>; + default-state = "keep"; + label = "vrm12"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + };
curious about label jump from vrm7 to vrm12.
Quoted 8 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts new file +5
-0+ cfam4_i2c10: i2c-bus at a { + reg = <10>; /* OP3A */ + #address-cells = <1>; + #size-cells = <0>; +It will be more readable to have "reg" value in hex too. I have seen similar stuff in this FSI nodes. It will be consistent with other places. +
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Ninad Palsule
reviewerPATCH v6 13/20 ARM: dts: aspeed: Add IBM P11 FSI devices
In reply to Eddie JamesHi Eddie,
arch/arm/boot/dts/aspeed/ibm-power11-quad.dtsi line 241
Quoted 4 lines
arch/arm/boot/dts/aspeed/ibm-power11-quad.dtsi new file +4
-0+ cfam0_i2c11: i2c-bus at b { + reg = <11>; /* OP3B */ + #address-cells = <1>; + #size-cells = <0>;
It will be nice to have reg value also in hex for easy ready.
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Re: [PATCH v6 12/20] dt-bindings: arm: aspeed: add IBM P11 BMC boards
In reply to Eddie JamesHi Eddie
Quoted 13 lines · Eddie James
Document two new AST2600 BMC boards for IBM P11 systems.
Signed-off-by Eddie James <[email protected]>--- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 2 ++ 1 file changed, 2 insertions(+)Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +0
-0
Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml properties: · line 94
Quoted 9 lines
Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +2
-0@@ -86,7 +86,9 @@ properties: - facebook,harma-bmc - facebook,minerva-cmc - facebook,yosemite4-bmc + - ibm,blueridge-bmc - ibm,everest-bmc + - ibm,fuji-bmc - ibm,rainier-bmc - ibm,system1-bmc - ibm,tacoma-bmc
Eddie James
maintainerRe: [PATCH v6 16/20] ARM: dts: aspeed: Add IBM P11 Fuji BMC system
In reply to Ninad PalsuleQuoted 12 lines · Ninad Palsule
Hi Eddie,
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts line 1583
Quoted 8 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts new file +8
-0+ + led at 6 { + reg = <6>; + default-state = "keep"; + label = "opencapi-connector5"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + };is led at 7 not connected?
Correct.
Quoted 33 lines
Quoted 33 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts new file +33
-0+ + led at 8 { + reg = <8>; + default-state = "keep"; + label = "vrm4"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + + led at 9 { + reg = <9>; + default-state = "keep"; + label = "vrm5"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + + led at 10 { + reg = <10>; + default-state = "keep"; + label = "vrm6"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + + led at 11 { + reg = <11>; + default-state = "keep"; + label = "vrm7"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; +
Quoted 8 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts line 1623
Quoted 7 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts new file +7
-0+ led at 12 { + reg = <12>; + default-state = "keep"; + label = "vrm12"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + };curious about label jump from vrm7 to vrm12.
vrm0-3 and 8-11 are on the previous pca chip. I believe this is correct based on the wiring in the spec, though the numberings are really just convention established by the guy who managed the LEDs on the system.
Quoted 10 lines
Quoted 7 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts new file +5
-0+ cfam4_i2c10: i2c-bus at a { + reg = <10>; /* OP3A */ + #address-cells = <1>; + #size-cells = <0>; +It will be more readable to have "reg" value in hex too. I have seen similar stuff in this FSI nodes. It will be consistent with other places. +
Reviewed-by Ninad Palsule <[email protected]>
Sure, thanks!
Eddie
Eddie James
maintainerRe: [PATCH v6 14/20] ARM: dts: aspeed: Add IBM P11 Blueridge BMC system
In reply to Ninad PalsuleQuoted 9 lines · Ninad Palsule
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts line 644
Quoted 8 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts new file +8
-0+ led at 6 { + reg = <6>; + default-state = "keep"; + label = "cpu-vrm1"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; +Is there a specific reason for skipping led at 7? Its not connected?
Yes, again not connected.
Quoted 12 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts line 653
Quoted 9 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts new file +9
-0+ led at 8 { + reg = <8>; + default-state = "keep"; + label = "lcd-russel"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + }; +Reviewed-by Ninad Palsule <[email protected]>
Thanks,
Eddie
Re: [PATCH v6 11/20] dt-bindings: i2c: i2c-fsi: Convert to json-schema
In reply to Eddie JamesHi Eddie,
Quoted 7 lines · Eddie James
Convert to json-schema for the FSI-attached I2C controller.
Signed-off-by Eddie James <[email protected]>---
Changes since v5:
- Use more specific regex for node names
Quoted 6 lines
.../devicetree/bindings/i2c/i2c-fsi.txt | 40 ---------- .../devicetree/bindings/i2c/ibm,i2c-fsi.yaml | 76 +++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 77 insertions(+), 41 deletions(-)delete mode 100644
Documentation/devicetree/bindings/i2c/i2c-fsi.txtcreate mode 100644Documentation/devicetree/bindings/i2c/ibm,i2c-fsi.yaml
Thanks & Regards,
Ninad
Ninad Palsule
reviewerPATCH v6 10/20 dt-bindings: fsi: Document the FSI Hub Controller
In reply to Eddie JamesHi Eddie,
Thanks & Regards,
Ninad
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Eddie James
maintainerQuoted 3 lines · Eddie James
Add the Blueridge and Fuji BMC systems. Document many missing FSI related properties, and fix existing warnings. Make some minor fixes in OCC and SCOM drivers for the updated bindings.
Hi Joel/Andrew, what else needs to be fixed before this can be merged (minus Huygens patch which I will resend)? I believe all the patches have been reviewed.
Thanks,
Eddie
Quoted 74 lines
Changes since v5:
- Switch from clock-frequency to bus-frequency for common FSI controller properties
- Add reg properties for AST2700 FSI controller
- Fix patternProperties for i2c bus nodes under FSI-based I2C controller
- Add bus-frequency for P11 FSI device tree node
- Change model name from Blueridge to Blueridge 2U
- Add missing reset gpio to led controller on Fuji
- Add Huygens (Rainier with modified FSI wiring)Eddie James (20):
spi: dt-bindings: Document the IBM FSI-attached SPI controller
dt-bindings: fsi: fsi2spi: Document SPI controller child nodes
dt-bindings: fsi: Document the IBM SCOM engine
dt-bindings: fsi: p9-occ: Convert to json-schema
dt-bindings: fsi: Document the IBM SBEFIFO engine
dt-bindings: fsi: Document the FSI controller common properties
dt-bindings: fsi: ibm,i2cr-fsi-master: Reference common FSI controller
dt-bindings: fsi: ast2600-fsi-master: Convert to json-schema
dt-bindings: fsi: Document the AST2700 FSI controller
dt-bindings: fsi: Document the FSI Hub Controller
dt-bindings: i2c: i2c-fsi: Convert to json-schema
dt-bindings: arm: aspeed: add IBM P11 BMC boards
ARM: dts: aspeed: Add IBM P11 FSI devices
ARM: dts: aspeed: Add IBM P11 Blueridge BMC system
ARM: dts: aspeed: Add IBM P11 Blueridge 4U BMC system
ARM: dts: aspeed: Add IBM P11 Fuji BMC system
ARM: dts: aspeed: Add IBM Huygens BMC system
fsi: occ: Get device number from FSI minor number API
fsi: occ: Find next available child rather than node name match
fsi: scom: Update compatible string to match documentation.../bindings/arm/aspeed/aspeed.yaml | 2 + .../fsi/aspeed,ast2600-fsi-master.yaml | 121 + .../bindings/fsi/fsi-controller.yaml | 66 + .../bindings/fsi/fsi-master-aspeed.txt | 36 - .../devicetree/bindings/fsi/ibm,fsi2spi.yaml | 36 +- .../bindings/fsi/ibm,i2cr-fsi-master.yaml | 5 +- .../bindings/fsi/ibm,p9-fsi-controller.yaml | 45 + .../devicetree/bindings/fsi/ibm,p9-occ.txt | 16 - .../devicetree/bindings/fsi/ibm,p9-occ.yaml | 40 + .../bindings/fsi/ibm,p9-sbefifo.yaml | 46 + .../devicetree/bindings/fsi/ibm,p9-scom.yaml | 37 + .../devicetree/bindings/i2c/i2c-fsi.txt | 40 - .../devicetree/bindings/i2c/ibm,i2c-fsi.yaml | 76 + .../devicetree/bindings/spi/ibm,spi-fsi.yaml | 55 + MAINTAINERS | 2 +- arch/arm/boot/dts/aspeed/Makefile | 3 + .../aspeed/aspeed-bmc-ibm-blueridge-4u.dts | 21 + .../dts/aspeed/aspeed-bmc-ibm-blueridge.dts | 1691 +++++++ .../boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts | 3881 +++++++++++++++++ .../dts/aspeed/aspeed-bmc-ibm-huygens.dts | 23 + .../arm/boot/dts/aspeed/ibm-power11-quad.dtsi | 1539 +++++++ drivers/fsi/fsi-occ.c | 49 +- drivers/fsi/fsi-scom.c | 1 + 23 files changed, 7694 insertions(+), 137 deletions(-)create mode 100644
Documentation/devicetree/bindings/fsi/aspeed,ast2600-fsi-master.yamlcreate mode 100644Documentation/devicetree/bindings/fsi/fsi-controller.yamldelete mode 100644Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txtcreate mode 100644Documentation/devicetree/bindings/fsi/ibm,p9-fsi-controller.yamldelete mode 100644Documentation/devicetree/bindings/fsi/ibm,p9-occ.txtcreate mode 100644Documentation/devicetree/bindings/fsi/ibm,p9-occ.yamlcreate mode 100644Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.yamlcreate mode 100644Documentation/devicetree/bindings/fsi/ibm,p9-scom.yamldelete mode 100644Documentation/devicetree/bindings/i2c/i2c-fsi.txtcreate mode 100644Documentation/devicetree/bindings/i2c/ibm,i2c-fsi.yamlcreate mode 100644Documentation/devicetree/bindings/spi/ibm,spi-fsi.yamlcreate mode 100644arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge-4u.dtscreate mode 100644arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dtscreate mode 100644arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dtscreate mode 100644arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-huygens.dtscreate mode 100644arch/arm/boot/dts/aspeed/ibm-power11-quad.dtsi
Andrew Jeffery
maintainerHi Eddie,
Quoted 10 lines · Eddie James
Quoted 3 lines · Eddie James
Add the Blueridge and Fuji BMC systems. Document many missing FSI related properties, and fix existing warnings. Make some minor fixes in OCC and SCOM drivers for the updated bindings.
Hi Joel/Andrew, what else needs to be fixed before this can be merged (minus Huygens patch which I will resend)? I believe all the patches have been reviewed.
Firstly, thanks for your work here on the FSI bindings.
However, the series is a bit awkward, as it sandwiches Aspeed devicetree patches that should go through Joel's bmc tree between the bindings and driver fixes that should go through the FSI tree.
This is potentially less of a problem for Joel as he's the maintainer for both, but it's not my place to be touching the FSI tree.
For now I've applied the dts patches and pushed them here after dropping the Huygens patch:
https://github.com/amboar/linux/commits/for/bmc/dt-6.11/
But I would appreciate it if you split series by subsystem in the future (see my comments on the other FSI series you have out for review).
Andrew
Quoted 80 lines
Thanks,
Eddie
Quoted 74 lines
Changes since v5:
- Switch from clock-frequency to bus-frequency for common FSI controller properties
- Add reg properties for AST2700 FSI controller
- Fix patternProperties for i2c bus nodes under FSI-based I2C controller
- Add bus-frequency for P11 FSI device tree node
- Change model name from Blueridge to Blueridge 2U
- Add missing reset gpio to led controller on Fuji
- Add Huygens (Rainier with modified FSI wiring)Eddie James (20):
spi: dt-bindings: Document the IBM FSI-attached SPI controller
dt-bindings: fsi: fsi2spi: Document SPI controller child nodes
dt-bindings: fsi: Document the IBM SCOM engine
dt-bindings: fsi: p9-occ: Convert to json-schema
dt-bindings: fsi: Document the IBM SBEFIFO engine
dt-bindings: fsi: Document the FSI controller common properties
dt-bindings: fsi: ibm,i2cr-fsi-master: Reference common FSI controller
dt-bindings: fsi: ast2600-fsi-master: Convert to json-schema
dt-bindings: fsi: Document the AST2700 FSI controller
dt-bindings: fsi: Document the FSI Hub Controller
dt-bindings: i2c: i2c-fsi: Convert to json-schema
dt-bindings: arm: aspeed: add IBM P11 BMC boards
ARM: dts: aspeed: Add IBM P11 FSI devices
ARM: dts: aspeed: Add IBM P11 Blueridge BMC system
ARM: dts: aspeed: Add IBM P11 Blueridge 4U BMC system
ARM: dts: aspeed: Add IBM P11 Fuji BMC system
ARM: dts: aspeed: Add IBM Huygens BMC system
fsi: occ: Get device number from FSI minor number API
fsi: occ: Find next available child rather than node name match
fsi: scom: Update compatible string to match documentation.../bindings/arm/aspeed/aspeed.yaml | 2 + .../fsi/aspeed,ast2600-fsi-master.yaml | 121 + .../bindings/fsi/fsi-controller.yaml | 66 + .../bindings/fsi/fsi-master-aspeed.txt | 36 - .../devicetree/bindings/fsi/ibm,fsi2spi.yaml | 36 +- .../bindings/fsi/ibm,i2cr-fsi-master.yaml | 5 +- .../bindings/fsi/ibm,p9-fsi-controller.yaml | 45 + .../devicetree/bindings/fsi/ibm,p9-occ.txt | 16 - .../devicetree/bindings/fsi/ibm,p9-occ.yaml | 40 + .../bindings/fsi/ibm,p9-sbefifo.yaml | 46 + .../devicetree/bindings/fsi/ibm,p9-scom.yaml | 37 + .../devicetree/bindings/i2c/i2c-fsi.txt | 40 - .../devicetree/bindings/i2c/ibm,i2c-fsi.yaml | 76 + .../devicetree/bindings/spi/ibm,spi-fsi.yaml | 55 + MAINTAINERS | 2 +- arch/arm/boot/dts/aspeed/Makefile | 3 + .../aspeed/aspeed-bmc-ibm-blueridge-4u.dts | 21 + .../dts/aspeed/aspeed-bmc-ibm-blueridge.dts | 1691 +++++++ .../boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts | 3881 +++++++++++++++++ .../dts/aspeed/aspeed-bmc-ibm-huygens.dts | 23 + .../arm/boot/dts/aspeed/ibm-power11-quad.dtsi | 1539 +++++++ drivers/fsi/fsi-occ.c | 49 +- drivers/fsi/fsi-scom.c | 1 + 23 files changed, 7694 insertions(+), 137 deletions(-)create mode 100644
Documentation/devicetree/bindings/fsi/aspeed,ast2600-fsi-master.yamlcreate mode 100644Documentation/devicetree/bindings/fsi/fsi-controller.yamldelete mode 100644Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txtcreate mode 100644Documentation/devicetree/bindings/fsi/ibm,p9-fsi-controller.yamldelete mode 100644Documentation/devicetree/bindings/fsi/ibm,p9-occ.txtcreate mode 100644Documentation/devicetree/bindings/fsi/ibm,p9-occ.yamlcreate mode 100644Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.yamlcreate mode 100644Documentation/devicetree/bindings/fsi/ibm,p9-scom.yamldelete mode 100644Documentation/devicetree/bindings/i2c/i2c-fsi.txtcreate mode 100644Documentation/devicetree/bindings/i2c/ibm,i2c-fsi.yamlcreate mode 100644Documentation/devicetree/bindings/spi/ibm,spi-fsi.yamlcreate mode 100644arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge-4u.dtscreate mode 100644arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dtscreate mode 100644arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dtscreate mode 100644arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-huygens.dtscreate mode 100644arch/arm/boot/dts/aspeed/ibm-power11-quad.dtsi
Rob Herring
maintainerQuoted 14 lines · Eddie James
Add the Blueridge and Fuji BMC systems. Document many missing FSI related properties, and fix existing warnings. Make some minor fixes in OCC and SCOM drivers for the updated bindings.
Changes since v5:
- Switch from clock-frequency to bus-frequency for common FSI controller properties
- Add reg properties for AST2700 FSI controller
- Fix patternProperties for i2c bus nodes under FSI-based I2C controller
- Add bus-frequency for P11 FSI device tree node
- Change model name from Blueridge to Blueridge 2U
- Add missing reset gpio to led controller on Fuji
- Add Huygens (Rainier with modified FSI wiring)
Quoted 12 lines
Eddie James (20):
spi: dt-bindings: Document the IBM FSI-attached SPI controller
dt-bindings: fsi: fsi2spi: Document SPI controller child nodes
dt-bindings: fsi: Document the IBM SCOM engine
dt-bindings: fsi: p9-occ: Convert to json-schema
dt-bindings: fsi: Document the IBM SBEFIFO engine
dt-bindings: fsi: Document the FSI controller common properties
dt-bindings: fsi: ibm,i2cr-fsi-master: Reference common FSI controller
dt-bindings: fsi: ast2600-fsi-master: Convert to json-schema
dt-bindings: fsi: Document the AST2700 FSI controller
dt-bindings: fsi: Document the FSI Hub Controller
dt-bindings: i2c: i2c-fsi: Convert to json-schema
Looks like these haven't been applied, so I applied patches 2-11.
Quoted 9 lines
dt-bindings: arm: aspeed: add IBM P11 BMC boards
ARM: dts: aspeed: Add IBM P11 FSI devices
ARM: dts: aspeed: Add IBM P11 Blueridge BMC system
ARM: dts: aspeed: Add IBM P11 Blueridge 4U BMC system
ARM: dts: aspeed: Add IBM P11 Fuji BMC system
ARM: dts: aspeed: Add IBM Huygens BMC system
fsi: occ: Get device number from FSI minor number API
fsi: occ: Find next available child rather than node name match
fsi: scom: Update compatible string to match documentation