io-pgtable-arm + drm/msm: Extend iova fault debugging
Subsystems (6)
DRM drivers Arm Qualcomm mailing list IOMMU DRM driver for Qualcomm display hardware +2 more subsystems
v3 cover io-pgtable-arm + drm/msm: Extend iova fault debugging
From: Rob Clark <[email protected]>
This series extends io-pgtable-arm with a method to retrieve the page table entries traversed in the process of address translation, and then beefs up drm/msm gpu devcore dump to include this (and additional info) in the devcore dump.
This is a respin of https://patchwork.freedesktop.org/series/94968/
(minus a patch that was already merged)
v2: Fix an armv7/32b build error in the last patch
v3: Incorperate Will Deacon's suggestion to make the interface
callback based.
Rob Clark (2):
iommu/io-pgtable-arm: Add way to debug pgtable walk drm/msm: Extend gpu devcore dumps with pgtbl info
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 10 +++++ drivers/gpu/drm/msm/msm_gpu.c | 22 +++++++++++ drivers/gpu/drm/msm/msm_gpu.h | 8 ++++ drivers/gpu/drm/msm/msm_iommu.c | 18 +++++++++ drivers/gpu/drm/msm/msm_mmu.h | 5 ++- drivers/iommu/io-pgtable-arm.c | 50 ++++++++++++++++++++----- include/linux/io-pgtable.h | 4 ++ 7 files changed, 107 insertions(+), 10 deletions(-)
Signature · 1 line
2.45.1
PATCH v3 1/2 iommu/io-pgtable-arm: Add way to debug pgtable walk
From: Rob Clark <[email protected]>
Add an io-pgtable method to walk the pgtable returning the raw PTEs that would be traversed for a given iova access.
Signed-off-by Rob Clark <[email protected]>
--- drivers/iommu/io-pgtable-arm.c | 50 ++++++++++++++++++++++++++++------ include/linux/io-pgtable.h | 4 +++ 2 files changed, 45 insertions(+), 9 deletions(-)
drivers/iommu/io-pgtable-arm.c +41 -9
@@ -693,17 +693,19 @@ static size_t arm_lpae_unmap_pages(struct io_pgtable_ops *ops, unsigned long iov data->start_level, ptep); } -static phys_addr_t arm_lpae_iova_to_phys (struct io_pgtable_ops *ops, -unsigned long iova) +static int pgtable_walk (struct io_pgtable_ops *ops,unsigned long iova, +int (*cb)(void *cb_data,void *pte,int level), +void *cb_data) {struct arm_lpae_io_pgtable *data =io_pgtable_ops_to_data (ops);arm_lpae_iopte pte, *ptep = data->pgd;int lvl = data->start_level; +int ret; do { /* Valid IOPTE pointer? */ if (!ptep) - return 0; + return -EFAULT; /* Grab the IOPTE we're interested in */ ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
@@ -711,22 +713,52 @@ static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,/* Valid entry? */ if (!pte) -return 0 ; +return -EFAULT ; + + ret =cb (cb_data, &pte, lvl); +if (ret) +return ret; -/* Leaf entry? */ +/* Leaf entry? If so, we've found the translation */ if (iopte_leaf (pte, lvl, data->iop.fmt)) - goto found_translation; +return 0 ;/* Take it to the next level */ ptep =iopte_deref (pte, data); }while (++lvl <ARM_LPAE_MAX_LEVELS );/* Ran out of page tables to walk */ +return -EFAULT ; +} + +struct iova_to_phys_walk_data { +arm_lpae_iopte pte; +int level; +}; + +static int iova_to_phys_walk_cb (void *cb_data,void *pte,int level) +{ +struct iova_to_phys_walk_data *d = cb_data; + + d->pte = *(arm_lpae_iopte *)pte; + d->level = level; +return 0 ; +} + +static phys_addr_t arm_lpae_iova_to_phys (struct io_pgtable_ops *ops, +unsigned long iova) +{ +struct arm_lpae_io_pgtable *data =io_pgtable_ops_to_data (ops); +struct iova_to_phys_walk_data d; +int ret; + + ret =pgtable_walk (ops, iova, iova_to_phys_walk_cb, &d); +if (ret) +return 0 ; -found_translation: - iova &= (ARM_LPAE_BLOCK_SIZE (lvl, data) -1 ); -return iopte_to_paddr (pte, data) | iova; + iova &= (ARM_LPAE_BLOCK_SIZE (d.level, data) -1 ); +return iopte_to_paddr (d.pte, data) | iova; }static void arm_lpae_restrict_pgsizes (struct io_pgtable_cfg *cfg)
include/linux/io-pgtable.h +4 -0
@@ -177,6 +177,7 @@ struct io_pgtable_cfg {* @map_pages: Map a physically contiguous range of pages of the same size. * @unmap_pages: Unmap a range of virtually contiguous pages of the same size. * @iova_to_phys: Translate iova to physical address. +* @pgtable_walk: (optional) Perform a page table walk for a given iova. * * These functions map directly onto the iommu_ops member functions with * the same names.
@@ -190,6 +191,9 @@ struct io_pgtable_ops { struct iommu_iotlb_gather *gather);phys_addr_t (*iova_to_phys)(struct io_pgtable_ops *ops,unsigned long iova); +int (*pgtable_walk)(struct io_pgtable_ops *ops,unsigned long iova, +int (*cb)(void *cb_data,void *pte,int level), +void *cb_data); int (*read_and_clear_dirty)(struct io_pgtable_ops *ops, unsigned long iova, size_t size, unsigned long flags,
Signature · 1 line
2.45.1
PATCH v3 2/2 drm/msm: Extend gpu devcore dumps with pgtbl info
In reply to Rob ClarkFrom: Rob Clark <[email protected]>
In the case of iova fault triggered devcore dumps, include additional debug information based on what we think is the current page tables, including the TTBR0 value (which should match what we have in adreno_smmu_fault_info unless things have gone horribly wrong), and the pagetable entries traversed in the process of resolving the faulting iova.
Signed-off-by Rob Clark <[email protected]>
--- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 10 ++++++++++ drivers/gpu/drm/msm/msm_gpu.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/msm/msm_gpu.h | 8 ++++++++ drivers/gpu/drm/msm/msm_iommu.c | 18 ++++++++++++++++++ drivers/gpu/drm/msm/msm_mmu.h | 5 ++++- 5 files changed, 62 insertions(+), 1 deletion(-)
drivers/gpu/drm/msm/adreno/adreno_gpu.c +10 -0
@@ -861,6 +861,16 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,drm_printf (p," - dir=%s\n" , info->flags &IOMMU_FAULT_WRITE ?"WRITE" :"READ" );drm_printf (p," - type=%s\n" , info->type);drm_printf (p," - source=%s\n" , info->block); + +/* Information extracted from what we think are the current +* pgtables. Hopefully the TTBR0 matches what we've extracted +* from the SMMU registers in smmu_info! +*/ +drm_puts (p,"pgtable-fault-info:\n" ); +drm_printf (p," - ttbr0: %.16llx\n" , (u64 )info->pgtbl_ttbr0); +drm_printf (p," - asid: %d\n" , info->asid); +drm_printf (p," - ptes: %.16llx %.16llx %.16llx %.16llx\n" , + info->ptes[0 ], info->ptes[1 ], info->ptes[2 ], info->ptes[3 ]); }drm_printf (p,"rbbm-status: 0x%08x\n" , state->rbbm_status);
drivers/gpu/drm/msm/msm_gpu.c +22 -0
@@ -256,6 +256,18 @@ static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state, state->nr_bos++; } +static int pgtable_walk_cb (void *cb_data,void *pte,int level) +{ +struct msm_gpu_fault_info *info = cb_data; + +if (level >ARRAY_SIZE (info->ptes)) +return -EINVAL ; + + info->ptes[level] = *(u64 *)pte; + +return 0 ; +} +static void msm_gpu_crashstate_capture (struct msm_gpu *gpu,struct msm_gem_submit *submit,char *comm,char *cmd) {
@@ -281,6 +293,16 @@ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,if (submit) {int i; +if (state->fault_info.ttbr0) { +struct msm_gpu_fault_info *info = &state->fault_info; +struct msm_mmu *mmu = submit->aspace->mmu; + +msm_iommu_pagetable_params (mmu, &info->pgtbl_ttbr0, + &info->asid); +msm_iommu_pagetable_walk (mmu, info->iova, + pgtable_walk_cb, info); + } + state->bos =kcalloc (submit->nr_bos,sizeof (struct msm_gpu_state_bo ),GFP_KERNEL );
drivers/gpu/drm/msm/msm_gpu.h +8 -0
@@ -101,6 +101,14 @@ struct msm_gpu_fault_info {int flags;const char *type;const char *block; + +/* Information about what we think/expect is the current SMMU state, +* for example expected_ttbr0 should match smmu_info.ttbr0 which +* was read back from SMMU registers. +*/ +phys_addr_t pgtbl_ttbr0; +u64 ptes[4 ]; +int asid; };/**
drivers/gpu/drm/msm/msm_iommu.c +18 -0
@@ -195,6 +195,24 @@ struct iommu_domain_geometry *msm_iommu_get_geometry(struct msm_mmu *mmu)return &iommu->domain->geometry; } +int msm_iommu_pagetable_walk (struct msm_mmu *mmu,unsigned long iova, +int (*cb)(void *cb_data,void *pte,int level), +void *cb_data) +{ +struct msm_iommu_pagetable *pagetable; + +if (mmu->type !=MSM_MMU_IOMMU_PAGETABLE ) +return -EINVAL ; + + pagetable =to_pagetable (mmu); + +if (!pagetable->pgtbl_ops->pgtable_walk) +return -EINVAL ; + +return pagetable->pgtbl_ops->pgtable_walk (pagetable->pgtbl_ops, iova, + cb, cb_data); +} +static const struct msm_mmu_funcs pagetable_funcs = { .map = msm_iommu_pagetable_map, .unmap = msm_iommu_pagetable_unmap,
drivers/gpu/drm/msm/msm_mmu.h +4 -1
@@ -53,7 +53,10 @@ static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg,struct msm_mmu *msm_iommu_pagetable_create (struct msm_mmu *parent);int msm_iommu_pagetable_params (struct msm_mmu *mmu,phys_addr_t *ttbr, -int *asid); +int *asid); +int msm_iommu_pagetable_walk (struct msm_mmu *mmu,unsigned long iova, +int (*cb)(void *cb_data,void *pte,int level), +void *cb_data);struct iommu_domain_geometry *msm_iommu_get_geometry (struct msm_mmu *mmu);#endif /* __MSM_MMU_H__ */
Signature · 1 line
2.45.1