armada-370-xp irqchip updates round 2

index dce2b80bf439..66d6a2ebc8a5 100644
@@ -66,15 +66,14 @@
  *                   device
  *
  * The "global interrupt mask/unmask" is modified using the
- * ARMADA_370_XP_INT_SET_ENABLE_OFFS and
- * ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS registers, which are relative
- * to "main_int_base".
+ * ARMADA_370_XP_INT_SET_ENABLE and ARMADA_370_XP_INT_CLEAR_ENABLE
+ * registers, which are relative to "main_int_base".
  *
  * The "per-CPU mask/unmask" is modified using the
- * ARMADA_370_XP_INT_SET_MASK_OFFS and
- * ARMADA_370_XP_INT_CLEAR_MASK_OFFS registers, which are relative to
- * "per_cpu_int_base". This base address points to a special address,
- * which automatically accesses the registers of the current CPU.
+ * ARMADA_370_XP_INT_SET_MASK and ARMADA_370_XP_INT_CLEAR_MASK
+ * registers, which are relative to "per_cpu_int_base". This base
+ * address points to a special address, which automatically accesses
+ * the registers of the current CPU.
  *
  * The per-CPU mask/unmask can also be adjusted using the global
  * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use

@@ -118,21 +117,21 @@
 
 /* Registers relative to main_int_base */
 #define ARMADA_370_XP_INT_CONTROL		(0x00)
-#define ARMADA_370_XP_SW_TRIG_INT_OFFS		(0x04)
-#define ARMADA_370_XP_INT_SET_ENABLE_OFFS	(0x30)
-#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS	(0x34)
+#define ARMADA_370_XP_SW_TRIG_INT		(0x04)
+#define ARMADA_370_XP_INT_SET_ENABLE		(0x30)
+#define ARMADA_370_XP_INT_CLEAR_ENABLE		(0x34)
 #define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)
 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK	0xF
 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << cpuid)
 
 /* Registers relative to per_cpu_int_base */
-#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS	(0x08)
-#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS		(0x0c)
+#define ARMADA_370_XP_IN_DRBEL_CAUSE		(0x08)
+#define ARMADA_370_XP_IN_DRBEL_MSK		(0x0c)
 #define ARMADA_375_PPI_CAUSE			(0x10)
-#define ARMADA_370_XP_CPU_INTACK_OFFS		(0x44)
-#define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
-#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS	(0x4C)
-#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS	(0x54)
+#define ARMADA_370_XP_CPU_INTACK		(0x44)
+#define ARMADA_370_XP_INT_SET_MASK		(0x48)
+#define ARMADA_370_XP_INT_CLEAR_MASK		(0x4C)
+#define ARMADA_370_XP_INT_FABRIC_MASK		(0x54)
 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	(1 << cpu)
 
 #define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)

@@ -220,11 +219,9 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
 	if (!is_percpu_irq(hwirq))
-		writel(hwirq, main_int_base +
-				ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
+		writel(hwirq, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE);
 	else
-		writel(hwirq, per_cpu_int_base +
-				ARMADA_370_XP_INT_SET_MASK_OFFS);
+		writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK);
 }
 
 static void armada_370_xp_irq_unmask(struct irq_data *d)

@@ -232,11 +229,9 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
 	if (!is_percpu_irq(hwirq))
-		writel(hwirq, main_int_base +
-				ARMADA_370_XP_INT_SET_ENABLE_OFFS);
+		writel(hwirq, main_int_base + ARMADA_370_XP_INT_SET_ENABLE);
 	else
-		writel(hwirq, per_cpu_int_base +
-				ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+		writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 }
 
 #ifdef CONFIG_PCI_MSI

@@ -329,19 +324,18 @@ static void armada_370_xp_msi_reenable_percpu(void)
 	u32 reg;
 
 	/* Enable MSI doorbell mask and combined cpu local interrupt */
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 	reg |= msi_doorbell_mask();
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 
 	/* Unmask local doorbell interrupt */
-	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 }
 
 static int armada_370_xp_msi_init(struct device_node *node,
 				  phys_addr_t main_int_phys_base)
 {
-	msi_doorbell_addr = main_int_phys_base +
-		ARMADA_370_XP_SW_TRIG_INT_OFFS;
+	msi_doorbell_addr = main_int_phys_base + ARMADA_370_XP_SW_TRIG_INT;
 
 	armada_370_xp_msi_inner_domain =
 		irq_domain_add_linear(NULL, msi_doorbell_size(),

@@ -362,7 +356,7 @@ static int armada_370_xp_msi_init(struct device_node *node,
 
 	/* Unmask low 16 MSI irqs on non-IPI platforms */
 	if (!is_ipi_available())
-		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 
 	return 0;
 }

@@ -391,7 +385,7 @@ static void armada_xp_mpic_perf_init(void)
 
 	/* Enable Performance Counter Overflow interrupts */
 	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
-	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
+	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK);
 }
 
 #ifdef CONFIG_SMP

@@ -400,17 +394,17 @@ static struct irq_domain *ipi_domain;
 static void armada_370_xp_ipi_mask(struct irq_data *d)
 {
 	u32 reg;
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 	reg &= ~BIT(d->hwirq);
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 }
 
 static void armada_370_xp_ipi_unmask(struct irq_data *d)
 {
 	u32 reg;
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 	reg |= BIT(d->hwirq);
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 }
 
 static void armada_370_xp_ipi_send_mask(struct irq_data *d,

@@ -431,12 +425,12 @@ static void armada_370_xp_ipi_send_mask(struct irq_data *d,
 
 	/* submit softirq */
 	writel((map << 8) | d->hwirq, main_int_base +
-		ARMADA_370_XP_SW_TRIG_INT_OFFS);
+		ARMADA_370_XP_SW_TRIG_INT);
 }
 
 static void armada_370_xp_ipi_ack(struct irq_data *d)
 {
-	writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+	writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
 }
 
 static struct irq_chip ipi_irqchip = {

@@ -539,19 +533,19 @@ static void armada_xp_mpic_smp_cpu_init(void)
 	nr_irqs = (control >> 2) & 0x3ff;
 
 	for (i = 0; i < nr_irqs; i++)
-		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
+		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK);
 
 	if (!is_ipi_available())
 		return;
 
 	/* Disable all IPIs */
-	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 
 	/* Clear pending IPIs */
-	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
 
 	/* Unmask IPI interrupt */
-	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 }
 
 static void armada_xp_mpic_reenable_percpu(void)

@@ -622,9 +616,9 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 	armada_370_xp_irq_mask(irq_get_irq_data(virq));
 	if (!is_percpu_irq(hw))
 		writel(hw, per_cpu_int_base +
-			ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+			ARMADA_370_XP_INT_CLEAR_MASK);
 	else
-		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
+		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE);
 	irq_set_status_flags(virq, IRQ_LEVEL);
 
 	if (is_percpu_irq(hw)) {

@@ -651,12 +645,10 @@ static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
 {
 	u32 msimask, msinr;
 
-	msimask = readl_relaxed(per_cpu_int_base +
-				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+	msimask = readl_relaxed(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
 	msimask &= msi_doorbell_mask();
 
-	writel(~msimask, per_cpu_int_base +
-	       ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+	writel(~msimask, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
 
 	for (msinr = msi_doorbell_start();
 	     msinr < msi_doorbell_end(); msinr++) {

@@ -712,7 +704,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 
 	do {
 		irqstat = readl_relaxed(per_cpu_int_base +
-					ARMADA_370_XP_CPU_INTACK_OFFS);
+					ARMADA_370_XP_CPU_INTACK);
 		irqnr = irqstat & 0x3FF;
 
 		if (irqnr > 1022)

@@ -735,7 +727,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 			int ipi;
 
 			ipimask = readl_relaxed(per_cpu_int_base +
-						ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
+						ARMADA_370_XP_IN_DRBEL_CAUSE)
 				& IPI_DOORBELL_MASK;
 
 			for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END)

@@ -748,8 +740,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 
 static int armada_370_xp_mpic_suspend(void)
 {
-	doorbell_mask_reg = readl(per_cpu_int_base +
-				  ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	doorbell_mask_reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 	return 0;
 }
 

@@ -774,13 +765,13 @@ static void armada_370_xp_mpic_resume(void)
 		if (!is_percpu_irq(irq)) {
 			/* Non per-CPU interrupts */
 			writel(irq, per_cpu_int_base +
-			       ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+			       ARMADA_370_XP_INT_CLEAR_MASK);
 			if (!irqd_irq_disabled(data))
 				armada_370_xp_irq_unmask(data);
 		} else {
 			/* Per-CPU interrupts */
 			writel(irq, main_int_base +
-			       ARMADA_370_XP_INT_SET_ENABLE_OFFS);
+			       ARMADA_370_XP_INT_SET_ENABLE);
 
 			/*
 			 * Re-enable on the current CPU,

@@ -794,7 +785,7 @@ static void armada_370_xp_mpic_resume(void)
 
 	/* Reconfigure doorbells for IPIs and MSIs */
 	writel(doorbell_mask_reg,
-	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 
 	if (is_ipi_available()) {
 		src0 = doorbell_mask_reg & IPI_DOORBELL_MASK;

@@ -805,9 +796,9 @@ static void armada_370_xp_mpic_resume(void)
 	}
 
 	if (src0)
-		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 	if (src1)
-		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 
 	if (is_ipi_available())
 		ipi_resume();

@@ -847,7 +838,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 	nr_irqs = (control >> 2) & 0x3ff;
 
 	for (i = 0; i < nr_irqs; i++)
-		writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
+		writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE);
 
 	armada_370_xp_mpic_domain =
 		irq_domain_add_linear(node, nr_irqs,

index 66d6a2ebc8a5..588a9e2e1887 100644
@@ -126,7 +126,7 @@
 
 /* Registers relative to per_cpu_int_base */
 #define ARMADA_370_XP_IN_DRBEL_CAUSE		(0x08)
-#define ARMADA_370_XP_IN_DRBEL_MSK		(0x0c)
+#define ARMADA_370_XP_IN_DRBEL_MASK		(0x0c)
 #define ARMADA_375_PPI_CAUSE			(0x10)
 #define ARMADA_370_XP_CPU_INTACK		(0x44)
 #define ARMADA_370_XP_INT_SET_MASK		(0x48)

@@ -324,9 +324,9 @@ static void armada_370_xp_msi_reenable_percpu(void)
 	u32 reg;
 
 	/* Enable MSI doorbell mask and combined cpu local interrupt */
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 	reg |= msi_doorbell_mask();
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 
 	/* Unmask local doorbell interrupt */
 	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);

@@ -394,17 +394,17 @@ static struct irq_domain *ipi_domain;
 static void armada_370_xp_ipi_mask(struct irq_data *d)
 {
 	u32 reg;
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 	reg &= ~BIT(d->hwirq);
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 }
 
 static void armada_370_xp_ipi_unmask(struct irq_data *d)
 {
 	u32 reg;
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 	reg |= BIT(d->hwirq);
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 }
 
 static void armada_370_xp_ipi_send_mask(struct irq_data *d,

@@ -539,7 +539,7 @@ static void armada_xp_mpic_smp_cpu_init(void)
 		return;
 
 	/* Disable all IPIs */
-	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 
 	/* Clear pending IPIs */
 	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);

@@ -740,7 +740,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 
 static int armada_370_xp_mpic_suspend(void)
 {
-	doorbell_mask_reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	doorbell_mask_reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 	return 0;
 }
 

@@ -785,7 +785,7 @@ static void armada_370_xp_mpic_resume(void)
 
 	/* Reconfigure doorbells for IPIs and MSIs */
 	writel(doorbell_mask_reg,
-	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 
 	if (is_ipi_available()) {
 		src0 = doorbell_mask_reg & IPI_DOORBELL_MASK;

index 588a9e2e1887..427ba5fd6adc 100644
@@ -137,13 +137,13 @@
 #define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)
 
 /* IPI and MSI interrupt definitions for IPI platforms */
-#define IPI_DOORBELL_START                      (0)
-#define IPI_DOORBELL_END                        (8)
-#define IPI_DOORBELL_MASK                       0xFF
-#define PCI_MSI_DOORBELL_START                  (16)
-#define PCI_MSI_DOORBELL_NR                     (16)
-#define PCI_MSI_DOORBELL_END                    (32)
-#define PCI_MSI_DOORBELL_MASK                   0xFFFF0000
+#define IPI_DOORBELL_START			(0)
+#define IPI_DOORBELL_END			(8)
+#define IPI_DOORBELL_MASK			0xFF
+#define PCI_MSI_DOORBELL_START			(16)
+#define PCI_MSI_DOORBELL_NR			(16)
+#define PCI_MSI_DOORBELL_END			(32)
+#define PCI_MSI_DOORBELL_MASK			0xFFFF0000
 
 /* MSI interrupt definitions for non-IPI platforms */
 #define PCI_MSI_FULL_DOORBELL_START		0

index 427ba5fd6adc..18aca9b5d3b3 100644
@@ -121,7 +121,7 @@
 #define ARMADA_370_XP_INT_SET_ENABLE		(0x30)
 #define ARMADA_370_XP_INT_CLEAR_ENABLE		(0x34)
 #define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)
-#define ARMADA_370_XP_INT_SOURCE_CPU_MASK	0xF
+#define ARMADA_370_XP_INT_SOURCE_CPU_MASK	GENMASK(3, 0)
 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << cpuid)
 
 /* Registers relative to per_cpu_int_base */

@@ -132,18 +132,18 @@
 #define ARMADA_370_XP_INT_SET_MASK		(0x48)
 #define ARMADA_370_XP_INT_CLEAR_MASK		(0x4C)
 #define ARMADA_370_XP_INT_FABRIC_MASK		(0x54)
-#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	(1 << cpu)
+#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	BIT(cpu)
 
 #define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)
 
 /* IPI and MSI interrupt definitions for IPI platforms */
 #define IPI_DOORBELL_START			(0)
 #define IPI_DOORBELL_END			(8)
-#define IPI_DOORBELL_MASK			0xFF
+#define IPI_DOORBELL_MASK			GENMASK(7, 0)
 #define PCI_MSI_DOORBELL_START			(16)
 #define PCI_MSI_DOORBELL_NR			(16)
 #define PCI_MSI_DOORBELL_END			(32)
-#define PCI_MSI_DOORBELL_MASK			0xFFFF0000
+#define PCI_MSI_DOORBELL_MASK			GENMASK(31, 16)
 
 /* MSI interrupt definitions for non-IPI platforms */
 #define PCI_MSI_FULL_DOORBELL_START		0

@@ -415,7 +415,7 @@ static void armada_370_xp_ipi_send_mask(struct irq_data *d,
 
 	/* Convert our logical CPU mask into a physical one. */
 	for_each_cpu(cpu, mask)
-		map |= 1 << cpu_logical_map(cpu);
+		map |= BIT(cpu_logical_map(cpu));
 
 	/*
 	 * Ensure that stores to Normal memory are visible to the

index 18aca9b5d3b3..14d213e9b0d2 100644
@@ -116,33 +116,33 @@
  */
 
 /* Registers relative to main_int_base */
-#define ARMADA_370_XP_INT_CONTROL		(0x00)
-#define ARMADA_370_XP_SW_TRIG_INT		(0x04)
-#define ARMADA_370_XP_INT_SET_ENABLE		(0x30)
-#define ARMADA_370_XP_INT_CLEAR_ENABLE		(0x34)
-#define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)
+#define ARMADA_370_XP_INT_CONTROL		0x00
+#define ARMADA_370_XP_SW_TRIG_INT		0x04
+#define ARMADA_370_XP_INT_SET_ENABLE		0x30
+#define ARMADA_370_XP_INT_CLEAR_ENABLE		0x34
+#define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + (irq) * 4)
 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK	GENMASK(3, 0)
-#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << cpuid)
+#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << (cpuid))
 
 /* Registers relative to per_cpu_int_base */
-#define ARMADA_370_XP_IN_DRBEL_CAUSE		(0x08)
-#define ARMADA_370_XP_IN_DRBEL_MASK		(0x0c)
-#define ARMADA_375_PPI_CAUSE			(0x10)
-#define ARMADA_370_XP_CPU_INTACK		(0x44)
-#define ARMADA_370_XP_INT_SET_MASK		(0x48)
-#define ARMADA_370_XP_INT_CLEAR_MASK		(0x4C)
-#define ARMADA_370_XP_INT_FABRIC_MASK		(0x54)
+#define ARMADA_370_XP_IN_DRBEL_CAUSE		0x08
+#define ARMADA_370_XP_IN_DRBEL_MASK		0x0c
+#define ARMADA_375_PPI_CAUSE			0x10
+#define ARMADA_370_XP_CPU_INTACK		0x44
+#define ARMADA_370_XP_INT_SET_MASK		0x48
+#define ARMADA_370_XP_INT_CLEAR_MASK		0x4C
+#define ARMADA_370_XP_INT_FABRIC_MASK		0x54
 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	BIT(cpu)
 
-#define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)
+#define ARMADA_370_XP_MAX_PER_CPU_IRQS		28
 
 /* IPI and MSI interrupt definitions for IPI platforms */
-#define IPI_DOORBELL_START			(0)
-#define IPI_DOORBELL_END			(8)
+#define IPI_DOORBELL_START			0
+#define IPI_DOORBELL_END			8
 #define IPI_DOORBELL_MASK			GENMASK(7, 0)
-#define PCI_MSI_DOORBELL_START			(16)
-#define PCI_MSI_DOORBELL_NR			(16)
-#define PCI_MSI_DOORBELL_END			(32)
+#define PCI_MSI_DOORBELL_START			16
+#define PCI_MSI_DOORBELL_NR			16
+#define PCI_MSI_DOORBELL_END			32
 #define PCI_MSI_DOORBELL_MASK			GENMASK(31, 16)
 
 /* MSI interrupt definitions for non-IPI platforms */

index 14d213e9b0d2..8f52de6d8921 100644
@@ -66,18 +66,17 @@
  *                   device
  *
  * The "global interrupt mask/unmask" is modified using the
- * ARMADA_370_XP_INT_SET_ENABLE and ARMADA_370_XP_INT_CLEAR_ENABLE
+ * MPIC_INT_SET_ENABLE and MPIC_INT_CLEAR_ENABLE
  * registers, which are relative to "main_int_base".
  *
- * The "per-CPU mask/unmask" is modified using the
- * ARMADA_370_XP_INT_SET_MASK and ARMADA_370_XP_INT_CLEAR_MASK
- * registers, which are relative to "per_cpu_int_base". This base
- * address points to a special address, which automatically accesses
- * the registers of the current CPU.
+ * The "per-CPU mask/unmask" is modified using the MPIC_INT_SET_MASK
+ * and MPIC_INT_CLEAR_MASK registers, which are relative to
+ * "per_cpu_int_base". This base address points to a special address,
+ * which automatically accesses the registers of the current CPU.
  *
  * The per-CPU mask/unmask can also be adjusted using the global
- * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use
- * to configure interrupt affinity.
+ * per-interrupt MPIC_INT_SOURCE_CTL register, which we use to
+ * configure interrupt affinity.
  *
  * Due to this model, all interrupts need to be mask/unmasked at two
  * different levels: at the global level and at the per-CPU level.

@@ -91,9 +90,8 @@
  *    the current CPU, running the ->map() code. This allows to have
  *    the interrupt unmasked at this level in non-SMP
  *    configurations. In SMP configurations, the ->set_affinity()
- *    callback is called, which using the
- *    ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask
- *    for the interrupt.
+ *    callback is called, which using the MPIC_INT_SOURCE_CTL()
+ *    readjusts the per-CPU mask/unmask for the interrupt.
  *
  *    The ->mask() and ->unmask() operations only mask/unmask the
  *    interrupt at the "global" level.

@@ -116,25 +114,25 @@
  */
 
 /* Registers relative to main_int_base */
-#define ARMADA_370_XP_INT_CONTROL		0x00
-#define ARMADA_370_XP_SW_TRIG_INT		0x04
-#define ARMADA_370_XP_INT_SET_ENABLE		0x30
-#define ARMADA_370_XP_INT_CLEAR_ENABLE		0x34
-#define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + (irq) * 4)
-#define ARMADA_370_XP_INT_SOURCE_CPU_MASK	GENMASK(3, 0)
-#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << (cpuid))
+#define MPIC_INT_CONTROL			0x00
+#define MPIC_SW_TRIG_INT			0x04
+#define MPIC_INT_SET_ENABLE			0x30
+#define MPIC_INT_CLEAR_ENABLE			0x34
+#define MPIC_INT_SOURCE_CTL(irq)		(0x100 + (irq) * 4)
+#define MPIC_INT_SOURCE_CPU_MASK		GENMASK(3, 0)
+#define MPIC_INT_IRQ_FIQ_MASK(cpuid)		((BIT(0) | BIT(8)) << (cpuid))
 
 /* Registers relative to per_cpu_int_base */
-#define ARMADA_370_XP_IN_DRBEL_CAUSE		0x08
-#define ARMADA_370_XP_IN_DRBEL_MASK		0x0c
-#define ARMADA_375_PPI_CAUSE			0x10
-#define ARMADA_370_XP_CPU_INTACK		0x44
-#define ARMADA_370_XP_INT_SET_MASK		0x48
-#define ARMADA_370_XP_INT_CLEAR_MASK		0x4C
-#define ARMADA_370_XP_INT_FABRIC_MASK		0x54
-#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	BIT(cpu)
+#define MPIC_IN_DRBEL_CAUSE			0x08
+#define MPIC_IN_DRBEL_MASK			0x0c
+#define MPIC_PPI_CAUSE				0x10
+#define MPIC_CPU_INTACK				0x44
+#define MPIC_INT_SET_MASK			0x48
+#define MPIC_INT_CLEAR_MASK			0x4C
+#define MPIC_INT_FABRIC_MASK			0x54
+#define MPIC_INT_CAUSE_PERF(cpu)		BIT(cpu)
 
-#define ARMADA_370_XP_MAX_PER_CPU_IRQS		28
+#define MPIC_MAX_PER_CPU_IRQS			28
 
 /* IPI and MSI interrupt definitions for IPI platforms */
 #define IPI_DOORBELL_START			0

@@ -203,7 +201,7 @@ static inline unsigned int msi_doorbell_end(void)
 
 static inline bool is_percpu_irq(irq_hw_number_t irq)
 {
-	if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
+	if (irq <= MPIC_MAX_PER_CPU_IRQS)
 		return true;
 
 	return false;

@@ -219,9 +217,9 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
 	if (!is_percpu_irq(hwirq))
-		writel(hwirq, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE);
+		writel(hwirq, main_int_base + MPIC_INT_CLEAR_ENABLE);
 	else
-		writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK);
+		writel(hwirq, per_cpu_int_base + MPIC_INT_SET_MASK);
 }
 
 static void armada_370_xp_irq_unmask(struct irq_data *d)

@@ -229,9 +227,9 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
 	if (!is_percpu_irq(hwirq))
-		writel(hwirq, main_int_base + ARMADA_370_XP_INT_SET_ENABLE);
+		writel(hwirq, main_int_base + MPIC_INT_SET_ENABLE);
 	else
-		writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+		writel(hwirq, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 }
 
 #ifdef CONFIG_PCI_MSI

@@ -324,18 +322,18 @@ static void armada_370_xp_msi_reenable_percpu(void)
 	u32 reg;
 
 	/* Enable MSI doorbell mask and combined cpu local interrupt */
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 	reg |= msi_doorbell_mask();
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 
 	/* Unmask local doorbell interrupt */
-	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+	writel(1, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 }
 
 static int armada_370_xp_msi_init(struct device_node *node,
 				  phys_addr_t main_int_phys_base)
 {
-	msi_doorbell_addr = main_int_phys_base + ARMADA_370_XP_SW_TRIG_INT;
+	msi_doorbell_addr = main_int_phys_base + MPIC_SW_TRIG_INT;
 
 	armada_370_xp_msi_inner_domain =
 		irq_domain_add_linear(NULL, msi_doorbell_size(),

@@ -356,7 +354,7 @@ static int armada_370_xp_msi_init(struct device_node *node,
 
 	/* Unmask low 16 MSI irqs on non-IPI platforms */
 	if (!is_ipi_available())
-		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+		writel(0, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 
 	return 0;
 }

@@ -384,8 +382,8 @@ static void armada_xp_mpic_perf_init(void)
 	cpuid = cpu_logical_map(smp_processor_id());
 
 	/* Enable Performance Counter Overflow interrupts */
-	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
-	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK);
+	writel(MPIC_INT_CAUSE_PERF(cpuid),
+	       per_cpu_int_base + MPIC_INT_FABRIC_MASK);
 }
 
 #ifdef CONFIG_SMP

@@ -394,17 +392,17 @@ static struct irq_domain *ipi_domain;
 static void armada_370_xp_ipi_mask(struct irq_data *d)
 {
 	u32 reg;
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 	reg &= ~BIT(d->hwirq);
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 }
 
 static void armada_370_xp_ipi_unmask(struct irq_data *d)
 {
 	u32 reg;
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 	reg |= BIT(d->hwirq);
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 }
 
 static void armada_370_xp_ipi_send_mask(struct irq_data *d,

@@ -424,13 +422,12 @@ static void armada_370_xp_ipi_send_mask(struct irq_data *d,
 	dsb();
 
 	/* submit softirq */
-	writel((map << 8) | d->hwirq, main_int_base +
-		ARMADA_370_XP_SW_TRIG_INT);
+	writel((map << 8) | d->hwirq, main_int_base + MPIC_SW_TRIG_INT);
 }
 
 static void armada_370_xp_ipi_ack(struct irq_data *d)
 {
-	writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
+	writel(~BIT(d->hwirq), per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
 }
 
 static struct irq_chip ipi_irqchip = {

@@ -515,9 +512,8 @@ static int armada_xp_set_affinity(struct irq_data *d,
 	/* Select a single core from the affinity mask which is online */
 	cpu = cpumask_any_and(mask_val, cpu_online_mask);
 
-	atomic_io_modify(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq),
-			 ARMADA_370_XP_INT_SOURCE_CPU_MASK,
-			 BIT(cpu_logical_map(cpu)));
+	atomic_io_modify(main_int_base + MPIC_INT_SOURCE_CTL(hwirq),
+			 MPIC_INT_SOURCE_CPU_MASK, BIT(cpu_logical_map(cpu)));
 
 	irq_data_update_effective_affinity(d, cpumask_of(cpu));
 

@@ -529,23 +525,23 @@ static void armada_xp_mpic_smp_cpu_init(void)
 	u32 control;
 	int nr_irqs, i;
 
-	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
+	control = readl(main_int_base + MPIC_INT_CONTROL);
 	nr_irqs = (control >> 2) & 0x3ff;
 
 	for (i = 0; i < nr_irqs; i++)
-		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK);
+		writel(i, per_cpu_int_base + MPIC_INT_SET_MASK);
 
 	if (!is_ipi_available())
 		return;
 
 	/* Disable all IPIs */
-	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	writel(0, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 
 	/* Clear pending IPIs */
-	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
+	writel(0, per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
 
 	/* Unmask IPI interrupt */
-	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+	writel(0, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 }
 
 static void armada_xp_mpic_reenable_percpu(void)

@@ -553,7 +549,7 @@ static void armada_xp_mpic_reenable_percpu(void)
 	unsigned int irq;
 
 	/* Re-enable per-CPU interrupts that were enabled before suspend */
-	for (irq = 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) {
+	for (irq = 0; irq < MPIC_MAX_PER_CPU_IRQS; irq++) {
 		struct irq_data *data;
 		int virq;
 

@@ -615,10 +611,9 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 
 	armada_370_xp_irq_mask(irq_get_irq_data(virq));
 	if (!is_percpu_irq(hw))
-		writel(hw, per_cpu_int_base +
-			ARMADA_370_XP_INT_CLEAR_MASK);
+		writel(hw, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 	else
-		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE);
+		writel(hw, main_int_base + MPIC_INT_SET_ENABLE);
 	irq_set_status_flags(virq, IRQ_LEVEL);
 
 	if (is_percpu_irq(hw)) {

@@ -645,10 +640,10 @@ static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
 {
 	u32 msimask, msinr;
 
-	msimask = readl_relaxed(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
+	msimask = readl_relaxed(per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
 	msimask &= msi_doorbell_mask();
 
-	writel(~msimask, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
+	writel(~msimask, per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
 
 	for (msinr = msi_doorbell_start();
 	     msinr < msi_doorbell_end(); msinr++) {

@@ -673,17 +668,16 @@ static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
 
 	chained_irq_enter(chip, desc);
 
-	irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
+	irqmap = readl_relaxed(per_cpu_int_base + MPIC_PPI_CAUSE);
 	cpuid = cpu_logical_map(smp_processor_id());
 
 	for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
-		irqsrc = readl_relaxed(main_int_base +
-				       ARMADA_370_XP_INT_SOURCE_CTL(irqn));
+		irqsrc = readl_relaxed(main_int_base + MPIC_INT_SOURCE_CTL(irqn));
 
 		/* Check if the interrupt is not masked on current CPU.
 		 * Test IRQ (0-1) and FIQ (8-9) mask bits.
 		 */
-		if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
+		if (!(irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)))
 			continue;
 
 		if (irqn == 0 || irqn == 1) {

@@ -703,8 +697,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 	u32 irqstat, irqnr;
 
 	do {
-		irqstat = readl_relaxed(per_cpu_int_base +
-					ARMADA_370_XP_CPU_INTACK);
+		irqstat = readl_relaxed(per_cpu_int_base + MPIC_CPU_INTACK);
 		irqnr = irqstat & 0x3FF;
 
 		if (irqnr > 1022)

@@ -727,7 +720,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 			int ipi;
 
 			ipimask = readl_relaxed(per_cpu_int_base +
-						ARMADA_370_XP_IN_DRBEL_CAUSE)
+						MPIC_IN_DRBEL_CAUSE)
 				& IPI_DOORBELL_MASK;
 
 			for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END)

@@ -740,7 +733,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 
 static int armada_370_xp_mpic_suspend(void)
 {
-	doorbell_mask_reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	doorbell_mask_reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 	return 0;
 }
 

@@ -751,7 +744,7 @@ static void armada_370_xp_mpic_resume(void)
 	irq_hw_number_t irq;
 
 	/* Re-enable interrupts */
-	nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
+	nirqs = (readl(main_int_base + MPIC_INT_CONTROL) >> 2) & 0x3ff;
 	for (irq = 0; irq < nirqs; irq++) {
 		struct irq_data *data;
 		int virq;

@@ -764,14 +757,12 @@ static void armada_370_xp_mpic_resume(void)
 
 		if (!is_percpu_irq(irq)) {
 			/* Non per-CPU interrupts */
-			writel(irq, per_cpu_int_base +
-			       ARMADA_370_XP_INT_CLEAR_MASK);
+			writel(irq, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 			if (!irqd_irq_disabled(data))
 				armada_370_xp_irq_unmask(data);
 		} else {
 			/* Per-CPU interrupts */
-			writel(irq, main_int_base +
-			       ARMADA_370_XP_INT_SET_ENABLE);
+			writel(irq, main_int_base + MPIC_INT_SET_ENABLE);
 
 			/*
 			 * Re-enable on the current CPU,

@@ -784,8 +775,7 @@ static void armada_370_xp_mpic_resume(void)
 	}
 
 	/* Reconfigure doorbells for IPIs and MSIs */
-	writel(doorbell_mask_reg,
-	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	writel(doorbell_mask_reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 
 	if (is_ipi_available()) {
 		src0 = doorbell_mask_reg & IPI_DOORBELL_MASK;

@@ -796,9 +786,9 @@ static void armada_370_xp_mpic_resume(void)
 	}
 
 	if (src0)
-		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+		writel(0, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 	if (src1)
-		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+		writel(1, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 
 	if (is_ipi_available())
 		ipi_resume();

@@ -834,11 +824,11 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 				   resource_size(&per_cpu_int_res));
 	BUG_ON(!per_cpu_int_base);
 
-	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
+	control = readl(main_int_base + MPIC_INT_CONTROL);
 	nr_irqs = (control >> 2) & 0x3ff;
 
 	for (i = 0; i < nr_irqs; i++)
-		writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE);
+		writel(i, main_int_base + MPIC_INT_CLEAR_ENABLE);
 
 	armada_370_xp_mpic_domain =
 		irq_domain_add_linear(node, nr_irqs,

index 8f52de6d8921..b9631cc25c0b 100644
@@ -409,7 +409,7 @@ static void armada_370_xp_ipi_send_mask(struct irq_data *d,
 					const struct cpumask *mask)
 {
 	unsigned long map = 0;
-	int cpu;
+	unsigned int cpu;
 
 	/* Convert our logical CPU mask into a physical one. */
 	for_each_cpu(cpu, mask)

@@ -507,7 +507,7 @@ static int armada_xp_set_affinity(struct irq_data *d,
 				  const struct cpumask *mask_val, bool force)
 {
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
-	int cpu;
+	unsigned int cpu;
 
 	/* Select a single core from the affinity mask which is online */
 	cpu = cpumask_any_and(mask_val, cpu_online_mask);

index b9631cc25c0b..cfd6dc803150 100644
@@ -201,10 +201,7 @@ static inline unsigned int msi_doorbell_end(void)
 
 static inline bool is_percpu_irq(irq_hw_number_t irq)
 {
-	if (irq <= MPIC_MAX_PER_CPU_IRQS)
-		return true;
-
-	return false;
+	return irq <= MPIC_MAX_PER_CPU_IRQS;
 }
 
 /*

index cfd6dc803150..3d15d0bb7605 100644
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Marvell Armada 370 and Armada XP SoC IRQ handling
  *

@@ -7,10 +8,6 @@
  * Gregory CLEMENT <[email protected]>
  * Thomas Petazzoni <[email protected]>
  * Ben Dooks <[email protected]>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/bits.h>

index 3d15d0bb7605..22e1a493abae 100644
@@ -276,7 +276,7 @@ static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
 static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
 				   unsigned int nr_irqs, void *args)
 {
-	int hwirq, i;
+	int hwirq;
 
 	mutex_lock(&msi_used_lock);
 	hwirq = bitmap_find_free_region(msi_used, msi_doorbell_size(),

@@ -286,7 +286,7 @@ static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
 	if (hwirq < 0)
 		return -ENOSPC;
 
-	for (i = 0; i < nr_irqs; i++) {
+	for (int i = 0; i < nr_irqs; i++) {
 		irq_domain_set_info(domain, virq + i, hwirq + i,
 				    &armada_370_xp_msi_bottom_irq_chip,
 				    domain->host_data, handle_simple_irq,

@@ -436,9 +436,7 @@ static int armada_370_xp_ipi_alloc(struct irq_domain *d,
 					 unsigned int virq,
 					 unsigned int nr_irqs, void *args)
 {
-	int i;
-
-	for (i = 0; i < nr_irqs; i++) {
+	for (int i = 0; i < nr_irqs; i++) {
 		irq_set_percpu_devid(virq + i);
 		irq_domain_set_info(d, virq + i, i, &ipi_irqchip,
 				    d->host_data,

@@ -463,9 +461,7 @@ static const struct irq_domain_ops ipi_domain_ops = {
 
 static void ipi_resume(void)
 {
-	int i;
-
-	for (i = 0; i < IPI_DOORBELL_END; i++) {
+	for (int i = 0; i < IPI_DOORBELL_END; i++) {
 		int irq;
 
 		irq = irq_find_mapping(ipi_domain, i);

@@ -517,12 +513,12 @@ static int armada_xp_set_affinity(struct irq_data *d,
 static void armada_xp_mpic_smp_cpu_init(void)
 {
 	u32 control;
-	int nr_irqs, i;
+	int nr_irqs;
 
 	control = readl(main_int_base + MPIC_INT_CONTROL);
 	nr_irqs = (control >> 2) & 0x3ff;
 
-	for (i = 0; i < nr_irqs; i++)
+	for (int i = 0; i < nr_irqs; i++)
 		writel(i, per_cpu_int_base + MPIC_INT_SET_MASK);
 
 	if (!is_ipi_available())

@@ -540,10 +536,8 @@ static void armada_xp_mpic_smp_cpu_init(void)
 
 static void armada_xp_mpic_reenable_percpu(void)
 {
-	unsigned int irq;
-
 	/* Re-enable per-CPU interrupts that were enabled before suspend */
-	for (irq = 0; irq < MPIC_MAX_PER_CPU_IRQS; irq++) {
+	for (unsigned int irq = 0; irq < MPIC_MAX_PER_CPU_IRQS; irq++) {
 		struct irq_data *data;
 		int virq;
 

@@ -735,11 +729,10 @@ static void armada_370_xp_mpic_resume(void)
 {
 	bool src0, src1;
 	int nirqs;
-	irq_hw_number_t irq;
 
 	/* Re-enable interrupts */
 	nirqs = (readl(main_int_base + MPIC_INT_CONTROL) >> 2) & 0x3ff;
-	for (irq = 0; irq < nirqs; irq++) {
+	for (irq_hw_number_t irq = 0; irq < nirqs; irq++) {
 		struct irq_data *data;
 		int virq;
 

@@ -797,7 +790,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 					     struct device_node *parent)
 {
 	struct resource main_int_res, per_cpu_int_res;
-	int nr_irqs, i;
+	int nr_irqs;
 	u32 control;
 
 	BUG_ON(of_address_to_resource(node, 0, &main_int_res));

@@ -821,7 +814,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 	control = readl(main_int_base + MPIC_INT_CONTROL);
 	nr_irqs = (control >> 2) & 0x3ff;
 
-	for (i = 0; i < nr_irqs; i++)
+	for (int i = 0; i < nr_irqs; i++)
 		writel(i, main_int_base + MPIC_INT_CLEAR_ENABLE);
 
 	armada_370_xp_mpic_domain =

index 22e1a493abae..d8b0609a9160 100644
@@ -462,16 +462,13 @@ static const struct irq_domain_ops ipi_domain_ops = {
 static void ipi_resume(void)
 {
 	for (int i = 0; i < IPI_DOORBELL_END; i++) {
-		int irq;
+		unsigned int virq = irq_find_mapping(ipi_domain, i);
 
-		irq = irq_find_mapping(ipi_domain, i);
-		if (irq <= 0)
+		if (!virq || !irq_percpu_is_enabled(virq))
 			continue;
-		if (irq_percpu_is_enabled(irq)) {
-			struct irq_data *d;
-			d = irq_domain_get_irq_data(ipi_domain, irq);
-			armada_370_xp_ipi_unmask(d);
-		}
+
+		armada_370_xp_ipi_unmask(irq_domain_get_irq_data(ipi_domain,
+								 virq));
 	}
 }
 

index d8b0609a9160..afd3a9c5b40c 100644
@@ -539,7 +539,7 @@ static void armada_xp_mpic_reenable_percpu(void)
 		int virq;
 
 		virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
-		if (virq == 0)
+		if (!virq)
 			continue;
 
 		data = irq_get_irq_data(virq);

@@ -734,7 +734,7 @@ static void armada_370_xp_mpic_resume(void)
 		int virq;
 
 		virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
-		if (virq == 0)
+		if (!virq)
 			continue;
 
 		data = irq_get_irq_data(virq);

index afd3a9c5b40c..5db1c6da938d 100644
@@ -229,9 +229,9 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
 #ifdef CONFIG_PCI_MSI
 
 static struct irq_chip armada_370_xp_msi_irq_chip = {
-	.name = "MPIC MSI",
-	.irq_mask = pci_msi_mask_irq,
-	.irq_unmask = pci_msi_unmask_irq,
+	.name		= "MPIC MSI",
+	.irq_mask	= pci_msi_mask_irq,
+	.irq_unmask	= pci_msi_unmask_irq,
 };
 
 static struct msi_domain_info armada_370_xp_msi_domain_info = {

@@ -386,6 +386,7 @@ static struct irq_domain *ipi_domain;
 static void armada_370_xp_ipi_mask(struct irq_data *d)
 {
 	u32 reg;
+
 	reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 	reg &= ~BIT(d->hwirq);
 	writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);

@@ -394,6 +395,7 @@ static void armada_370_xp_ipi_mask(struct irq_data *d)
 static void armada_370_xp_ipi_unmask(struct irq_data *d)
 {
 	u32 reg;
+
 	reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 	reg |= BIT(d->hwirq);
 	writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);

@@ -432,24 +434,20 @@ static struct irq_chip ipi_irqchip = {
 	.ipi_send_mask	= armada_370_xp_ipi_send_mask,
 };
 
-static int armada_370_xp_ipi_alloc(struct irq_domain *d,
-					 unsigned int virq,
-					 unsigned int nr_irqs, void *args)
+static int armada_370_xp_ipi_alloc(struct irq_domain *d, unsigned int virq,
+				   unsigned int nr_irqs, void *args)
 {
 	for (int i = 0; i < nr_irqs; i++) {
 		irq_set_percpu_devid(virq + i);
-		irq_domain_set_info(d, virq + i, i, &ipi_irqchip,
-				    d->host_data,
-				    handle_percpu_devid_irq,
-				    NULL, NULL);
+		irq_domain_set_info(d, virq + i, i, &ipi_irqchip, d->host_data,
+				    handle_percpu_devid_irq, NULL, NULL);
 	}
 
 	return 0;
 }
 
-static void armada_370_xp_ipi_free(struct irq_domain *d,
-					 unsigned int virq,
-					 unsigned int nr_irqs)
+static void armada_370_xp_ipi_free(struct irq_domain *d, unsigned int virq,
+				   unsigned int nr_irqs)
 {
 	/* Not freeing IPIs */
 }

@@ -483,7 +481,8 @@ static __init void armada_xp_ipi_init(struct device_node *node)
 		return;
 
 	irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
-	base_ipi = irq_domain_alloc_irqs(ipi_domain, IPI_DOORBELL_END, NUMA_NO_NODE, NULL);
+	base_ipi = irq_domain_alloc_irqs(ipi_domain, IPI_DOORBELL_END,
+					 NUMA_NO_NODE, NULL);
 	if (WARN_ON(!base_ipi))
 		return;
 

@@ -561,6 +560,7 @@ static int armada_xp_mpic_starting_cpu(unsigned int cpu)
 	armada_xp_mpic_perf_init();
 	armada_xp_mpic_smp_cpu_init();
 	armada_xp_mpic_reenable_percpu();
+
 	return 0;
 }
 

@@ -569,6 +569,7 @@ static int mpic_cascaded_starting_cpu(unsigned int cpu)
 	armada_xp_mpic_perf_init();
 	armada_xp_mpic_reenable_percpu();
 	enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
+
 	return 0;
 }
 #else

@@ -578,9 +579,9 @@ static void ipi_resume(void) {}
 
 static struct irq_chip armada_370_xp_irq_chip = {
 	.name		= "MPIC",
-	.irq_mask       = armada_370_xp_irq_mask,
-	.irq_mask_ack   = armada_370_xp_irq_mask,
-	.irq_unmask     = armada_370_xp_irq_unmask,
+	.irq_mask	= armada_370_xp_irq_mask,
+	.irq_mask_ack	= armada_370_xp_irq_mask,
+	.irq_unmask	= armada_370_xp_irq_unmask,
 #ifdef CONFIG_SMP
 	.irq_set_affinity = armada_xp_set_affinity,
 #endif

@@ -604,10 +605,10 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 	if (is_percpu_irq(hw)) {
 		irq_set_percpu_devid(virq);
 		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
-					handle_percpu_devid_irq);
+					 handle_percpu_devid_irq);
 	} else {
 		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
-					handle_level_irq);
+					 handle_level_irq);
 		irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
 	}
 	irq_set_probe(virq);

@@ -616,8 +617,8 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 }
 
 static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
-	.map = armada_370_xp_mpic_irq_map,
-	.xlate = irq_domain_xlate_onecell,
+	.map	= armada_370_xp_mpic_irq_map,
+	.xlate	= irq_domain_xlate_onecell,
 };
 
 #ifdef CONFIG_PCI_MSI

@@ -705,20 +706,20 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 			int ipi;
 
 			ipimask = readl_relaxed(per_cpu_int_base +
-						MPIC_IN_DRBEL_CAUSE)
-				& IPI_DOORBELL_MASK;
+						MPIC_IN_DRBEL_CAUSE) &
+				  IPI_DOORBELL_MASK;
 
 			for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END)
 				generic_handle_domain_irq(ipi_domain, ipi);
 		}
 #endif
-
 	} while (1);
 }
 
 static int armada_370_xp_mpic_suspend(void)
 {
 	doorbell_mask_reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
+
 	return 0;
 }
 

@@ -814,9 +815,9 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 	for (int i = 0; i < nr_irqs; i++)
 		writel(i, main_int_base + MPIC_INT_CLEAR_ENABLE);
 
-	armada_370_xp_mpic_domain =
-		irq_domain_add_linear(node, nr_irqs,
-				&armada_370_xp_mpic_irq_ops, NULL);
+	armada_370_xp_mpic_domain = irq_domain_add_linear(node, nr_irqs,
+							  &armada_370_xp_mpic_irq_ops,
+							  NULL);
 	BUG_ON(!armada_370_xp_mpic_domain);
 	irq_domain_update_bus_token(armada_370_xp_mpic_domain, DOMAIN_BUS_WIRED);
 

index 5db1c6da938d..7da5167510e9 100644
@@ -150,18 +150,18 @@
 
 static void __iomem *per_cpu_int_base;
 static void __iomem *main_int_base;
-static struct irq_domain *armada_370_xp_mpic_domain;
+static struct irq_domain *mpic_domain;
 static u32 doorbell_mask_reg;
 static int parent_irq;
 #ifdef CONFIG_PCI_MSI
-static struct irq_domain *armada_370_xp_msi_domain;
-static struct irq_domain *armada_370_xp_msi_inner_domain;
+static struct irq_domain *mpic_msi_domain;
+static struct irq_domain *mpic_msi_inner_domain;
 static DECLARE_BITMAP(msi_used, PCI_MSI_FULL_DOORBELL_NR);
 static DEFINE_MUTEX(msi_used_lock);
 static phys_addr_t msi_doorbell_addr;
 #endif
 
-static inline bool is_ipi_available(void)
+static inline bool mpic_is_ipi_available(void)
 {
 	/*
 	 * We distinguish IPI availability in the IC by the IC not having a

@@ -174,29 +174,29 @@ static inline bool is_ipi_available(void)
 
 static inline u32 msi_doorbell_mask(void)
 {
-	return is_ipi_available() ? PCI_MSI_DOORBELL_MASK :
-				    PCI_MSI_FULL_DOORBELL_MASK;
+	return mpic_is_ipi_available() ? PCI_MSI_DOORBELL_MASK :
+					 PCI_MSI_FULL_DOORBELL_MASK;
 }
 
 static inline unsigned int msi_doorbell_start(void)
 {
-	return is_ipi_available() ? PCI_MSI_DOORBELL_START :
-				    PCI_MSI_FULL_DOORBELL_START;
+	return mpic_is_ipi_available() ? PCI_MSI_DOORBELL_START :
+					 PCI_MSI_FULL_DOORBELL_START;
 }
 
 static inline unsigned int msi_doorbell_size(void)
 {
-	return is_ipi_available() ? PCI_MSI_DOORBELL_NR :
-				    PCI_MSI_FULL_DOORBELL_NR;
+	return mpic_is_ipi_available() ? PCI_MSI_DOORBELL_NR :
+					 PCI_MSI_FULL_DOORBELL_NR;
 }
 
 static inline unsigned int msi_doorbell_end(void)
 {
-	return is_ipi_available() ? PCI_MSI_DOORBELL_END :
-				    PCI_MSI_FULL_DOORBELL_END;
+	return mpic_is_ipi_available() ? PCI_MSI_DOORBELL_END :
+					 PCI_MSI_FULL_DOORBELL_END;
 }
 
-static inline bool is_percpu_irq(irq_hw_number_t irq)
+static inline bool mpic_is_percpu_irq(irq_hw_number_t irq)
 {
 	return irq <= MPIC_MAX_PER_CPU_IRQS;
 }

@@ -206,21 +206,21 @@ static inline bool is_percpu_irq(irq_hw_number_t irq)
  * For shared global interrupts, mask/unmask global enable bit
  * For CPU interrupts, mask/unmask the calling CPU's bit
  */
-static void armada_370_xp_irq_mask(struct irq_data *d)
+static void mpic_irq_mask(struct irq_data *d)
 {
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
-	if (!is_percpu_irq(hwirq))
+	if (!mpic_is_percpu_irq(hwirq))
 		writel(hwirq, main_int_base + MPIC_INT_CLEAR_ENABLE);
 	else
 		writel(hwirq, per_cpu_int_base + MPIC_INT_SET_MASK);
 }
 
-static void armada_370_xp_irq_unmask(struct irq_data *d)
+static void mpic_irq_unmask(struct irq_data *d)
 {
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
-	if (!is_percpu_irq(hwirq))
+	if (!mpic_is_percpu_irq(hwirq))
 		writel(hwirq, main_int_base + MPIC_INT_SET_ENABLE);
 	else
 		writel(hwirq, per_cpu_int_base + MPIC_INT_CLEAR_MASK);

@@ -228,19 +228,19 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
 
 #ifdef CONFIG_PCI_MSI
 
-static struct irq_chip armada_370_xp_msi_irq_chip = {
+static struct irq_chip mpic_msi_irq_chip = {
 	.name		= "MPIC MSI",
 	.irq_mask	= pci_msi_mask_irq,
 	.irq_unmask	= pci_msi_unmask_irq,
 };
 
-static struct msi_domain_info armada_370_xp_msi_domain_info = {
+static struct msi_domain_info mpic_msi_domain_info = {
 	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
 		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
-	.chip	= &armada_370_xp_msi_irq_chip,
+	.chip	= &mpic_msi_irq_chip,
 };
 
-static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
+static void mpic_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 {
 	unsigned int cpu = cpumask_first(irq_data_get_effective_affinity_mask(data));
 

@@ -249,8 +249,8 @@ static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg
 	msg->data = BIT(cpu + 8) | (data->hwirq + msi_doorbell_start());
 }
 
-static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,
-					  const struct cpumask *mask, bool force)
+static int mpic_msi_set_affinity(struct irq_data *irq_data,
+				 const struct cpumask *mask, bool force)
 {
 	unsigned int cpu;
 

@@ -267,14 +267,14 @@ static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,
 	return IRQ_SET_MASK_OK;
 }
 
-static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
+static struct irq_chip mpic_msi_bottom_irq_chip = {
 	.name			= "MPIC MSI",
-	.irq_compose_msi_msg	= armada_370_xp_compose_msi_msg,
-	.irq_set_affinity	= armada_370_xp_msi_set_affinity,
+	.irq_compose_msi_msg	= mpic_compose_msi_msg,
+	.irq_set_affinity	= mpic_msi_set_affinity,
 };
 
-static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
-				   unsigned int nr_irqs, void *args)
+static int mpic_msi_alloc(struct irq_domain *domain, unsigned int virq,
+			  unsigned int nr_irqs, void *args)
 {
 	int hwirq;
 

@@ -288,7 +288,7 @@ static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
 
 	for (int i = 0; i < nr_irqs; i++) {
 		irq_domain_set_info(domain, virq + i, hwirq + i,
-				    &armada_370_xp_msi_bottom_irq_chip,
+				    &mpic_msi_bottom_irq_chip,
 				    domain->host_data, handle_simple_irq,
 				    NULL, NULL);
 	}

@@ -296,8 +296,8 @@ static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
 	return 0;
 }
 
-static void armada_370_xp_msi_free(struct irq_domain *domain,
-				   unsigned int virq, unsigned int nr_irqs)
+static void mpic_msi_free(struct irq_domain *domain, unsigned int virq,
+			  unsigned int nr_irqs)
 {
 	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
 

@@ -306,12 +306,12 @@ static void armada_370_xp_msi_free(struct irq_domain *domain,
 	mutex_unlock(&msi_used_lock);
 }
 
-static const struct irq_domain_ops armada_370_xp_msi_domain_ops = {
-	.alloc	= armada_370_xp_msi_alloc,
-	.free	= armada_370_xp_msi_free,
+static const struct irq_domain_ops mpic_msi_domain_ops = {
+	.alloc	= mpic_msi_alloc,
+	.free	= mpic_msi_free,
 };
 
-static void armada_370_xp_msi_reenable_percpu(void)
+static void mpic_msi_reenable_percpu(void)
 {
 	u32 reg;
 

@@ -324,45 +324,44 @@ static void armada_370_xp_msi_reenable_percpu(void)
 	writel(1, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 }
 
-static int armada_370_xp_msi_init(struct device_node *node,
-				  phys_addr_t main_int_phys_base)
+static int mpic_msi_init(struct device_node *node,
+			 phys_addr_t main_int_phys_base)
 {
 	msi_doorbell_addr = main_int_phys_base + MPIC_SW_TRIG_INT;
 
-	armada_370_xp_msi_inner_domain =
-		irq_domain_add_linear(NULL, msi_doorbell_size(),
-				      &armada_370_xp_msi_domain_ops, NULL);
-	if (!armada_370_xp_msi_inner_domain)
+	mpic_msi_inner_domain = irq_domain_add_linear(NULL, msi_doorbell_size(),
+						      &mpic_msi_domain_ops,
+						      NULL);
+	if (!mpic_msi_inner_domain)
 		return -ENOMEM;
 
-	armada_370_xp_msi_domain =
-		pci_msi_create_irq_domain(of_node_to_fwnode(node),
-					  &armada_370_xp_msi_domain_info,
-					  armada_370_xp_msi_inner_domain);
-	if (!armada_370_xp_msi_domain) {
-		irq_domain_remove(armada_370_xp_msi_inner_domain);
+	mpic_msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
+						    &mpic_msi_domain_info,
+						    mpic_msi_inner_domain);
+	if (!mpic_msi_domain) {
+		irq_domain_remove(mpic_msi_inner_domain);
 		return -ENOMEM;
 	}
 
-	armada_370_xp_msi_reenable_percpu();
+	mpic_msi_reenable_percpu();
 
 	/* Unmask low 16 MSI irqs on non-IPI platforms */
-	if (!is_ipi_available())
+	if (!mpic_is_ipi_available())
 		writel(0, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 
 	return 0;
 }
 #else
-static __maybe_unused void armada_370_xp_msi_reenable_percpu(void) {}
+static __maybe_unused void mpic_msi_reenable_percpu(void) {}
 
-static inline int armada_370_xp_msi_init(struct device_node *node,
-					 phys_addr_t main_int_phys_base)
+static inline int mpic_msi_init(struct device_node *node,
+				phys_addr_t main_int_phys_base)
 {
 	return 0;
 }
 #endif
 
-static void armada_xp_mpic_perf_init(void)
+static void mpic_perf_init(void)
 {
 	unsigned long cpuid;
 

@@ -381,9 +380,9 @@ static void armada_xp_mpic_perf_init(void)
 }
 
 #ifdef CONFIG_SMP
-static struct irq_domain *ipi_domain;
+static struct irq_domain *mpic_ipi_domain;
 
-static void armada_370_xp_ipi_mask(struct irq_data *d)
+static void mpic_ipi_mask(struct irq_data *d)
 {
 	u32 reg;
 

@@ -392,7 +391,7 @@ static void armada_370_xp_ipi_mask(struct irq_data *d)
 	writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 }
 
-static void armada_370_xp_ipi_unmask(struct irq_data *d)
+static void mpic_ipi_unmask(struct irq_data *d)
 {
 	u32 reg;
 

@@ -401,8 +400,7 @@ static void armada_370_xp_ipi_unmask(struct irq_data *d)
 	writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 }
 
-static void armada_370_xp_ipi_send_mask(struct irq_data *d,
-					const struct cpumask *mask)
+static void mpic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
 {
 	unsigned long map = 0;
 	unsigned int cpu;

@@ -421,67 +419,67 @@ static void armada_370_xp_ipi_send_mask(struct irq_data *d,
 	writel((map << 8) | d->hwirq, main_int_base + MPIC_SW_TRIG_INT);
 }
 
-static void armada_370_xp_ipi_ack(struct irq_data *d)
+static void mpic_ipi_ack(struct irq_data *d)
 {
 	writel(~BIT(d->hwirq), per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
 }
 
-static struct irq_chip ipi_irqchip = {
+static struct irq_chip mpic_ipi_irqchip = {
 	.name		= "IPI",
-	.irq_ack	= armada_370_xp_ipi_ack,
-	.irq_mask	= armada_370_xp_ipi_mask,
-	.irq_unmask	= armada_370_xp_ipi_unmask,
-	.ipi_send_mask	= armada_370_xp_ipi_send_mask,
+	.irq_ack	= mpic_ipi_ack,
+	.irq_mask	= mpic_ipi_mask,
+	.irq_unmask	= mpic_ipi_unmask,
+	.ipi_send_mask	= mpic_ipi_send_mask,
 };
 
-static int armada_370_xp_ipi_alloc(struct irq_domain *d, unsigned int virq,
-				   unsigned int nr_irqs, void *args)
+static int mpic_ipi_alloc(struct irq_domain *d, unsigned int virq,
+			  unsigned int nr_irqs, void *args)
 {
 	for (int i = 0; i < nr_irqs; i++) {
 		irq_set_percpu_devid(virq + i);
-		irq_domain_set_info(d, virq + i, i, &ipi_irqchip, d->host_data,
-				    handle_percpu_devid_irq, NULL, NULL);
+		irq_domain_set_info(d, virq + i, i, &mpic_ipi_irqchip,
+				    d->host_data, handle_percpu_devid_irq,
+				    NULL, NULL);
 	}
 
 	return 0;
 }
 
-static void armada_370_xp_ipi_free(struct irq_domain *d, unsigned int virq,
-				   unsigned int nr_irqs)
+static void mpic_ipi_free(struct irq_domain *d, unsigned int virq,
+			  unsigned int nr_irqs)
 {
 	/* Not freeing IPIs */
 }
 
-static const struct irq_domain_ops ipi_domain_ops = {
-	.alloc	= armada_370_xp_ipi_alloc,
-	.free	= armada_370_xp_ipi_free,
+static const struct irq_domain_ops mpic_ipi_domain_ops = {
+	.alloc	= mpic_ipi_alloc,
+	.free	= mpic_ipi_free,
 };
 
-static void ipi_resume(void)
+static void mpic_ipi_resume(void)
 {
 	for (int i = 0; i < IPI_DOORBELL_END; i++) {
-		unsigned int virq = irq_find_mapping(ipi_domain, i);
+		unsigned int virq = irq_find_mapping(mpic_ipi_domain, i);
 
 		if (!virq || !irq_percpu_is_enabled(virq))
 			continue;
 
-		armada_370_xp_ipi_unmask(irq_domain_get_irq_data(ipi_domain,
-								 virq));
+		mpic_ipi_unmask(irq_domain_get_irq_data(mpic_ipi_domain, virq));
 	}
 }
 
-static __init void armada_xp_ipi_init(struct device_node *node)
+static __init void mpic_ipi_init(struct device_node *node)
 {
 	int base_ipi;
 
-	ipi_domain = irq_domain_create_linear(of_node_to_fwnode(node),
-					      IPI_DOORBELL_END,
-					      &ipi_domain_ops, NULL);
-	if (WARN_ON(!ipi_domain))
+	mpic_ipi_domain = irq_domain_create_linear(of_node_to_fwnode(node),
+						   IPI_DOORBELL_END,
+						   &mpic_ipi_domain_ops, NULL);
+	if (WARN_ON(!mpic_ipi_domain))
 		return;
 
-	irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
-	base_ipi = irq_domain_alloc_irqs(ipi_domain, IPI_DOORBELL_END,
+	irq_domain_update_bus_token(mpic_ipi_domain, DOMAIN_BUS_IPI);
+	base_ipi = irq_domain_alloc_irqs(mpic_ipi_domain, IPI_DOORBELL_END,
 					 NUMA_NO_NODE, NULL);
 	if (WARN_ON(!base_ipi))
 		return;

@@ -489,8 +487,8 @@ static __init void armada_xp_ipi_init(struct device_node *node)
 	set_smp_ipi_range(base_ipi, IPI_DOORBELL_END);
 }
 
-static int armada_xp_set_affinity(struct irq_data *d,
-				  const struct cpumask *mask_val, bool force)
+static int mpic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
+			     bool force)
 {
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 	unsigned int cpu;

@@ -506,7 +504,7 @@ static int armada_xp_set_affinity(struct irq_data *d,
 	return IRQ_SET_MASK_OK;
 }
 
-static void armada_xp_mpic_smp_cpu_init(void)
+static void mpic_smp_cpu_init(void)
 {
 	u32 control;
 	int nr_irqs;

@@ -517,7 +515,7 @@ static void armada_xp_mpic_smp_cpu_init(void)
 	for (int i = 0; i < nr_irqs; i++)
 		writel(i, per_cpu_int_base + MPIC_INT_SET_MASK);
 
-	if (!is_ipi_available())
+	if (!mpic_is_ipi_available())
 		return;
 
 	/* Disable all IPIs */

@@ -530,14 +528,14 @@ static void armada_xp_mpic_smp_cpu_init(void)
 	writel(0, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 }
 
-static void armada_xp_mpic_reenable_percpu(void)
+static void mpic_reenable_percpu(void)
 {
 	/* Re-enable per-CPU interrupts that were enabled before suspend */
 	for (unsigned int irq = 0; irq < MPIC_MAX_PER_CPU_IRQS; irq++) {
 		struct irq_data *data;
 		int virq;
 
-		virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
+		virq = irq_linear_revmap(mpic_domain, irq);
 		if (!virq)
 			continue;
 

@@ -546,69 +544,68 @@ static void armada_xp_mpic_reenable_percpu(void)
 		if (!irq_percpu_is_enabled(virq))
 			continue;
 
-		armada_370_xp_irq_unmask(data);
+		mpic_irq_unmask(data);
 	}
 
-	if (is_ipi_available())
-		ipi_resume();
+	if (mpic_is_ipi_available())
+		mpic_ipi_resume();
 
-	armada_370_xp_msi_reenable_percpu();
+	mpic_msi_reenable_percpu();
 }
 
-static int armada_xp_mpic_starting_cpu(unsigned int cpu)
+static int mpic_starting_cpu(unsigned int cpu)
 {
-	armada_xp_mpic_perf_init();
-	armada_xp_mpic_smp_cpu_init();
-	armada_xp_mpic_reenable_percpu();
+	mpic_perf_init();
+	mpic_smp_cpu_init();
+	mpic_reenable_percpu();
 
 	return 0;
 }
 
 static int mpic_cascaded_starting_cpu(unsigned int cpu)
 {
-	armada_xp_mpic_perf_init();
-	armada_xp_mpic_reenable_percpu();
+	mpic_perf_init();
+	mpic_reenable_percpu();
 	enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
 
 	return 0;
 }
 #else
-static void armada_xp_mpic_smp_cpu_init(void) {}
-static void ipi_resume(void) {}
+static void mpic_smp_cpu_init(void) {}
+static void mpic_ipi_resume(void) {}
 #endif
 
-static struct irq_chip armada_370_xp_irq_chip = {
+static struct irq_chip mpic_irq_chip = {
 	.name		= "MPIC",
-	.irq_mask	= armada_370_xp_irq_mask,
-	.irq_mask_ack	= armada_370_xp_irq_mask,
-	.irq_unmask	= armada_370_xp_irq_unmask,
+	.irq_mask	= mpic_irq_mask,
+	.irq_mask_ack	= mpic_irq_mask,
+	.irq_unmask	= mpic_irq_unmask,
 #ifdef CONFIG_SMP
-	.irq_set_affinity = armada_xp_set_affinity,
+	.irq_set_affinity = mpic_set_affinity,
 #endif
 	.flags		= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
 };
 
-static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
-				      unsigned int virq, irq_hw_number_t hw)
+static int mpic_irq_map(struct irq_domain *h, unsigned int virq,
+			irq_hw_number_t hw)
 {
 	/* IRQs 0 and 1 cannot be mapped, they are handled internally */
 	if (hw <= 1)
 		return -EINVAL;
 
-	armada_370_xp_irq_mask(irq_get_irq_data(virq));
-	if (!is_percpu_irq(hw))
+	mpic_irq_mask(irq_get_irq_data(virq));
+	if (!mpic_is_percpu_irq(hw))
 		writel(hw, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 	else
 		writel(hw, main_int_base + MPIC_INT_SET_ENABLE);
 	irq_set_status_flags(virq, IRQ_LEVEL);
 
-	if (is_percpu_irq(hw)) {
+	if (mpic_is_percpu_irq(hw)) {
 		irq_set_percpu_devid(virq);
-		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
+		irq_set_chip_and_handler(virq, &mpic_irq_chip,
 					 handle_percpu_devid_irq);
 	} else {
-		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
-					 handle_level_irq);
+		irq_set_chip_and_handler(virq, &mpic_irq_chip, handle_level_irq);
 		irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
 	}
 	irq_set_probe(virq);

@@ -616,13 +613,13 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 	return 0;
 }
 
-static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
-	.map	= armada_370_xp_mpic_irq_map,
+static const struct irq_domain_ops mpic_irq_ops = {
+	.map	= mpic_irq_map,
 	.xlate	= irq_domain_xlate_onecell,
 };
 
 #ifdef CONFIG_PCI_MSI
-static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
+static void mpic_handle_msi_irq(struct pt_regs *regs, bool is_chained)
 {
 	u32 msimask, msinr;
 

@@ -640,14 +637,14 @@ static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
 
 		irq = msinr - msi_doorbell_start();
 
-		generic_handle_domain_irq(armada_370_xp_msi_inner_domain, irq);
+		generic_handle_domain_irq(mpic_msi_inner_domain, irq);
 	}
 }
 #else
-static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
+static void mpic_handle_msi_irq(struct pt_regs *r, bool b) {}
 #endif
 
-static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
+static void mpic_handle_cascade_irq(struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	unsigned long irqmap, irqn, irqsrc, cpuid;

@@ -667,18 +664,17 @@ static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
 			continue;
 
 		if (irqn == 0 || irqn == 1) {
-			armada_370_xp_handle_msi_irq(NULL, true);
+			mpic_handle_msi_irq(NULL, true);
 			continue;
 		}
 
-		generic_handle_domain_irq(armada_370_xp_mpic_domain, irqn);
+		generic_handle_domain_irq(mpic_domain, irqn);
 	}
 
 	chained_irq_exit(chip, desc);
 }
 
-static void __exception_irq_entry
-armada_370_xp_handle_irq(struct pt_regs *regs)
+static void __exception_irq_entry mpic_handle_irq(struct pt_regs *regs)
 {
 	u32 irqstat, irqnr;
 

@@ -690,14 +686,13 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 			break;
 
 		if (irqnr > 1) {
-			generic_handle_domain_irq(armada_370_xp_mpic_domain,
-						  irqnr);
+			generic_handle_domain_irq(mpic_domain, irqnr);
 			continue;
 		}
 
 		/* MSI handling */
 		if (irqnr == 1)
-			armada_370_xp_handle_msi_irq(regs, false);
+			mpic_handle_msi_irq(regs, false);
 
 #ifdef CONFIG_SMP
 		/* IPI Handling */

@@ -710,20 +705,20 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 				  IPI_DOORBELL_MASK;
 
 			for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END)
-				generic_handle_domain_irq(ipi_domain, ipi);
+				generic_handle_domain_irq(mpic_ipi_domain, ipi);
 		}
 #endif
 	} while (1);
 }
 
-static int armada_370_xp_mpic_suspend(void)
+static int mpic_suspend(void)
 {
 	doorbell_mask_reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 
 	return 0;
 }
 
-static void armada_370_xp_mpic_resume(void)
+static void mpic_resume(void)
 {
 	bool src0, src1;
 	int nirqs;

@@ -734,35 +729,34 @@ static void armada_370_xp_mpic_resume(void)
 		struct irq_data *data;
 		int virq;
 
-		virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
+		virq = irq_linear_revmap(mpic_domain, irq);
 		if (!virq)
 			continue;
 
 		data = irq_get_irq_data(virq);
 
-		if (!is_percpu_irq(irq)) {
+		if (!mpic_is_percpu_irq(irq)) {
 			/* Non per-CPU interrupts */
 			writel(irq, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 			if (!irqd_irq_disabled(data))
-				armada_370_xp_irq_unmask(data);
+				mpic_irq_unmask(data);
 		} else {
 			/* Per-CPU interrupts */
 			writel(irq, main_int_base + MPIC_INT_SET_ENABLE);
 
 			/*
-			 * Re-enable on the current CPU,
-			 * armada_xp_mpic_reenable_percpu() will take
-			 * care of secondary CPUs when they come up.
+			 * Re-enable on the current CPU, mpic_reenable_percpu()
+			 * will take care of secondary CPUs when they come up.
 			 */
 			if (irq_percpu_is_enabled(virq))
-				armada_370_xp_irq_unmask(data);
+				mpic_irq_unmask(data);
 		}
 	}
 
 	/* Reconfigure doorbells for IPIs and MSIs */
 	writel(doorbell_mask_reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 
-	if (is_ipi_available()) {
+	if (mpic_is_ipi_available()) {
 		src0 = doorbell_mask_reg & IPI_DOORBELL_MASK;
 		src1 = doorbell_mask_reg & PCI_MSI_DOORBELL_MASK;
 	} else {

@@ -775,17 +769,17 @@ static void armada_370_xp_mpic_resume(void)
 	if (src1)
 		writel(1, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 
-	if (is_ipi_available())
-		ipi_resume();
+	if (mpic_is_ipi_available())
+		mpic_ipi_resume();
 }
 
-static struct syscore_ops armada_370_xp_mpic_syscore_ops = {
-	.suspend	= armada_370_xp_mpic_suspend,
-	.resume		= armada_370_xp_mpic_resume,
+static struct syscore_ops mpic_syscore_ops = {
+	.suspend	= mpic_suspend,
+	.resume		= mpic_resume,
 };
 
-static int __init armada_370_xp_mpic_of_init(struct device_node *node,
-					     struct device_node *parent)
+static int __init mpic_of_init(struct device_node *node,
+			       struct device_node *parent)
 {
 	struct resource main_int_res, per_cpu_int_res;
 	int nr_irqs;

@@ -815,11 +809,9 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 	for (int i = 0; i < nr_irqs; i++)
 		writel(i, main_int_base + MPIC_INT_CLEAR_ENABLE);
 
-	armada_370_xp_mpic_domain = irq_domain_add_linear(node, nr_irqs,
-							  &armada_370_xp_mpic_irq_ops,
-							  NULL);
-	BUG_ON(!armada_370_xp_mpic_domain);
-	irq_domain_update_bus_token(armada_370_xp_mpic_domain, DOMAIN_BUS_WIRED);
+	mpic_domain = irq_domain_add_linear(node, nr_irqs, &mpic_irq_ops, NULL);
+	BUG_ON(!mpic_domain);
+	irq_domain_update_bus_token(mpic_domain, DOMAIN_BUS_WIRED);
 
 	/*
 	 * Initialize parent_irq before calling any other functions, since it is

@@ -828,19 +820,19 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 	parent_irq = irq_of_parse_and_map(node, 0);
 
 	/* Setup for the boot CPU */
-	armada_xp_mpic_perf_init();
-	armada_xp_mpic_smp_cpu_init();
+	mpic_perf_init();
+	mpic_smp_cpu_init();
 
-	armada_370_xp_msi_init(node, main_int_res.start);
+	mpic_msi_init(node, main_int_res.start);
 
 	if (parent_irq <= 0) {
-		irq_set_default_host(armada_370_xp_mpic_domain);
-		set_handle_irq(armada_370_xp_handle_irq);
+		irq_set_default_host(mpic_domain);
+		set_handle_irq(mpic_handle_irq);
 #ifdef CONFIG_SMP
-		armada_xp_ipi_init(node);
+		mpic_ipi_init(node);
 		cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
 					  "irqchip/armada/ipi:starting",
-					  armada_xp_mpic_starting_cpu, NULL);
+					  mpic_starting_cpu, NULL);
 #endif
 	} else {
 #ifdef CONFIG_SMP

@@ -848,13 +840,12 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 					  "irqchip/armada/cascade:starting",
 					  mpic_cascaded_starting_cpu, NULL);
 #endif
-		irq_set_chained_handler(parent_irq,
-					armada_370_xp_mpic_handle_cascade_irq);
+		irq_set_chained_handler(parent_irq, mpic_handle_cascade_irq);
 	}
 
-	register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
+	register_syscore_ops(&mpic_syscore_ops);
 
 	return 0;
 }
 
-IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
+IRQCHIP_DECLARE(marvell_mpic, "marvell,mpic", mpic_of_init);

index 7da5167510e9..c287579da436 100644
@@ -506,13 +506,7 @@ static int mpic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 
 static void mpic_smp_cpu_init(void)
 {
-	u32 control;
-	int nr_irqs;
-
-	control = readl(main_int_base + MPIC_INT_CONTROL);
-	nr_irqs = (control >> 2) & 0x3ff;
-
-	for (int i = 0; i < nr_irqs; i++)
+	for (int i = 0; i < mpic_domain->hwirq_max; i++)
 		writel(i, per_cpu_int_base + MPIC_INT_SET_MASK);
 
 	if (!mpic_is_ipi_available())

@@ -721,11 +715,9 @@ static int mpic_suspend(void)
 static void mpic_resume(void)
 {
 	bool src0, src1;
-	int nirqs;
 
 	/* Re-enable interrupts */
-	nirqs = (readl(main_int_base + MPIC_INT_CONTROL) >> 2) & 0x3ff;
-	for (irq_hw_number_t irq = 0; irq < nirqs; irq++) {
+	for (irq_hw_number_t irq = 0; irq < mpic_domain->hwirq_max; irq++) {
 		struct irq_data *data;
 		int virq;
 

index c287579da436..d8db46001961 100644
@@ -10,6 +10,7 @@
  * Ben Dooks <[email protected]>
  */
 
+#include <linux/bitfield.h>
 #include <linux/bits.h>
 #include <linux/kernel.h>
 #include <linux/module.h>

@@ -112,6 +113,7 @@
 
 /* Registers relative to main_int_base */
 #define MPIC_INT_CONTROL			0x00
+#define MPIC_INT_CONTROL_NUMINT_MASK		GENMASK(12, 2)
 #define MPIC_SW_TRIG_INT			0x04
 #define MPIC_INT_SET_ENABLE			0x30
 #define MPIC_INT_CLEAR_ENABLE			0x34

@@ -124,6 +126,7 @@
 #define MPIC_IN_DRBEL_MASK			0x0c
 #define MPIC_PPI_CAUSE				0x10
 #define MPIC_CPU_INTACK				0x44
+#define MPIC_CPU_INTACK_IID_MASK		GENMASK(9, 0)
 #define MPIC_INT_SET_MASK			0x48
 #define MPIC_INT_CLEAR_MASK			0x4C
 #define MPIC_INT_FABRIC_MASK			0x54

@@ -674,7 +677,7 @@ static void __exception_irq_entry mpic_handle_irq(struct pt_regs *regs)
 
 	do {
 		irqstat = readl_relaxed(per_cpu_int_base + MPIC_CPU_INTACK);
-		irqnr = irqstat & 0x3FF;
+		irqnr = FIELD_GET(MPIC_CPU_INTACK_IID_MASK, irqstat);
 
 		if (irqnr > 1022)
 			break;

@@ -774,8 +777,7 @@ static int __init mpic_of_init(struct device_node *node,
 			       struct device_node *parent)
 {
 	struct resource main_int_res, per_cpu_int_res;
-	int nr_irqs;
-	u32 control;
+	unsigned int nr_irqs;
 
 	BUG_ON(of_address_to_resource(node, 0, &main_int_res));
 	BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));

@@ -795,8 +797,8 @@ static int __init mpic_of_init(struct device_node *node,
 				   resource_size(&per_cpu_int_res));
 	BUG_ON(!per_cpu_int_base);
 
-	control = readl(main_int_base + MPIC_INT_CONTROL);
-	nr_irqs = (control >> 2) & 0x3ff;
+	nr_irqs = FIELD_GET(MPIC_INT_CONTROL_NUMINT_MASK,
+			    readl(main_int_base + MPIC_INT_CONTROL));
 
 	for (int i = 0; i < nr_irqs; i++)
 		writel(i, main_int_base + MPIC_INT_CLEAR_ENABLE);

index d8db46001961..9e8b189da1d1 100644
@@ -618,24 +618,15 @@ static const struct irq_domain_ops mpic_irq_ops = {
 #ifdef CONFIG_PCI_MSI
 static void mpic_handle_msi_irq(struct pt_regs *regs, bool is_chained)
 {
-	u32 msimask, msinr;
+	unsigned long cause, nr;
 
-	msimask = readl_relaxed(per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
-	msimask &= msi_doorbell_mask();
+	cause = readl_relaxed(per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
+	cause &= msi_doorbell_mask();
+	writel(~cause, per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
 
-	writel(~msimask, per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
-
-	for (msinr = msi_doorbell_start();
-	     msinr < msi_doorbell_end(); msinr++) {
-		unsigned int irq;
-
-		if (!(msimask & BIT(msinr)))
-			continue;
-
-		irq = msinr - msi_doorbell_start();
-
-		generic_handle_domain_irq(mpic_msi_inner_domain, irq);
-	}
+	for_each_set_bit(nr, &cause, BITS_PER_LONG)
+		generic_handle_domain_irq(mpic_msi_inner_domain,
+					  nr - msi_doorbell_start());
 }
 #else
 static void mpic_handle_msi_irq(struct pt_regs *r, bool b) {}

index 9e8b189da1d1..d21216515fc2 100644
@@ -528,20 +528,13 @@ static void mpic_smp_cpu_init(void)
 static void mpic_reenable_percpu(void)
 {
 	/* Re-enable per-CPU interrupts that were enabled before suspend */
-	for (unsigned int irq = 0; irq < MPIC_MAX_PER_CPU_IRQS; irq++) {
-		struct irq_data *data;
-		int virq;
+	for (irq_hw_number_t i = 0; i < MPIC_MAX_PER_CPU_IRQS; i++) {
+		unsigned int virq = irq_linear_revmap(mpic_domain, i);
 
-		virq = irq_linear_revmap(mpic_domain, irq);
-		if (!virq)
-			continue;
-
-		data = irq_get_irq_data(virq);
-
-		if (!irq_percpu_is_enabled(virq))
+		if (!virq || !irq_percpu_is_enabled(virq))
 			continue;
 
-		mpic_irq_unmask(data);
+		mpic_irq_unmask(irq_get_irq_data(virq));
 	}
 
 	if (mpic_is_ipi_available())

index d21216515fc2..f773d88ead73 100644
@@ -289,7 +289,7 @@ static int mpic_msi_alloc(struct irq_domain *domain, unsigned int virq,
 	if (hwirq < 0)
 		return -ENOSPC;
 
-	for (int i = 0; i < nr_irqs; i++) {
+	for (unsigned int i = 0; i < nr_irqs; i++) {
 		irq_domain_set_info(domain, virq + i, hwirq + i,
 				    &mpic_msi_bottom_irq_chip,
 				    domain->host_data, handle_simple_irq,

@@ -438,7 +438,7 @@ static struct irq_chip mpic_ipi_irqchip = {
 static int mpic_ipi_alloc(struct irq_domain *d, unsigned int virq,
 			  unsigned int nr_irqs, void *args)
 {
-	for (int i = 0; i < nr_irqs; i++) {
+	for (unsigned int i = 0; i < nr_irqs; i++) {
 		irq_set_percpu_devid(virq + i);
 		irq_domain_set_info(d, virq + i, i, &mpic_ipi_irqchip,
 				    d->host_data, handle_percpu_devid_irq,

@@ -461,7 +461,7 @@ static const struct irq_domain_ops mpic_ipi_domain_ops = {
 
 static void mpic_ipi_resume(void)
 {
-	for (int i = 0; i < IPI_DOORBELL_END; i++) {
+	for (irq_hw_number_t i = 0; i < IPI_DOORBELL_END; i++) {
 		unsigned int virq = irq_find_mapping(mpic_ipi_domain, i);
 
 		if (!virq || !irq_percpu_is_enabled(virq))

@@ -509,7 +509,7 @@ static int mpic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 
 static void mpic_smp_cpu_init(void)
 {
-	for (int i = 0; i < mpic_domain->hwirq_max; i++)
+	for (irq_hw_number_t i = 0; i < mpic_domain->hwirq_max; i++)
 		writel(i, per_cpu_int_base + MPIC_INT_SET_MASK);
 
 	if (!mpic_is_ipi_available())

@@ -628,7 +628,8 @@ static void mpic_handle_msi_irq(struct pt_regs *r, bool b) {}
 static void mpic_handle_cascade_irq(struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);
-	unsigned long irqmap, irqn, irqsrc, cpuid;
+	unsigned long irqmap, irqsrc, cpuid;
+	irq_hw_number_t irqn;
 
 	chained_irq_enter(chip, desc);
 

@@ -657,7 +658,8 @@ static void mpic_handle_cascade_irq(struct irq_desc *desc)
 
 static void __exception_irq_entry mpic_handle_irq(struct pt_regs *regs)
 {
-	u32 irqstat, irqnr;
+	irq_hw_number_t irqnr;
+	u32 irqstat;
 
 	do {
 		irqstat = readl_relaxed(per_cpu_int_base + MPIC_CPU_INTACK);

@@ -679,7 +681,7 @@ static void __exception_irq_entry mpic_handle_irq(struct pt_regs *regs)
 		/* IPI Handling */
 		if (irqnr == 0) {
 			unsigned long ipimask;
-			int ipi;
+			irq_hw_number_t ipi;
 
 			ipimask = readl_relaxed(per_cpu_int_base +
 						MPIC_IN_DRBEL_CAUSE) &

@@ -784,7 +786,7 @@ static int __init mpic_of_init(struct device_node *node,
 	nr_irqs = FIELD_GET(MPIC_INT_CONTROL_NUMINT_MASK,
 			    readl(main_int_base + MPIC_INT_CONTROL));
 
-	for (int i = 0; i < nr_irqs; i++)
+	for (irq_hw_number_t i = 0; i < nr_irqs; i++)
 		writel(i, main_int_base + MPIC_INT_CLEAR_ENABLE);
 
 	mpic_domain = irq_domain_add_linear(node, nr_irqs, &mpic_irq_ops, NULL);

index f773d88ead73..b08f49516bee 100644
@@ -117,7 +117,7 @@
 #define MPIC_SW_TRIG_INT			0x04
 #define MPIC_INT_SET_ENABLE			0x30
 #define MPIC_INT_CLEAR_ENABLE			0x34
-#define MPIC_INT_SOURCE_CTL(irq)		(0x100 + (irq) * 4)
+#define MPIC_INT_SOURCE_CTL(hwirq)		(0x100 + (hwirq) * 4)
 #define MPIC_INT_SOURCE_CPU_MASK		GENMASK(3, 0)
 #define MPIC_INT_IRQ_FIQ_MASK(cpuid)		((BIT(0) | BIT(8)) << (cpuid))
 

@@ -199,9 +199,9 @@ static inline unsigned int msi_doorbell_end(void)
 					 PCI_MSI_FULL_DOORBELL_END;
 }
 
-static inline bool mpic_is_percpu_irq(irq_hw_number_t irq)
+static inline bool mpic_is_percpu_irq(irq_hw_number_t hwirq)
 {
-	return irq <= MPIC_MAX_PER_CPU_IRQS;
+	return hwirq <= MPIC_MAX_PER_CPU_IRQS;
 }
 
 /*

@@ -577,20 +577,20 @@ static struct irq_chip mpic_irq_chip = {
 };
 
 static int mpic_irq_map(struct irq_domain *h, unsigned int virq,
-			irq_hw_number_t hw)
+			irq_hw_number_t hwirq)
 {
 	/* IRQs 0 and 1 cannot be mapped, they are handled internally */
-	if (hw <= 1)
+	if (hwirq <= 1)
 		return -EINVAL;
 
 	mpic_irq_mask(irq_get_irq_data(virq));
-	if (!mpic_is_percpu_irq(hw))
-		writel(hw, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
+	if (!mpic_is_percpu_irq(hwirq))
+		writel(hwirq, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 	else
-		writel(hw, main_int_base + MPIC_INT_SET_ENABLE);
+		writel(hwirq, main_int_base + MPIC_INT_SET_ENABLE);
 	irq_set_status_flags(virq, IRQ_LEVEL);
 
-	if (mpic_is_percpu_irq(hw)) {
+	if (mpic_is_percpu_irq(hwirq)) {
 		irq_set_percpu_devid(virq);
 		irq_set_chip_and_handler(virq, &mpic_irq_chip,
 					 handle_percpu_devid_irq);

@@ -629,15 +629,15 @@ static void mpic_handle_cascade_irq(struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	unsigned long irqmap, irqsrc, cpuid;
-	irq_hw_number_t irqn;
+	irq_hw_number_t hwirq;
 
 	chained_irq_enter(chip, desc);
 
 	irqmap = readl_relaxed(per_cpu_int_base + MPIC_PPI_CAUSE);
 	cpuid = cpu_logical_map(smp_processor_id());
 
-	for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
-		irqsrc = readl_relaxed(main_int_base + MPIC_INT_SOURCE_CTL(irqn));
+	for_each_set_bit(hwirq, &irqmap, BITS_PER_LONG) {
+		irqsrc = readl_relaxed(main_int_base + MPIC_INT_SOURCE_CTL(hwirq));
 
 		/* Check if the interrupt is not masked on current CPU.
 		 * Test IRQ (0-1) and FIQ (8-9) mask bits.

@@ -645,12 +645,12 @@ static void mpic_handle_cascade_irq(struct irq_desc *desc)
 		if (!(irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)))
 			continue;
 
-		if (irqn == 0 || irqn == 1) {
+		if (hwirq == 0 || hwirq == 1) {
 			mpic_handle_msi_irq(NULL, true);
 			continue;
 		}
 
-		generic_handle_domain_irq(mpic_domain, irqn);
+		generic_handle_domain_irq(mpic_domain, hwirq);
 	}
 
 	chained_irq_exit(chip, desc);

@@ -658,28 +658,28 @@ static void mpic_handle_cascade_irq(struct irq_desc *desc)
 
 static void __exception_irq_entry mpic_handle_irq(struct pt_regs *regs)
 {
-	irq_hw_number_t irqnr;
+	irq_hw_number_t hwirq;
 	u32 irqstat;
 
 	do {
 		irqstat = readl_relaxed(per_cpu_int_base + MPIC_CPU_INTACK);
-		irqnr = FIELD_GET(MPIC_CPU_INTACK_IID_MASK, irqstat);
+		hwirq = FIELD_GET(MPIC_CPU_INTACK_IID_MASK, irqstat);
 
-		if (irqnr > 1022)
+		if (hwirq > 1022)
 			break;
 
-		if (irqnr > 1) {
-			generic_handle_domain_irq(mpic_domain, irqnr);
+		if (hwirq > 1) {
+			generic_handle_domain_irq(mpic_domain, hwirq);
 			continue;
 		}
 
 		/* MSI handling */
-		if (irqnr == 1)
+		if (hwirq == 1)
 			mpic_handle_msi_irq(regs, false);
 
 #ifdef CONFIG_SMP
 		/* IPI Handling */
-		if (irqnr == 0) {
+		if (hwirq == 0) {
 			unsigned long ipimask;
 			irq_hw_number_t ipi;
 

@@ -706,24 +706,24 @@ static void mpic_resume(void)
 	bool src0, src1;
 
 	/* Re-enable interrupts */
-	for (irq_hw_number_t irq = 0; irq < mpic_domain->hwirq_max; irq++) {
+	for (irq_hw_number_t i = 0; i < mpic_domain->hwirq_max; i++) {
 		struct irq_data *data;
 		int virq;
 
-		virq = irq_linear_revmap(mpic_domain, irq);
+		virq = irq_linear_revmap(mpic_domain, i);
 		if (!virq)
 			continue;
 
 		data = irq_get_irq_data(virq);
 
-		if (!mpic_is_percpu_irq(irq)) {
+		if (!mpic_is_percpu_irq(i)) {
 			/* Non per-CPU interrupts */
-			writel(irq, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
+			writel(i, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 			if (!irqd_irq_disabled(data))
 				mpic_irq_unmask(data);
 		} else {
 			/* Per-CPU interrupts */
-			writel(irq, main_int_base + MPIC_INT_SET_ENABLE);
+			writel(i, main_int_base + MPIC_INT_SET_ENABLE);
 
 			/*
 			 * Re-enable on the current CPU, mpic_reenable_percpu()

index b08f49516bee..4b4c0dae72b0 100644
@@ -707,10 +707,9 @@ static void mpic_resume(void)
 
 	/* Re-enable interrupts */
 	for (irq_hw_number_t i = 0; i < mpic_domain->hwirq_max; i++) {
+		unsigned int virq = irq_linear_revmap(mpic_domain, i);
 		struct irq_data *data;
-		int virq;
 
-		virq = irq_linear_revmap(mpic_domain, i);
 		if (!virq)
 			continue;
 

index 4b4c0dae72b0..5ce55cc15572 100644
@@ -625,6 +625,22 @@ static void mpic_handle_msi_irq(struct pt_regs *regs, bool is_chained)
 static void mpic_handle_msi_irq(struct pt_regs *r, bool b) {}
 #endif
 
+#ifdef CONFIG_SMP
+static void mpic_handle_ipi_irq(void)
+{
+	irq_hw_number_t hwirq;
+	unsigned long cause;
+
+	cause = readl_relaxed(per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
+	cause &= IPI_DOORBELL_MASK;
+
+	for_each_set_bit(hwirq, &cause, IPI_DOORBELL_END)
+		generic_handle_domain_irq(mpic_ipi_domain, hwirq);
+}
+#else
+static inline void mpic_handle_ipi_irq(void) {}
+#endif
+
 static void mpic_handle_cascade_irq(struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);

@@ -677,20 +693,9 @@ static void __exception_irq_entry mpic_handle_irq(struct pt_regs *regs)
 		if (hwirq == 1)
 			mpic_handle_msi_irq(regs, false);
 
-#ifdef CONFIG_SMP
 		/* IPI Handling */
-		if (hwirq == 0) {
-			unsigned long ipimask;
-			irq_hw_number_t ipi;
-
-			ipimask = readl_relaxed(per_cpu_int_base +
-						MPIC_IN_DRBEL_CAUSE) &
-				  IPI_DOORBELL_MASK;
-
-			for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END)
-				generic_handle_domain_irq(mpic_ipi_domain, ipi);
-		}
-#endif
+		if (hwirq == 0)
+			mpic_handle_ipi_irq();
 	} while (1);
 }
 

index 5ce55cc15572..8de2f43792f8 100644
@@ -609,7 +609,7 @@ static const struct irq_domain_ops mpic_irq_ops = {
 };
 
 #ifdef CONFIG_PCI_MSI
-static void mpic_handle_msi_irq(struct pt_regs *regs, bool is_chained)
+static void mpic_handle_msi_irq(void)
 {
 	unsigned long cause, nr;
 

@@ -622,7 +622,7 @@ static void mpic_handle_msi_irq(struct pt_regs *regs, bool is_chained)
 					  nr - msi_doorbell_start());
 }
 #else
-static void mpic_handle_msi_irq(struct pt_regs *r, bool b) {}
+static void mpic_handle_msi_irq(void) {}
 #endif
 
 #ifdef CONFIG_SMP

@@ -662,7 +662,7 @@ static void mpic_handle_cascade_irq(struct irq_desc *desc)
 			continue;
 
 		if (hwirq == 0 || hwirq == 1) {
-			mpic_handle_msi_irq(NULL, true);
+			mpic_handle_msi_irq();
 			continue;
 		}
 

@@ -691,7 +691,7 @@ static void __exception_irq_entry mpic_handle_irq(struct pt_regs *regs)
 
 		/* MSI handling */
 		if (hwirq == 1)
-			mpic_handle_msi_irq(regs, false);
+			mpic_handle_msi_irq();
 
 		/* IPI Handling */
 		if (hwirq == 0)

index 8de2f43792f8..f28c067ef4cb 100644
@@ -289,12 +289,11 @@ static int mpic_msi_alloc(struct irq_domain *domain, unsigned int virq,
 	if (hwirq < 0)
 		return -ENOSPC;
 
-	for (unsigned int i = 0; i < nr_irqs; i++) {
+	for (unsigned int i = 0; i < nr_irqs; i++)
 		irq_domain_set_info(domain, virq + i, hwirq + i,
 				    &mpic_msi_bottom_irq_chip,
 				    domain->host_data, handle_simple_irq,
 				    NULL, NULL);
-	}
 
 	return 0;
 }

index f28c067ef4cb..b4631e0a14af 100644
@@ -683,10 +683,8 @@ static void __exception_irq_entry mpic_handle_irq(struct pt_regs *regs)
 		if (hwirq > 1022)
 			break;
 
-		if (hwirq > 1) {
+		if (hwirq > 1)
 			generic_handle_domain_irq(mpic_domain, hwirq);
-			continue;
-		}
 
 		/* MSI handling */
 		if (hwirq == 1)