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Introduce Nuvoton Arbel NPCM8XX BMC SoC

PATCH RESEND Superseded Tomer Maimon 3 participants 10 messages Aug 15, 2024 – Sep 12, 2024

Subsystems (4)
Device tree bindings Common clk Reset controller framework Arm/nuvoton npcm architecture

v27 of 28 Superseded Latest is v28 →

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Tomer Maimon

author maintainer
#0 lore raw

v27 cover Introduce Nuvoton Arbel NPCM8XX BMC SoC

This patchset adds clock support for the Nuvoton Arbel NPCM8XX Board Management controller (BMC) SoC family.

The NPCM8xx clock controller is created using the auxiliary device framework and set up in the npcm reset driver since the NPCM8xx clock is using the same register region.

This patchset cover letter is based from the initial support for NPCM8xx BMC to keep tracking the version history.

This patchset was tested on the Arbel NPCM8XX evaluation board.

No changes since version 26, only tested in kernel 6.11.rc1

Changes since version 25:
- Add select AUXILIARY_BUS to npcm_reset kconfig.
- Include <linux/auxiliary_bus.h> and <linux/slab.h> in reset and clock driver.

Changes since version 24:
- Keep clock npcm8xx dt-binding to avoid ABI break.
- Fix kfree parameter.
- Correct reference.
- Modify commit message.

Changes since version 23:
- NPCM8xx clock controller using the auxiliary device framework.
- Add NPCM8xx clock controller aux device registration support in npcm reset driver.
- Remove unused nuvoton,npcm845 clk bindings.
- Remove all string #define

Changes since version 22:
- Modify commit message to explain broken ABI in dt-binding
- Using regmap parenet regmap memory therefore remove use of npcm8xx rst-clock patch.
- Leave npcm7xx rst node as is

Changes since version 21:
- Since using regmap instead of ioremap replace reg to syscon property in dt-bindings and dts.
- Add reference clock property to the dt-bindings and dts.
- Using .index instead of .name in clk_parent_data structures.
- Using string where any macros are used once.

Changes since version 20:
- Using regmap instead of ioremap.
the clock and reset modules are sharing the same memory region and cause failure when using devm_platform_ioremap_resource function, this version uses regmap to handle shared reset and clock memory region, in case it is approved I will modify the reset driver to use the regmap as well.
- Using clk_hw instead of clk_parent_data structre.
- Divider clock definition to one line

Changes since version 19:
- Remove unnecessary free command.
- Defining pr_fmt().
- Using dev_err_probe.
- Return zero in the end of the probe function.

Changes since version 18:
- NPCM8XX clock driver did not changed from version 18 only build and tested under kernel 6.6-rc1.

Changes since version 17:
- NPCM8XX clock driver did not changed from version 17 only build and tested under kernel 6.5-rc3.

Changes since version 16:
- NPCM8XX clock driver
- Using devm_kzalloc instead kzalloc.
- Remove unnecessary parenthesis.
- Modify incorrect spelling.

Changes since version 15:
- NPCM8XX clock driver
- Remove unused regs parameter from npcm8xx_pll_data structure.
- Using index and clk_hw parameters to set the clock parent in the clock structures.

Changes since version 14:
- NPCM8XX clock driver
- Remove unnecessary register definitions.
- Remove the internal reference clock, instead use the external DT reference clock.
- rearrange the driver.
- using .names parameter in DT to define clock (refclk).

Changes since version 13:
- NPCM8XX clock driver
- Remove unnecessary definitions and add module.h define
- Use in clk_parent_data struct.fw_name and .name.
- Add module_exit function.
- Add const to divider clock names.
- Add MODULE_DESCRIPTION and MODULE_LICENSE

Changes since version 12:
- NPCM8XX clock driver
- Use clk_parent_data in mux and div clock structure.
- Add const to mux tables.
- Using devm_clk_hw_register_fixed_rate function.
- use only .name clk_parent_data instead .name and .fw_name.
- Modify mask values in mux clocks.

Changes since version 11:
- NPCM8XX clock driver
- Modify Kconfig help.
- Modify loop variable to unsigned int.

Changes since version 11:
- NPCM8XX clock driver
- Modify Kconfig help.
- Modify loop variable to unsigned int.

Changes since version 10:
- NPCM8XX clock driver
- Fix const warning.

Changes since version 9:
- NPCM8XX clock driver
- Move configuration place.
- Using clk_parent_data instead of parent_name
- using devm_ioremap instead of ioremap. deeply sorry, I know we had a long discussion on what should the driver use, from other examples (also in other clock drivers) I see the combination of platform_get_resource and devm_ioremap are commonly used and it answer the reset and clock needs.

Changes since version 8:
- NPCM8XX clock driver
- Move configuration place.
- Add space before and aftre '{' '}'.
- Handle devm_of_clk_add_hw_provider function error.

Changes since version 7:
- NPCM8XX clock driver
- The clock and reset registers using the same memory region, due to it the clock driver should claim the ioremap directly without checking the memory region.

Changes since version 5:
- NPCM8XX clock driver
- Remove refclk if devm_of_clk_add_hw_provider function failed.

Changes since version 4:
- NPCM8XX clock driver
- Use the same quote in the dt-binding file.

Changes since version 3:
- NPCM8XX clock driver
- Rename NPCM8xx clock dt-binding header file.
- Remove unused structures.
- Improve Handling the clocks registration.

Changes since version 2:
- NPCM8XX clock driver
- Add debug new line.
- Add 25M fixed rate clock.
- Remove unused clocks and clock name from dt-binding.

Changes since version 1:
- NPCM8XX clock driver
- Modify dt-binding.
- Remove unsed definition and include.
- Include alphabetically.
- Use clock devm.

Tomer Maimon (3):
dt-bindings: reset: npcm: add clock properties
reset: npcm: register npcm8xx clock auxiliary bus device
clk: npcm8xx: add clock controller

 .../bindings/reset/nuvoton,npcm750-reset.yaml |  18 +
 drivers/clk/Kconfig                           |   8 +
 drivers/clk/Makefile                          |   1 +
 drivers/clk/clk-npcm8xx.c                     | 430 ++++++++++++++++++
 drivers/reset/Kconfig                         |   1 +
 drivers/reset/reset-npcm.c                    |  74 ++-
 include/soc/nuvoton/clock-npcm8xx.h           |  16 +
 7 files changed, 547 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/clk-npcm8xx.c
 create mode 100755 include/soc/nuvoton/clock-npcm8xx.h
Signature · 1 line
2.34.1
author maintainer
#1 lore raw

PATCH RESEND v27 1/3 dt-bindings: reset: npcm: add clock properties

This commit adds a 25MHz reference clock and clock-cell properties to the NPCM reset document. The addition is necessitated by the integration of the NPCM8xx clock auxiliary bus device into the NPCM reset driver.

The inclusion of the NPCM8xx clock properties in the reset document is crucial as the reset block also serves as a clock provider for the NPCM8xx clock. This enhancement is intended to facilitate the use of the NPCM8xx clock driver.

Signed-off-by Tomer Maimon <[email protected]>
Reviewed-by Rob Herring <[email protected]>
---
 .../bindings/reset/nuvoton,npcm750-reset.yaml  | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml +18 -0
index d82e65e37cc0..72523f1bbc18 100644
@@ -21,6 +21,13 @@ properties:
   '#reset-cells':
     const: 2
 
+  '#clock-cells':
+    const: 1
+
+  clocks:
+    items:
+      - description: specify external 25MHz reference clock.
+
   nuvoton,sysgcr:
     $ref: /schemas/types.yaml#/definitions/phandle
     description: a phandle to access GCR registers.

@@ -39,6 +46,17 @@ required:
   - '#reset-cells'
   - nuvoton,sysgcr
 
+if:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - nuvoton,npcm845-reset
+then:
+  required:
+    - '#clock-cells'
+    - clocks
+
 additionalProperties: false
 
 examples:
Signature · 1 line
2.34.1
author maintainer
#2 lore raw

PATCH RESEND v27 2/3 reset: npcm: register npcm8xx clock auxiliary bus device

In reply to Tomer Maimon

Add NPCM8xx clock controller auxiliary bus device registration.

The NPCM8xx clock controller is registered as an aux device because the reset and the clock controller share the same register region.

Signed-off-by Tomer Maimon <[email protected]>
Tested-by Benjamin Fair <[email protected]>
---
 drivers/reset/Kconfig               |  1 +
 drivers/reset/reset-npcm.c          | 74 ++++++++++++++++++++++++++++-
 include/soc/nuvoton/clock-npcm8xx.h | 16 +++++++
 3 files changed, 90 insertions(+), 1 deletion(-)
 create mode 100755 include/soc/nuvoton/clock-npcm8xx.h
drivers/reset/Kconfig +1 -0
index 67bce340a87e..c6bf5275cca2 100644
@@ -157,6 +157,7 @@ config RESET_MESON_AUDIO_ARB
 config RESET_NPCM
 	bool "NPCM BMC Reset Driver" if COMPILE_TEST
 	default ARCH_NPCM
+	select AUXILIARY_BUS
 	help
 	  This enables the reset controller driver for Nuvoton NPCM
 	  BMC SoCs.
drivers/reset/reset-npcm.c +73 -1

115 lines not on this page · raw message

include/soc/nuvoton/clock-npcm8xx.h new file +16 -0
new file mode 100755
index 000000000000..139130e98c51
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SOC_NPCM8XX_CLOCK_H
+#define __SOC_NPCM8XX_CLOCK_H
+
+#include <linux/auxiliary_bus.h>
+#include <linux/container_of.h>
+
+struct npcm_clock_adev {
+	void __iomem *base;
+	struct auxiliary_device adev;
+};
+
+#define to_npcm_clock_adev(_adev) \
+	container_of((_adev), struct npcm_clock_adev, adev)
+
+#endif
Signature · 1 line
2.34.1
maintainer Reviewed-by on v27 2/3
#3 lore raw

Re: [PATCH RESEND v27 2/3] reset: npcm: register npcm8xx clock auxiliary bus device

Quoted 138 lines · Tomer Maimon

Add NPCM8xx clock controller auxiliary bus device registration.

The NPCM8xx clock controller is registered as an aux device because the reset and the clock controller share the same register region.

Signed-off-by Tomer Maimon <[email protected]>
Tested-by Benjamin Fair <[email protected]>
---
 drivers/reset/Kconfig               |  1 +
 drivers/reset/reset-npcm.c          | 74 ++++++++++++++++++++++++++++-
 include/soc/nuvoton/clock-npcm8xx.h | 16 +++++++
 3 files changed, 90 insertions(+), 1 deletion(-)
 create mode 100755 include/soc/nuvoton/clock-npcm8xx.h
drivers/reset/Kconfig +1 -0
index 67bce340a87e..c6bf5275cca2 100644
@@ -157,6 +157,7 @@ config RESET_MESON_AUDIO_ARB
 config RESET_NPCM
 	bool "NPCM BMC Reset Driver" if COMPILE_TEST
 	default ARCH_NPCM
+	select AUXILIARY_BUS
 	help
 	  This enables the reset controller driver for Nuvoton NPCM
 	  BMC SoCs.
drivers/reset/reset-npcm.c +67 -0
index 8935ef95a2d1..aa68b947226a 100644
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 // Copyright (c) 2019 Nuvoton Technology corporation.
 
+#include <linux/auxiliary_bus.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/io.h>

@@ -10,11 +11,14 @@
 #include <linux/property.h>
 #include <linux/reboot.h>
 #include <linux/reset-controller.h>
+#include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
 #include <linux/of_address.h>
 
+#include <soc/nuvoton/clock-npcm8xx.h>
+
 /* NPCM7xx GCR registers */
 #define NPCM_MDLR_OFFSET	0x7C
 #define NPCM7XX_MDLR_USBD0	BIT(9)

@@ -89,6 +93,7 @@ struct npcm_rc_data {
 	const struct npcm_reset_info *info;
 	struct regmap *gcr_regmap;
 	u32 sw_reset_number;
+	struct device *dev;
 	void __iomem *base;
 	spinlock_t lock;
 };

@@ -372,6 +377,67 @@ static const struct reset_control_ops npcm_rc_ops = {
 	.status		= npcm_rc_status,
 };
 
+static void npcm_clock_unregister_adev(void *_adev)
+{
+	struct auxiliary_device *adev = _adev;
+
+	auxiliary_device_delete(adev);
+	auxiliary_device_uninit(adev);
+}
+
+static void npcm_clock_adev_release(struct device *dev)
+{
+	struct auxiliary_device *adev = to_auxiliary_dev(dev);
+	struct npcm_clock_adev *rdev = to_npcm_clock_adev(adev);
+
+	kfree(rdev);
+}
+
+static struct auxiliary_device *npcm_clock_adev_alloc(struct npcm_rc_data *rst_data, char *clk_name)
+{
+	struct npcm_clock_adev *rdev;
+	struct auxiliary_device *adev;
+	int ret;
+
+	rdev = kzalloc(sizeof(*rdev), GFP_KERNEL);
+	if (!rdev)
+		return ERR_PTR(-ENOMEM);
+
+	rdev->base = rst_data->base;
+
+	adev = &rdev->adev;
+	adev->name = clk_name;
+	adev->dev.parent = rst_data->dev;
+	adev->dev.release = npcm_clock_adev_release;
+	adev->id = 555u;
+
+	ret = auxiliary_device_init(adev);
+	if (ret) {
+		kfree(rdev);
+		return ERR_PTR(ret);
+	}
+
+	return adev;
+}
+
+static int npcm8xx_clock_controller_register(struct npcm_rc_data *rst_data, char *clk_name)
+{
+	struct auxiliary_device *adev;
+	int ret;
+
+	adev = npcm_clock_adev_alloc(rst_data, clk_name);
+	if (IS_ERR(adev))
+		return PTR_ERR(adev);
+
+	ret = auxiliary_device_add(adev);
+	if (ret) {
+		auxiliary_device_uninit(adev);
+		return ret;
+	}
+
+	return devm_add_action_or_reset(rst_data->dev, npcm_clock_unregister_adev, adev);
+}
+
 static int npcm_rc_probe(struct platform_device *pdev)
 {
 	struct npcm_rc_data *rc;

@@ -392,6 +458,7 @@ static int npcm_rc_probe(struct platform_device *pdev)
 	rc->rcdev.of_node = pdev->dev.of_node;
 	rc->rcdev.of_reset_n_cells = 2;
 	rc->rcdev.of_xlate = npcm_reset_xlate;
+	rc->dev = &pdev->dev;
 
 	ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev);
 	if (ret) {

drivers/reset/reset-npcm.c static int npcm_rc_probe(struct platform_device *pdev) · line 484

Quoted 6 lines
drivers/reset/reset-npcm.c +2 -1
@@ -413,7 +480,12 @@ static int npcm_rc_probe(struct platform_device *pdev)
 		}
 	}
 
-	return ret;
+	switch (rc->info->bmc_id) {
+	case BMC_NPCM8XX:

Here ret is ignored, which may be the return value from register_restart_handler() above.

Quoted 17 lines
drivers/reset/reset-npcm.c +4 -0
+		return npcm8xx_clock_controller_register(rc, "clk-npcm8xx");
+	default:
+		return ret;
+	}
 }
 
 static struct platform_driver npcm_rc_driver = {
include/soc/nuvoton/clock-npcm8xx.h new file +4 -0
new file mode 100755
index 000000000000..139130e98c51
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SOC_NPCM8XX_CLOCK_H
+#define __SOC_NPCM8XX_CLOCK_H
+

include/soc/nuvoton/clock-npcm8xx.h line 14

Quoted 10 lines
include/soc/nuvoton/clock-npcm8xx.h new file +10 -0
+#include <linux/auxiliary_bus.h>
+#include <linux/container_of.h>
+
+struct npcm_clock_adev {
+	void __iomem *base;
+	struct auxiliary_device adev;
+};
+
+#define to_npcm_clock_adev(_adev) \
+	container_of((_adev), struct npcm_clock_adev, adev)

Could you make this an inline function instead?

With those two issues addressed,

Reviewed-by Philipp Zabel <[email protected]>

regards
Philipp

author maintainer
#4 lore raw

Re: [PATCH RESEND v27 2/3] reset: npcm: register npcm8xx clock auxiliary bus device

Hi Philipp,

Thanks for your review.

Done in Version 28 :-)

Best regards,

Tomer

Quoted 186 lines · Philipp Zabel
Quoted 138 lines · Tomer Maimon

Add NPCM8xx clock controller auxiliary bus device registration.

The NPCM8xx clock controller is registered as an aux device because the reset and the clock controller share the same register region.

Signed-off-by Tomer Maimon <[email protected]>
Tested-by Benjamin Fair <[email protected]>
---
 drivers/reset/Kconfig               |  1 +
 drivers/reset/reset-npcm.c          | 74 ++++++++++++++++++++++++++++-
 include/soc/nuvoton/clock-npcm8xx.h | 16 +++++++
 3 files changed, 90 insertions(+), 1 deletion(-)
 create mode 100755 include/soc/nuvoton/clock-npcm8xx.h
drivers/reset/Kconfig +1 -0
index 67bce340a87e..c6bf5275cca2 100644
@@ -157,6 +157,7 @@ config RESET_MESON_AUDIO_ARB
 config RESET_NPCM
      bool "NPCM BMC Reset Driver" if COMPILE_TEST
      default ARCH_NPCM
+     select AUXILIARY_BUS
      help
        This enables the reset controller driver for Nuvoton NPCM
        BMC SoCs.
drivers/reset/reset-npcm.c +67 -0
index 8935ef95a2d1..aa68b947226a 100644
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 // Copyright (c) 2019 Nuvoton Technology corporation.
 
+#include <linux/auxiliary_bus.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/io.h>

@@ -10,11 +11,14 @@
 #include <linux/property.h>
 #include <linux/reboot.h>
 #include <linux/reset-controller.h>
+#include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
 #include <linux/of_address.h>
 
+#include <soc/nuvoton/clock-npcm8xx.h>
+
 /* NPCM7xx GCR registers */
 #define NPCM_MDLR_OFFSET     0x7C
 #define NPCM7XX_MDLR_USBD0   BIT(9)

@@ -89,6 +93,7 @@ struct npcm_rc_data {
      const struct npcm_reset_info *info;
      struct regmap *gcr_regmap;
      u32 sw_reset_number;
+     struct device *dev;
      void __iomem *base;
      spinlock_t lock;
 };

@@ -372,6 +377,67 @@ static const struct reset_control_ops npcm_rc_ops = {
      .status         = npcm_rc_status,
 };
 
+static void npcm_clock_unregister_adev(void *_adev)
+{
+     struct auxiliary_device *adev = _adev;
+
+     auxiliary_device_delete(adev);
+     auxiliary_device_uninit(adev);
+}
+
+static void npcm_clock_adev_release(struct device *dev)
+{
+     struct auxiliary_device *adev = to_auxiliary_dev(dev);
+     struct npcm_clock_adev *rdev = to_npcm_clock_adev(adev);
+
+     kfree(rdev);
+}
+
+static struct auxiliary_device *npcm_clock_adev_alloc(struct npcm_rc_data *rst_data, char *clk_name)
+{
+     struct npcm_clock_adev *rdev;
+     struct auxiliary_device *adev;
+     int ret;
+
+     rdev = kzalloc(sizeof(*rdev), GFP_KERNEL);
+     if (!rdev)
+             return ERR_PTR(-ENOMEM);
+
+     rdev->base = rst_data->base;
+
+     adev = &rdev->adev;
+     adev->name = clk_name;
+     adev->dev.parent = rst_data->dev;
+     adev->dev.release = npcm_clock_adev_release;
+     adev->id = 555u;
+
+     ret = auxiliary_device_init(adev);
+     if (ret) {
+             kfree(rdev);
+             return ERR_PTR(ret);
+     }
+
+     return adev;
+}
+
+static int npcm8xx_clock_controller_register(struct npcm_rc_data *rst_data, char *clk_name)
+{
+     struct auxiliary_device *adev;
+     int ret;
+
+     adev = npcm_clock_adev_alloc(rst_data, clk_name);
+     if (IS_ERR(adev))
+             return PTR_ERR(adev);
+
+     ret = auxiliary_device_add(adev);
+     if (ret) {
+             auxiliary_device_uninit(adev);
+             return ret;
+     }
+
+     return devm_add_action_or_reset(rst_data->dev, npcm_clock_unregister_adev, adev);
+}
+
 static int npcm_rc_probe(struct platform_device *pdev)
 {
      struct npcm_rc_data *rc;

@@ -392,6 +458,7 @@ static int npcm_rc_probe(struct platform_device *pdev)
      rc->rcdev.of_node = pdev->dev.of_node;
      rc->rcdev.of_reset_n_cells = 2;
      rc->rcdev.of_xlate = npcm_reset_xlate;
+     rc->dev = &pdev->dev;
 
      ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev);
      if (ret) {

drivers/reset/reset-npcm.c static int npcm_rc_probe(struct platform_device *pdev) · line 484

Quoted 6 lines
drivers/reset/reset-npcm.c +2 -1
@@ -413,7 +480,12 @@ static int npcm_rc_probe(struct platform_device *pdev)
              }
      }
 
-     return ret;
+     switch (rc->info->bmc_id) {
+     case BMC_NPCM8XX:

Here ret is ignored, which may be the return value from register_restart_handler() above.

Quoted 17 lines
drivers/reset/reset-npcm.c +4 -0
+             return npcm8xx_clock_controller_register(rc, "clk-npcm8xx");
+     default:
+             return ret;
+     }
 }
 
 static struct platform_driver npcm_rc_driver = {
include/soc/nuvoton/clock-npcm8xx.h new file +4 -0
new file mode 100755
index 000000000000..139130e98c51
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SOC_NPCM8XX_CLOCK_H
+#define __SOC_NPCM8XX_CLOCK_H
+

include/soc/nuvoton/clock-npcm8xx.h line 14

Quoted 10 lines
include/soc/nuvoton/clock-npcm8xx.h new file +10 -0
+#include <linux/auxiliary_bus.h>
+#include <linux/container_of.h>
+
+struct npcm_clock_adev {
+     void __iomem *base;
+     struct auxiliary_device adev;
+};
+
+#define to_npcm_clock_adev(_adev) \
+     container_of((_adev), struct npcm_clock_adev, adev)

Could you make this an inline function instead?

With those two issues addressed,

Reviewed-by Philipp Zabel <[email protected]>

regards
Philipp

author maintainer
#5 lore raw

PATCH RESEND v27 3/3 clk: npcm8xx: add clock controller

In reply to Tomer Maimon

Add auxiliary driver to support Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller which generates and supplies clocks to all modules within the BMC.

The NPCM8xx clock controller is created using the auxiliary device framework and set up in the npcm reset driver since the NPCM8xx clock is using the same register region.

Signed-off-by Tomer Maimon <[email protected]>
Tested-by Benjamin Fair <[email protected]>
---
 drivers/clk/Kconfig       |   8 +
 drivers/clk/Makefile      |   1 +
 drivers/clk/clk-npcm8xx.c | 430 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 439 insertions(+)
 create mode 100644 drivers/clk/clk-npcm8xx.c
drivers/clk/Kconfig +8 -0
index 983ef4f36d8c..335cd2ede139 100644
@@ -334,6 +334,14 @@ config COMMON_CLK_LOCHNAGAR
 	  This driver supports the clocking features of the Cirrus Logic
 	  Lochnagar audio development board.
 
+config COMMON_CLK_NPCM8XX
+	tristate "Clock driver for the NPCM8XX SoC Family"
+	depends on ARCH_NPCM || COMPILE_TEST
+	help
+	  This driver supports the clocks on the Nuvoton BMC NPCM8XX SoC Family,
+	  all the clocks are initialized by the bootloader, so this driver
+	  allows only reading of current settings directly from the hardware.
+
 config COMMON_CLK_LOONGSON2
 	bool "Clock driver for Loongson-2 SoC"
 	depends on LOONGARCH || COMPILE_TEST
drivers/clk/Makefile +1 -0
index f793a16cad40..b8367b47d2b8 100644
@@ -52,6 +52,7 @@ obj-$(CONFIG_ARCH_MILBEAUT_M10V)	+= clk-milbeaut.o
 obj-$(CONFIG_ARCH_MOXART)		+= clk-moxart.o
 obj-$(CONFIG_ARCH_NOMADIK)		+= clk-nomadik.o
 obj-$(CONFIG_ARCH_NPCM7XX)	    	+= clk-npcm7xx.o
+obj-$(CONFIG_COMMON_CLK_NPCM8XX)	+= clk-npcm8xx.o
 obj-$(CONFIG_ARCH_NSPIRE)		+= clk-nspire.o
 obj-$(CONFIG_COMMON_CLK_PALMAS)		+= clk-palmas.o
 obj-$(CONFIG_CLK_LS1028A_PLLDIG)	+= clk-plldig.o
drivers/clk/clk-npcm8xx.c new file +430 -0

430 lines not on this page · raw message

Signature · 1 line
2.34.1
maintainer Reviewed-by on v27 3/3
#6 lore raw

Re: [PATCH RESEND v27 3/3] clk: npcm8xx: add clock controller

Quoting Tomer Maimon (2024-08-15 08:02:55)

Quoted 11 lines

Add auxiliary driver to support Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller which generates and supplies clocks to all modules within the BMC.

The NPCM8xx clock controller is created using the auxiliary device framework and set up in the npcm reset driver since the NPCM8xx clock is using the same register region.

Signed-off-by Tomer Maimon <[email protected]>
Tested-by Benjamin Fair <[email protected]>

---

Reviewed-by Stephen Boyd <[email protected]>
maintainer
#7 lore raw
In reply to Tomer Maimon

Quoting Tomer Maimon (2024-08-15 08:02:52)

Quoted 7 lines

This patchset adds clock support for the Nuvoton Arbel NPCM8XX Board Management controller (BMC) SoC family.

The NPCM8xx clock controller is created using the auxiliary device framework and set up in the npcm reset driver since the NPCM8xx clock is using the same register region.

Quoted 6 lines

This patchset cover letter is based from the initial support for NPCM8xx BMC to keep tracking the version history.

This patchset was tested on the Arbel NPCM8XX evaluation board.

No changes since version 26, only tested in kernel 6.11.rc1

Thanks for working on this! I'm waiting for Philipp to review/ack the reset driver part. Until then I don't think I can apply this series to the clk tree. I'll add a review tag to the clk driver patch in case that helps.

author maintainer
#8 lore raw

Hi Stephen,

Sure.

Thanks a lot,

Tomer

Quoted 20 lines · Stephen Boyd

Quoting Tomer Maimon (2024-08-15 08:02:52)

Quoted 7 lines

This patchset adds clock support for the Nuvoton Arbel NPCM8XX Board Management controller (BMC) SoC family.

The NPCM8xx clock controller is created using the auxiliary device framework and set up in the npcm reset driver since the NPCM8xx clock is using the same register region.

Quoted 6 lines

This patchset cover letter is based from the initial support for NPCM8xx BMC to keep tracking the version history.

This patchset was tested on the Arbel NPCM8XX evaluation board.

No changes since version 26, only tested in kernel 6.11.rc1

Thanks for working on this! I'm waiting for Philipp to review/ack the reset driver part. Until then I don't think I can apply this series to the clk tree. I'll add a review tag to the clk driver patch in case that helps.

author maintainer
#9 lore raw

Hi Stephen,

Philipp approved the reset patch with the minor changes; these minor changes are already addressed in V28 that sent few minutes ago.

So the clock patchset could be applied :-)

Appreciate your efforts and guidance.

Best regards,

Tomer

Quoted 30 lines · Tomer Maimon

Hi Stephen,

Sure.

Thanks a lot,

Tomer

Quoted 20 lines · Stephen Boyd

Quoting Tomer Maimon (2024-08-15 08:02:52)

Quoted 7 lines

This patchset adds clock support for the Nuvoton Arbel NPCM8XX Board Management controller (BMC) SoC family.

The NPCM8xx clock controller is created using the auxiliary device framework and set up in the npcm reset driver since the NPCM8xx clock is using the same register region.

Quoted 6 lines

This patchset cover letter is based from the initial support for NPCM8xx BMC to keep tracking the version history.

This patchset was tested on the Arbel NPCM8XX evaluation board.

No changes since version 26, only tested in kernel 6.11.rc1

Thanks for working on this! I'm waiting for Philipp to review/ack the reset driver part. Until then I don't think I can apply this series to the clk tree. I'll add a review tag to the clk driver patch in case that helps.