riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110

RFC PATCH Superseded E Shattow 2 participants 9 messages Jan 2, 2025 – Jan 24, 2025

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Device tree bindings RISC-V StarFive devicetrees

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E Shattow

author

2025-01-02 20:42 UTC #0 lore raw

cover riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110

U-Boot boot loader has adopted using the Linux dt-rebasing tree for dts with JH7110 VisionFive2 board target (and related JH7110 common boards). Sync the minimum changes from jh7110.dtsi needed for boot so these can be dropped from U-Boot.

This series of jh7110.dtsi changes is RFC as being uncertain about what is required for boot. Testing, review, and suggestions are appreciated.

E Shattow (3):
riscv: dts: starfive: jh7110: add timer node
riscv: dts: starfive: jh7110: add DRAM memory controller node
riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
loader

 arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 ++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

base-commit: 708d55db3edbe2ccf88d94b5f2e2b404bc0ba37c

Signature · 1 line

2.45.2

E Shattow

author

2025-01-02 20:42 UTC #1 lore raw

RFC PATCH 1/3 riscv: dts: starfive: jh7110: add timer node

no idea if this does anything useful; not needed for boot

Signed-off-by E Shattow <[email protected]>

---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

arch/riscv/boot/dts/starfive/jh7110.dtsi +9 -0

index 0d8339357bad..0bc922b3ae8a 100644
@@ -344,6 +344,15 @@ tdm_ext: tdm-ext-clock {
 		#clock-cells = <0>;
 	};
 
+	timer {
+		compatible = "riscv, timer";
+		interrupts-extended = <&cpu0_intc 5>,
+				      <&cpu1_intc 5>,
+				      <&cpu2_intc 5>,
+				      <&cpu3_intc 5>,
+				      <&cpu4_intc 5>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&plic>;

Signature · 1 line

2.45.2

E Shattow

author

2025-01-02 20:42 UTC #5 lore raw

RFC PATCH 2/3 riscv: dts: starfive: jh7110: add DRAM memory controller node

In reply to E Shattow

add DRAM memory controller node (no driver), required for U-Boot to boot successfully.

Signed-off-by E Shattow <[email protected]>

---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

arch/riscv/boot/dts/starfive/jh7110.dtsi +13 -0

index 0bc922b3ae8a..6948974400c1 100644
@@ -381,6 +381,19 @@ ccache: cache-controller@2010000 {
 			cache-unified;
 		};
 
+		dmc: dmc@15700000 {
+			compatible = "starfive,jh7110-dmc";
+			reg = <0x0 0x15700000 0x0 0x10000>,
+			      <0x0 0x13000000 0x0 0x10000>;
+			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+				 <&syscrg JH7110_SYSRST_DDR_OSC>,
+				 <&syscrg JH7110_SYSRST_DDR_APB>;
+			reset-names = "axi", "osc", "apb";
+			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+			clock-names = "pll1_out";
+			clock-frequency = <2133>;
+		};
+
 		plic: interrupt-controller@c000000 {
 			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;

Signature · 1 line

2.45.2

E Shattow

author

2025-01-02 20:42 UTC #7 lore raw

RFC PATCH 3/3 riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader

In reply to E Shattow

Add bootph-pre-ram hinting to jh7110.dtsi:
- CPU interrupt controller(s)
- timer
- DRAM memory controller
- oscillator
- syscrg clock-controller
- (optional) dma controller
- (optional) aoncrg clock-controller

With this the U-Boot SPL secondary program loader may drop such overrides when using dt-rebasing with JH7110 OF_UPSTREAM board targets.

Signed-off-by E Shattow <[email protected]>

---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

arch/riscv/boot/dts/starfive/jh7110.dtsi +11 -0

index 6948974400c1..4f19b88fe73f 100644
@@ -37,6 +37,7 @@ cpu0_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				interrupt-controller;
 				#interrupt-cells = <1>;
+				bootph-pre-ram;
 			};
 		};

@@ -70,6 +71,7 @@ cpu1_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				interrupt-controller;
 				#interrupt-cells = <1>;
+				bootph-pre-ram;
 			};
 		};

@@ -103,6 +105,7 @@ cpu2_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				interrupt-controller;
 				#interrupt-cells = <1>;
+				bootph-pre-ram;
 			};
 		};

@@ -136,6 +139,7 @@ cpu3_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				interrupt-controller;
 				#interrupt-cells = <1>;
+				bootph-pre-ram;
 			};
 		};

@@ -169,6 +173,7 @@ cpu4_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				interrupt-controller;
 				#interrupt-cells = <1>;
+				bootph-pre-ram;
 			};
 		};

@@ -323,6 +328,7 @@ osc: oscillator {
 		compatible = "fixed-clock";
 		clock-output-names = "osc";
 		#clock-cells = <0>;
+		bootph-pre-ram;
 	};
 
 	rtc_osc: rtc-oscillator {

@@ -368,6 +374,7 @@ clint: timer@2000000 {
 					      <&cpu2_intc 3>, <&cpu2_intc 7>,
 					      <&cpu3_intc 3>, <&cpu3_intc 7>,
 					      <&cpu4_intc 3>, <&cpu4_intc 7>;
+			bootph-pre-ram;
 		};
 
 		ccache: cache-controller@2010000 {

@@ -382,6 +389,7 @@ ccache: cache-controller@2010000 {
 		};
 
 		dmc: dmc@15700000 {
+			bootph-pre-ram;
 			compatible = "starfive,jh7110-dmc";
 			reg = <0x0 0x15700000 0x0 0x10000>,
 			      <0x0 0x13000000 0x0 0x10000>;

@@ -916,6 +924,7 @@ syscrg: clock-controller@13020000 {
 				      "pll0_out", "pll1_out", "pll2_out";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
+			bootph-pre-ram;
 		};
 
 		sys_syscon: syscon@13030000 {

@@ -1098,6 +1107,7 @@ dma: dma-controller@16050000 {
 			snps,block-size = <65536 65536 65536 65536>;
 			snps,priority = <0 1 2 3>;
 			snps,axi-max-burst-len = <16>;
+			bootph-pre-ram;
 		};
 
 		aoncrg: clock-controller@17000000 {

@@ -1115,6 +1125,7 @@ aoncrg: clock-controller@17000000 {
 				      "rtc_osc";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
+			bootph-pre-ram;
 		};
 
 		aon_syscon: syscon@17010000 {

Signature · 1 line

2.45.2

Conor Dooley

maintainer

2025-01-13 18:39 UTC #2 lore raw

Re: [RFC PATCH v1 1/3] riscv: dts: starfive: jh7110: add timer node

In reply to E Shattow

Quoted 12 lines · E Shattow

no idea if this does anything useful; not needed for boot
Signed-off-by E Shattow <[email protected]>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/riscv/boot/dts/starfive/jh7110.dtsi +0 -0
index 0d8339357bad..0bc922b3ae8a 100644

arch/riscv/boot/dts/starfive/jh7110.dtsi tdm_ext: tdm-ext-clock { · line 348

Quoted 5 lines

arch/riscv/boot/dts/starfive/jh7110.dtsi +2 -0

@@ -344,6 +344,15 @@ tdm_ext: tdm-ext-clock {
 		#clock-cells = <0>;
 	};
 
+	timer {
+		compatible = "riscv, timer";

compatible has an extra space, so won't do anything!

Quoted 13 lines

arch/riscv/boot/dts/starfive/jh7110.dtsi +7 -0

+		interrupts-extended = <&cpu0_intc 5>,
+				      <&cpu1_intc 5>,
+				      <&cpu2_intc 5>,
+				      <&cpu3_intc 5>,
+				      <&cpu4_intc 5>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&plic>;

Signature · 1 line

2.45.2

Conor Dooley

maintainer

2025-01-13 18:41 UTC #6 lore raw

Re: [RFC PATCH v1 2/3] riscv: dts: starfive: jh7110: add DRAM memory controller node

In reply to E Shattow

Quoted 13 lines · E Shattow

add DRAM memory controller node (no driver), required for U-Boot to boot successfully.
Signed-off-by E Shattow <[email protected]>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)
arch/riscv/boot/dts/starfive/jh7110.dtsi +0 -0
index 0bc922b3ae8a..6948974400c1 100644

arch/riscv/boot/dts/starfive/jh7110.dtsi ccache: cache-controller@2010000 { · line 384

Quoted 4 lines

arch/riscv/boot/dts/starfive/jh7110.dtsi +1 -0

@@ -381,6 +381,19 @@ ccache: cache-controller@2010000 {
 			cache-unified;
 		};
 
+		dmc: dmc@15700000 {

memory-controller@157.... cos you don't need the label and "dmc" isn't generic. You're missing a binding for this either way.

Quoted 20 lines

arch/riscv/boot/dts/starfive/jh7110.dtsi +12 -0

+			compatible = "starfive,jh7110-dmc";
 
 
+			reg = <0x0 0x15700000 0x0 0x10000>,
+			      <0x0 0x13000000 0x0 0x10000>;
+			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+				 <&syscrg JH7110_SYSRST_DDR_OSC>,
+				 <&syscrg JH7110_SYSRST_DDR_APB>;
+			reset-names = "axi", "osc", "apb";
+			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+			clock-names = "pll1_out";
+			clock-frequency = <2133>;
+		};
+
 		plic: interrupt-controller@c000000 {

arch/riscv/boot/dts/starfive/jh7110.dtsi +0 -0

 			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;

Signature · 1 line

2.45.2

Conor Dooley

maintainer

2025-01-13 18:41 UTC #8 lore raw

In reply to E Shattow

Quoted 7 lines · E Shattow

U-Boot boot loader has adopted using the Linux dt-rebasing tree for dts with JH7110 VisionFive2 board target (and related JH7110 common boards). Sync the minimum changes from jh7110.dtsi needed for boot so these can be dropped from U-Boot.
This series of jh7110.dtsi changes is RFC as being uncertain about what is required for boot. Testing, review, and suggestions are appreciated.

I don't see a reason not to take this stuff, provided it passes dtbs_check.

E Shattow

author

2025-01-24 11:19 UTC #3 lore raw

Re: [RFC PATCH v1 1/3] riscv: dts: starfive: jh7110: add timer node

In reply to Conor Dooley

Quoted 21 lines · Conor Dooley

Quoted 12 lines · E Shattow
no idea if this does anything useful; not needed for boot
Signed-off-by E Shattow <[email protected]>
---
  arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++
  1 file changed, 9 insertions(+)
arch/riscv/boot/dts/starfive/jh7110.dtsi +0 -0
index 0d8339357bad..0bc922b3ae8a 100644
arch/riscv/boot/dts/starfive/jh7110.dtsi tdm_ext: tdm-ext-clock { · line 348
Quoted 5 lines
arch/riscv/boot/dts/starfive/jh7110.dtsi +2 -0
@@ -344,6 +344,15 @@ tdm_ext: tdm-ext-clock {
  		#clock-cells = <0>;
  	};
 
+	timer {
+		compatible = "riscv, timer";
compatible has an extra space, so won't do anything!

Quoted 13 lines

arch/riscv/boot/dts/starfive/jh7110.dtsi +7 -0

+		interrupts-extended = <&cpu0_intc 5>,
+				      <&cpu1_intc 5>,
+				      <&cpu2_intc 5>,
+				      <&cpu3_intc 5>,
+				      <&cpu4_intc 5>;
+	};
+
  	soc {
  		compatible = "simple-bus";
  		interrupt-parent = <&plic>;

Signature · 1 line

2.45.2

That extra space is my error and does not exist in U-Boot. Good catch! So, when corrected it appears to boot either way with or without and not any change in functionality that I can discern. My priority then for this series is to drop this patch as something unnecessary.

Thanks, Conor!

-E

Conor Dooley

maintainer

2025-01-24 16:40 UTC #4 lore raw

Re: [RFC PATCH v1 1/3] riscv: dts: starfive: jh7110: add timer node

Quoted 32 lines · E Shattow

Quoted 30 lines · Conor Dooley
Quoted 12 lines · E Shattow
no idea if this does anything useful; not needed for boot
Signed-off-by E Shattow <[email protected]>
---
  arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++
  1 file changed, 9 insertions(+)
arch/riscv/boot/dts/starfive/jh7110.dtsi +0 -0
index 0d8339357bad..0bc922b3ae8a 100644
arch/riscv/boot/dts/starfive/jh7110.dtsi tdm_ext: tdm-ext-clock { · line 347
Quoted 4 lines
arch/riscv/boot/dts/starfive/jh7110.dtsi +2 -0
@@ -344,6 +344,15 @@ tdm_ext: tdm-ext-clock {
  		#clock-cells = <0>;
  	};
+	timer {
+		compatible = "riscv, timer";
compatible has an extra space, so won't do anything!
Quoted 10 lines
arch/riscv/boot/dts/starfive/jh7110.dtsi +7 -0
+		interrupts-extended = <&cpu0_intc 5>,
+				      <&cpu1_intc 5>,
+				      <&cpu2_intc 5>,
+				      <&cpu3_intc 5>,
+				      <&cpu4_intc 5>;
+	};
+
  	soc {
  		compatible = "simple-bus";
  		interrupt-parent = <&plic>;

Quoted 8 lines

Quoted 3 lines
Quoted 3 lines
Signature · 1 line
2.45.2
That extra space is my error and does not exist in U-Boot. Good catch! So, when corrected it appears to boot either way with or without and not any change in functionality that I can discern. My priority then for this series is to drop this patch as something unnecessary.

I don't mind having it, if it makes the hw description more complete, even if not used.