clk: meson-g12a: fix missing spicc clks to clk_sel
Subsystems (4)
PATCH 1/1 clk: meson-g12a: fix missing spicc clks to clk_sel
HHI_SPICC_CLK_CNTL bits 25:23 controls spicc clk_sel.
It is missing fclk_div 2 and gp0_pll which causes the spicc module to output the incorrect clocks for spicc sclk at 2.5x the expected rate.
Add the missing clocks resolves this.
--- drivers/clk/meson/g12a.c | 2 ++ 1 file changed, 2 insertions(+)
drivers/clk/meson/g12a.c +2 -0
@@ -4099,8 +4099,10 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = { { .hw = &g12a_clk81.hw }, { .hw = &g12a_fclk_div4.hw }, { .hw = &g12a_fclk_div3.hw }, + { .hw = &g12a_fclk_div2.hw }, { .hw = &g12a_fclk_div5.hw }, { .hw = &g12a_fclk_div7.hw }, + { .hw = &g12a_gp0_pll.hw, }, };static struct clk_regmap g12a_spicc0_sclk_sel = {
Signature · 1 line
2.39.5
Sorry, this is an older version of the patch without Fixes tag from a mv error. I'm sending a v2, ignore this one.
Quoted 37 lines · Da Xue
HHI_SPICC_CLK_CNTLbits 25:23 controls spiccclk_sel.It is missing
fclk_div2 andgp0_pllwhich causes the spicc module to output the incorrect clocks for spicc sclk at 2.5x the expected rate.Add the missing clocks resolves this.
Cc <[email protected]> # 6.1.x: a18c8e0: clk: meson: g12a: addSigned-off-by Da Xue <[email protected]>--- drivers/clk/meson/g12a.c | 2 ++ 1 file changed, 2 insertions(+)drivers/clk/meson/g12a.c +2
-1@@ -4099,8 +4099,10 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = { { .hw = &g12a_clk81.hw }, { .hw = &g12a_fclk_div4.hw }, { .hw = &g12a_fclk_div3.hw }, + { .hw = &g12a_fclk_div2.hw }, { .hw = &g12a_fclk_div5.hw }, { .hw = &g12a_fclk_div7.hw }, + { .hw = &g12a_gp0_pll.hw, }, };static struct clk_regmap g12a_spicc0_sclk_sel = { --2.39.5
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