clk: meson-g12a: fix missing spicc clks to clk_sel
Subsystems (4)
PATCH v2 1/1 clk: meson-g12a: fix missing spicc clks to clk_sel
HHI_SPICC_CLK_CNTL bits 25:23 controls spicc clk_sel.
It is missing fclk_div 2 and gp0_pll which causes the spicc module to output the incorrect clocks for spicc sclk at 2.5x the expected rate.
Add the missing clocks resolves this.
---
Changelog:
v1 -> v2: add Fixes as an older version of the patch was incorrectly sent as v1
--- drivers/clk/meson/g12a.c | 2 ++ 1 file changed, 2 insertions(+)
drivers/clk/meson/g12a.c +2 -0
@@ -4099,8 +4099,10 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = { { .hw = &g12a_clk81.hw }, { .hw = &g12a_fclk_div4.hw }, { .hw = &g12a_fclk_div3.hw }, + { .hw = &g12a_fclk_div2.hw }, { .hw = &g12a_fclk_div5.hw }, { .hw = &g12a_fclk_div7.hw }, + { .hw = &g12a_gp0_pll.hw, }, };static struct clk_regmap g12a_spicc0_sclk_sel = {
Signature · 1 line
2.39.5
Neil Armstrong
maintainerHi,
Quoted 1 line · Da Xue
HHI_SPICC_CLK_CNTLbits 25:23 controls spiccclk_sel.
This sentence can be removed, this patch doesn't change anything in this= regard.
Quoted 3 lines
It is missing
fclk_div2 andgp0_pllwhich causes the spicc module to output the incorrect clocks for spicc sclk at 2.5x the expected rate.
The sentence is not correct, the spicc sclk will be at the freq computed but CCF, it simply can't achieve the requested rate without the missing parents.
But I'm against adding the GP0 PLL since this PLL is required to drive DSI panels.
And GP0 isn't needed since on G12, the SPICC has the "enhance_clk_div" which should be able to to reach much more rates with the fclk_divX clocks.
Neil
Quoted 29 lines
Add the missing clocks resolves this.
Fixes a18c8e0b7697 ("clk: meson: g12a: add support for the SPICC SCLK Source clocks")Cc <[email protected]> # 6.1Signed-off-by Da Xue <[email protected]>---
Changelog:v1 -> v2: add Fixes as an older version of the patch was incorrectly sent as v1
--- drivers/clk/meson/g12a.c | 2 ++ 1 file changed, 2 insertions(+)drivers/clk/meson/g12a.c +2
-0@@ -4099,8 +4099,10 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = { { .hw = &g12a_clk81.hw }, { .hw = &g12a_fclk_div4.hw }, { .hw = &g12a_fclk_div3.hw }, + { .hw = &g12a_fclk_div2.hw }, { .hw = &g12a_fclk_div5.hw }, { .hw = &g12a_fclk_div7.hw }, + { .hw = &g12a_gp0_pll.hw, }, };static struct clk_regmap g12a_spicc0_sclk_sel = {