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arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes

PATCH Superseded Rob Herring (Arm) 2 participants 4 messages Feb 19 – Feb 27

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Device tree bindings Arm i.MX and Layerscape

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Rob Herring (Arm)

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#0 lore raw

PATCH 1/1 arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes

i.MX93 contains an Arm Ethos-U65 NPU. The NPU uses the internal SRAM for temporary buffers. The SRAM is larger than 96KB, but that is all that is available to non-secure world.

Signed-off-by Rob Herring (Arm) <[email protected]>

---
NXP folks, any comments on NPU freq? IIRC, the clock controller supports setting the freq to 1GHz. Is that supported?

---
 arch/arm64/boot/dts/freescale/imx93.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
arch/arm64/boot/dts/freescale/imx93.dtsi +23 -0
index 7b27012dfcb5..d826d4b5a06b 100644
@@ -43,6 +43,29 @@ map0 {
 			};
 		};
 	};
+
+	sram: sram@20480000 {
+		compatible = "mmio-sram";
+		reg = <0x0 0x20480000 0x0 0x18000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x20480000 0x18000>;
+	};
+
+	soc@0 {
+		npu@4a900000 {
+			compatible = "fsl,imx93-npu", "arm,ethos-u65";
+			reg = <0x4a900000 0x1000>;
+			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&mlmix>;
+			clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+			clock-names = "core", "apb";
+			sram = <&sram>;
+			assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+			assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_24M>;
+			assigned-clock-rates = <800000000>, <24000000>;
+		};
+	};
 };
 
 &aips1 {
Signature · 1 line
2.51.0
#1 lore raw

Hi Rob,

Quoted 8 lines · Rob Herring (Arm)

i.MX93 contains an Arm Ethos-U65 NPU. The NPU uses the internal SRAM for temporary buffers. The SRAM is larger than 96KB, but that is all that is available to non-secure world.

Signed-off-by Rob Herring (Arm) <[email protected]>

---
NXP folks, any comments on NPU freq? IIRC, the clock controller supports setting the freq to 1GHz. Is that supported?

NPU supports three freqs:
500MHz for Low Drive mode
800MHz for Nominal Drive mode
1GHz for Over drive mode

The NXP downstream choose nominal drive mode for peripherals, in NXP downstream, there is a driver to do nominal and over drive mode switch for the SoC at runtime(through sysfs interface by user), there is no dedicated arm core voltage supply, there is only one vdd soc supply.

To avoid introduce complexity to various drivers, drivers use nomimal freq, so OD->ND switch does not require drivers to update its own clock frequencies.

Quoted 23 lines

---
arch/arm64/boot/dts/freescale/imx93.dtsi | 23 +++++++++++++++++++++++

1 file changed, 23 insertions(+)
arch/arm64/boot/dts/freescale/imx93.dtsi +11 -0
index 7b27012dfcb5..d826d4b5a06b 100644
@@ -43,6 +43,29 @@ map0 {
 			};
 		};
 	};
+
+	sram: sram@20480000 {
+		compatible = "mmio-sram";
+		reg = <0x0 0x20480000 0x0 0x18000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x20480000 0x18000>;
+	};
+
+	soc@0 {
+		npu@4a900000 {

arch/arm64/boot/dts/freescale/imx93.dtsi map0 { · line 66

Quoted 10 lines
arch/arm64/boot/dts/freescale/imx93.dtsi +10 -0
+			compatible = "fsl,imx93-npu", "arm,ethos-u65";
+			reg = <0x4a900000 0x1000>;
+			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&mlmix>;
+			clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+			clock-names = "core", "apb";
+			sram = <&sram>;
+			assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+			assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_24M>;
+			assigned-clock-rates = <800000000>, <24000000>;

APB could run at 133.3MHz.

Regards
Peng

Quoted 8 lines
arch/arm64/boot/dts/freescale/imx93.dtsi +2 -0
+		};
+	};
 };
 
 &aips1 {
Signature · 1 line
2.51.0
author maintainer
#2 lore raw
Quoted 53 lines · Peng Fan

Hi Rob,

Quoted 8 lines · Rob Herring (Arm)

i.MX93 contains an Arm Ethos-U65 NPU. The NPU uses the internal SRAM for temporary buffers. The SRAM is larger than 96KB, but that is all that is available to non-secure world.

Signed-off-by Rob Herring (Arm) <[email protected]>

---
NXP folks, any comments on NPU freq? IIRC, the clock controller supports setting the freq to 1GHz. Is that supported?

NPU supports three freqs:
500MHz for Low Drive mode
800MHz for Nominal Drive mode
1GHz for Over drive mode

The NXP downstream choose nominal drive mode for peripherals, in NXP downstream, there is a driver to do nominal and over drive mode switch for the SoC at runtime(through sysfs interface by user), there is no dedicated arm core voltage supply, there is only one vdd soc supply.

To avoid introduce complexity to various drivers, drivers use nomimal freq, so OD->ND switch does not require drivers to update its own clock frequencies.

Quoted 27 lines

---
arch/arm64/boot/dts/freescale/imx93.dtsi | 23 +++++++++++++++++++++++

1 file changed, 23 insertions(+)
arch/arm64/boot/dts/freescale/imx93.dtsi +15 -0
index 7b27012dfcb5..d826d4b5a06b 100644
@@ -43,6 +43,29 @@ map0 {
                      };
              };
      };
+
+      sram: sram@20480000 {
+              compatible = "mmio-sram";
+              reg = <0x0 0x20480000 0x0 0x18000>;
+              #address-cells = <1>;
+              #size-cells = <1>;
+              ranges = <0x0 0x0 0x20480000 0x18000>;
+      };
+
+      soc@0 {
+              npu@4a900000 {
+                      compatible = "fsl,imx93-npu", "arm,ethos-u65";
+                      reg = <0x4a900000 0x1000>;
+                      interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+                      power-domains = <&mlmix>;
Quoted 8 lines

arch/arm64/boot/dts/freescale/imx93.dtsi map0 { · line 66

Quoted 6 lines
arch/arm64/boot/dts/freescale/imx93.dtsi +6 -0
+                      clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+                      clock-names = "core", "apb";
+                      sram = <&sram>;
+                      assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+                      assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_24M>;
+                      assigned-clock-rates = <800000000>, <24000000>;

APB could run at 133.3MHz.

24MHz does seem a bit slow. Do you know what parent would that be?

Rob

#3 lore raw
Quoted 1 line

Subject: Re: [PATCH] arm64: dts: freescale: imx93: Add Ethos-U65 NPU

[...]

Quoted 12 lines
Quoted 7 lines

arch/arm64/boot/dts/freescale/imx93.dtsi map0 {

Quoted 7 lines
arch/arm64/boot/dts/freescale/imx93.dtsi +7 -0
+      soc@0 {
+              npu@4a900000 {
+                      compatible = "fsl,imx93-npu", "arm,ethos-u65";
+                      reg = <0x4a900000 0x1000>;
+                      interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+                      power-domains = <&mlmix>;
+                      clocks = <&clk IMX93_CLK_ML>, <&clk

IMX93_CLK_ML_APB>;

Quoted 3 lines

arch/arm64/boot/dts/freescale/imx93.dtsi map0 {

Quoted 3 lines
arch/arm64/boot/dts/freescale/imx93.dtsi +3 -0
+                      clock-names = "core", "apb";
+                      sram = <&sram>;
+                      assigned-clocks = <&clk IMX93_CLK_ML>, <&clk

IMX93_CLK_ML_APB>;

Quoted 8 lines
Quoted 1 line
Quoted 1 line

+ assigned-clock-parents = <&clk

IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_24M>;

Quoted 4 lines
Quoted 2 lines

+ assigned-clock-rates = <800000000>,
+ <24000000>;

APB could run at 133.3MHz.

24MHz does seem a bit slow. Do you know what parent would that be?

Please try below:
Parent: <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
Rate: <133000000>;

Regards
Peng.

Quoted 2 lines

Rob