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arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes

PATCH Applied Rob Herring (Arm) 4 participants 4 messages Mar 6 – Mar 23

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Rob Herring (Arm)

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#0 lore raw

PATCH v2 1/1 arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes

i.MX93 contains an Arm Ethos-U65 NPU. The NPU uses the internal SRAM for temporary buffers. The SRAM is larger than 96KB, but that is all that is available to non-secure world.

Signed-off-by Rob Herring (Arm) <[email protected]>

---
v2:
- Increase the APB freq to 133MHz

---
 arch/arm64/boot/dts/freescale/imx93.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
arch/arm64/boot/dts/freescale/imx93.dtsi +23 -0
index 7b27012dfcb5..95cc60158349 100644
@@ -43,6 +43,29 @@ map0 {
 			};
 		};
 	};
+
+	sram: sram@20480000 {
+		compatible = "mmio-sram";
+		reg = <0x0 0x20480000 0x0 0x18000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x20480000 0x18000>;
+	};
+
+	soc@0 {
+		npu@4a900000 {
+			compatible = "fsl,imx93-npu", "arm,ethos-u65";
+			reg = <0x4a900000 0x1000>;
+			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&mlmix>;
+			clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+			clock-names = "core", "apb";
+			sram = <&sram>;
+			assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+			assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+			assigned-clock-rates = <800000000>, <133000000>;
+		};
+	};
 };
 
 &aips1 {
Signature · 1 line
2.51.0
#1 lore raw

-----Original Message-----
From: Rob Herring (Arm) <[email protected]>
Sent: Saturday, March 7, 2026 4:31 AM
To: Forrest Shi <[email protected]>; Peng Fan (OSS) <[email protected]>; Krzysztof Kozlowski <[email protected]>; Conor Dooley <[email protected]>; Frank Li <[email protected]>; Sascha Hauer <[email protected]>; Pengutronix Kernel Team <[email protected]>; Fabio Estevam <[email protected]>
Cc: Peter Robinson <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]
Subject: [EXT] [PATCH v2] arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes

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i.MX93 contains an Arm Ethos-U65 NPU. The NPU uses the internal SRAM for temporary buffers. The SRAM is larger than 96KB, but that is all that is available to non-secure world.

Signed-off-by Rob Herring (Arm) <[email protected]>

---
v2:
- Increase the APB freq to 133MHz

---
 arch/arm64/boot/dts/freescale/imx93.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
arch/arm64/boot/dts/freescale/imx93.dtsi +4 -0
index 7b27012dfcb5..95cc60158349 100644
@@ -43,6 +43,29 @@ map0 {
                        };
                };
        };
+
+       sram: sram@20480000 {
+               compatible = "mmio-sram";
+               reg = <0x0 0x20480000 0x0 0x18000>;

[Forrest Shi] should it be 0x60000, 384KB? From NXP imx93 reference manual, there is one dedicated OCRAM for ethosu usage.
And this area is managed and accessed only by ethosu via command stream.

+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x0 0x20480000 0x18000>;

[Forrest Shi] same as above, 384KB?
+ };
+
+ soc@0 {
+ npu@4a900000 {

+                       compatible = "fsl,imx93-npu", "arm,ethos-u65";
+                       reg = <0x4a900000 0x1000>;
+                       interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+                       power-domains = <&mlmix>;
+                       clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+                       clock-names = "core", "apb";
+                       sram = <&sram>;
+                       assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+                       assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+                       assigned-clock-rates = <800000000>, <133000000>;

+ };
+ };
};

&aips1 {
--
2.51.0

Reviewed-by Tested-by on v2 1/1
#2 lore raw
In reply to Rob Herring (Arm)
Quoted 6 lines · Rob Herring (Arm)

i.MX93 contains an Arm Ethos-U65 NPU. The NPU uses the internal SRAM for temporary buffers. The SRAM is larger than 96KB, but that is all that is available to non-secure world.

Signed-off-by Rob Herring (Arm) <[email protected]>
Reviewed-by Peter Robinson <[email protected]>
Tested-by Peter Robinson <[email protected]> # Tested on a NXP

i.MX93 11X11 FRDM board

Quoted 44 lines

---
v2:
- Increase the APB freq to 133MHz

---
 arch/arm64/boot/dts/freescale/imx93.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
arch/arm64/boot/dts/freescale/imx93.dtsi +23 -1
index 7b27012dfcb5..95cc60158349 100644
@@ -43,6 +43,29 @@ map0 {
                        };
                };
        };
+
+       sram: sram@20480000 {
+               compatible = "mmio-sram";
+               reg = <0x0 0x20480000 0x0 0x18000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x0 0x20480000 0x18000>;
+       };
+
+       soc@0 {
+               npu@4a900000 {
+                       compatible = "fsl,imx93-npu", "arm,ethos-u65";
+                       reg = <0x4a900000 0x1000>;
+                       interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+                       power-domains = <&mlmix>;
+                       clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+                       clock-names = "core", "apb";
+                       sram = <&sram>;
+                       assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+                       assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+                       assigned-clock-rates = <800000000>, <133000000>;
+               };
+       };
 };
 
 &aips1 {
--

2.51.0

maintainer Applied
#3 lore raw
In reply to Rob Herring (Arm)
Quoted 5 lines · Rob Herring (Arm)

i.MX93 contains an Arm Ethos-U65 NPU. The NPU uses the internal SRAM for temporary buffers. The SRAM is larger than 96KB, but that is all that is available to non-secure world.

Applied, thanks!

[1/1] arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes

      commit: c95a5c0b55664ff938371b058673f294ce01fe1b

Move sram@20480000 node after soc@0 because keep order by address Fix line assigned-clock-parents to keep below 100 char to avoid checkpatch warning.

About sram size discussion, we can fix later.

Best regards,
--
Frank Li <[email protected]>