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cpu/mips/cpu.c: Fix flush_cache bug

U-Boot-Users Applied Shinya Kuribayashi 2 participants 2 messages Apr 8, 2008 – Apr 18, 2008

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Shinya Kuribayashi

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#0 lore raw

Cache operations have to take line address (addr), not start_addr. I noticed this bug when debugging ping failure.

Signed-off-by Shinya Kuribayashi <[email protected]>

---

 cpu/mips/cpu.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
cpu/mips/cpu.c +2 -2
index 8b43d8e..e267bba 100644
@@ -56,8 +56,8 @@ void flush_cache(ulong start_addr, ulong size)
 	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
 
 	while (1) {
-		cache_op(Hit_Writeback_Inv_D, start_addr);
-		cache_op(Hit_Invalidate_I, start_addr);
+		cache_op(Hit_Writeback_Inv_D, addr);
+		cache_op(Hit_Invalidate_I, addr);
 		if (addr == aend)
 			break;
 		addr += lsize;
Applied
#1 lore raw
Quoted 8 lines · In message <[email protected]> you wrote:

Cache operations have to take line address (addr), not start_addr. I noticed this bug when debugging ping failure.

Signed-off-by Shinya Kuribayashi <[email protected]>

---

 cpu/mips/cpu.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

Signature · 6 lines
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