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ARM: OMAP3: Check for L2 cache enabled

PATCH Superseded Dirk Behme 2 participants 2 messages May 10, 2008

Subsystems (3)
Arm (32-bit) Arm sub-architectures OMAP2+ support

v2 of 3 Superseded Latest is v3 →

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Dirk Behme

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#0 lore raw

PATCH v2 1/1 ARM: OMAP3: Check for L2 cache enabled

Enabling L2 cache of Cortex-A8 based OMAP3 has to be done by bootloader. Check if this is done and warn if not.

Signed-off-by Dirk Behme <[email protected]>

----

Changes in v2: Fix a typo.

arch/arm/mach-omap2/id.c +23 -0
Index: linux-beagle/arch/arm/mach-omap2/id.c
===================================================================
@@ -267,3 +267,26 @@ void __init omap2_check_revision(void)
 
 }
 
+#ifdef CONFIG_ARCH_OMAP3
+/*
+ * OMAP3 has L2 cache which has to be enabled by bootloader.
+ */
+static int __init omap3_check_l2cache(void)
+{
+	u32 val;
+
+	/* Get CP15 AUX register, bit 1 enabled indicates L2 cache is on */
+	asm volatile("mrc p15, 0, %0, c1, c0, 1":"=r" (val));
+
+	if ((val & 0x2) == 0) {
+		printk(KERN_WARNING "Warning: L2 cache not enabled. Check "
+		       "your bootloader. L2 off results in performance loss\n");
+	} else {
+		pr_info("OMAP3 L2 cache enabled");
+	}
+
+	return 0;
+}
+
+arch_initcall(omap3_check_l2cache);
+#endif /* CONFIG_ARCH_OMAP3 */
#1 lore raw
Quoted 20 lines · Dirk Behme

Enabling L2 cache of Cortex-A8 based OMAP3 has to be done by bootloader. Check if this is done and warn if not.

Signed-off-by Dirk Behme <[email protected]>

----

Changes in v2: Fix a typo.

Index: linux-beagle/arch/arm/mach-omap2/id.c
===================================================================

arch/arm/mach-omap2/id.c +2 -0
@@ -267,3 +267,26 @@ void __init omap2_check_revision(void)
 
 }
 
+#ifdef CONFIG_ARCH_OMAP3
+/*

arch/arm/mach-omap2/id.c void __init omap2_check_revision(void) · line 281

Quoted 10 lines
arch/arm/mach-omap2/id.c +10 -0
+ * OMAP3 has L2 cache which has to be enabled by bootloader.
+ */
+static int __init omap3_check_l2cache(void)
+{
+	u32 val;
+
+	/* Get CP15 AUX register, bit 1 enabled indicates L2 cache is on */
+	asm volatile("mrc p15, 0, %0, c1, c0, 1":"=r" (val));
+
+	if ((val & 0x2) == 0) {

The {} are unneeded here.

arch/arm/mach-omap2/id.c void __init omap2_check_revision(void) · line 284

Quoted 3 lines
arch/arm/mach-omap2/id.c +3 -0
+		printk(KERN_WARNING "Warning: L2 cache not enabled. Check "
+		       "your bootloader. L2 off results in performance loss\n");
+	} else {

same here.

Quoted 8 lines
arch/arm/mach-omap2/id.c +8 -0
+		pr_info("OMAP3 L2 cache enabled");
+	}
+
+	return 0;
+}
+
+arch_initcall(omap3_check_l2cache);
+#endif /* CONFIG_ARCH_OMAP3 */
Signature · 5 lines
Best Regards,

Felipe Balbi
[email protected]
http://blog.felipebalbi.com