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dmaengine: sh: Add Support SuperH DMA Engine driver

PATCH Superseded Nobuhiro Iwamatsu 3 participants 4 messages Apr 14, 2009 – May 12, 2009

Subsystems (2)
SuperH dmaengine

v5 of 7 Superseded Latest is v7 →

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Nobuhiro Iwamatsu

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PATCH v5 1/1 dmaengine: sh: Add Support SuperH DMA Engine driver

This supported all DMA channels, and it was tested in SH7722, SH7780 and SH7763.
This can not use with SH DMA API.

Signed-off-by Nobuhiro Iwamatsu <[email protected]>
Reviewed-by Matt Fleming <[email protected]>
Reviewed-by Dan Williams <[email protected]>
Acked-by Maciej Sosnowski <[email protected]>

---
v5: Fix some bug.
Add Cyclic extention API (got hint from dw_dmac.c)

 arch/sh/drivers/dma/Kconfig  |   12 +-
 arch/sh/drivers/dma/Makefile |    3 +-
 arch/sh/include/asm/dma-sh.h |   21 +
 drivers/dma/Kconfig          |    8 +
 drivers/dma/Makefile         |    2 +
 drivers/dma/shdma.c          | 1019 ++++++++++++++++++++++++++++++++++++++++++
 drivers/dma/shdma.h          |   82 ++++
 7 files changed, 1142 insertions(+), 5 deletions(-)
 create mode 100644 drivers/dma/shdma.c
 create mode 100644 drivers/dma/shdma.h
arch/sh/drivers/dma/Kconfig +9 -3
index 666713a..63dbf43 100644
@@ -1,12 +1,9 @@
 menu "DMA support"
 
-config SH_DMA_API
-	bool
 
 config SH_DMA
 	bool "SuperH on-chip DMA controller (DMAC) support"
 	depends on CPU_SH3 || CPU_SH4
-	select SH_DMA_API
 	default n
 
 config SH_DMA_IRQ_MULTI

@@ -18,6 +15,15 @@ config SH_DMA_IRQ_MULTI
 		     CPU_SUBTYPE_SH7763  || CPU_SUBTYPE_SH7764  || \
 		     CPU_SUBTYPE_SH7780  || CPU_SUBTYPE_SH7785
 
+config SH_DMA_API
+	depends on SH_DMA
+	bool "SuperH DMA API support"
+	default n
+	help
+	  SH_DMA_API always enabled DMA API of used SuperH.
+	  If you want to use DMA ENGINE, you must not enable this.
+	  Please enable DMA_ENGINE and SH_DMAE.
+
 config NR_ONCHIP_DMA_CHANNELS
 	int
 	depends on SH_DMA
arch/sh/drivers/dma/Makefile +1 -2
index c606813..d88c948 100644
@@ -2,8 +2,7 @@
 # Makefile for the SuperH DMA specific kernel interface routines under Linux.
 #
 
-obj-$(CONFIG_SH_DMA_API)	+= dma-api.o dma-sysfs.o
-obj-$(CONFIG_SH_DMA)		+= dma-sh.o
+obj-$(CONFIG_SH_DMA_API)	+= dma-sh.o dma-api.o dma-sysfs.o
 obj-$(CONFIG_PVR2_DMA)		+= dma-pvr2.o
 obj-$(CONFIG_G2_DMA)		+= dma-g2.o
 obj-$(CONFIG_SH_DMABRG)		+= dmabrg.o
arch/sh/include/asm/dma-sh.h +21 -0
index 0c8f8e1..d77e2d5 100644
@@ -115,4 +115,25 @@ static u32 dma_base_addr[] __maybe_unused = {
 #define CHCR    0x0C
 #define DMAOR	0x40
 
+/*
+ * for dma engine
+ *
+ * SuperH DMA mode
+ */
+#include <linux/dmaengine.h>
+#define SHDMA_MIX_IRQ	(1 << 1)
+#define SHDMA_DMAOR1	(1 << 2)
+#define SHDMA_DMAE1		(1 << 3)
+
+struct sh_dmae_pdata {
+	unsigned int mode;
+};
+
+int sh_dmae_cyclic_prep(struct dma_chan *chan,
+	dma_addr_t src_addr, dma_addr_t dst_addr, size_t buf_len,
+	size_t period_len, enum dma_data_direction direction);
+int sh_dmae_cyclic_free(struct dma_chan *chan);
+int sh_dmae_cyclic_start(struct dma_chan *chan);
+int sh_dmae_cyclic_stop(struct dma_chan *chan);
+
 #endif /* __DMA_SH_H */
drivers/dma/Kconfig +8 -0
index 3b3c01b..0a27f3c 100644
@@ -81,6 +81,14 @@ config MX3_IPU_IRQS
 	  To avoid bloating the irq_desc[] array we allocate a sufficient
 	  number of IRQ slots and map them dynamically to specific sources.
 
+config SH_DMAE
+	tristate "Renesas SuperH DMAC support"
+	depends on SUPERH && SH_DMA
+	depends on !SH_DMA_API
+	select DMA_ENGINE
+	help
+	  Enable support for the Renesas SuperH DMA controllers.
+
 config DMA_ENGINE
 	bool
drivers/dma/Makefile +2 -0
index 2e5dc96..0d2f3e9 100644
@@ -8,3 +8,5 @@ obj-$(CONFIG_FSL_DMA) += fsldma.o
 obj-$(CONFIG_MV_XOR) += mv_xor.o
 obj-$(CONFIG_DW_DMAC) += dw_dmac.o
 obj-$(CONFIG_MX3_IPU) += ipu/
+obj-$(CONFIG_SH_DMAE) += shdma.o
+
drivers/dma/shdma.c new file +1017 -0

1,017 lines not on this page · raw message

drivers/dma/shdma.h new file +82 -0

82 lines not on this page · raw message

Signature · 1 line
1.6.2.2
#1 lore raw
Quoted 4 lines · Nobuhiro Iwamatsu

This supported all DMA channels, and it was tested in SH7722, SH7780 and SH7763.
This can not use with SH DMA API.

Quoted 8 lines
Signed-off-by Nobuhiro Iwamatsu <[email protected]>
Reviewed-by Matt Fleming <[email protected]>
Reviewed-by Dan Williams <[email protected]>
Acked-by Maciej Sosnowski <[email protected]>

---
v5: Fix some bug.
Add Cyclic extention API (got hint from dw_dmac.c)

I didn't see any comment from Dan on the last version. Dan?

#2 lore raw
In reply to Nobuhiro Iwamatsu
Quoted 11 lines · Nobuhiro Iwamatsu

This supported all DMA channels, and it was tested in SH7722, SH7780 and SH7763.
This can not use with SH DMA API.

Signed-off-by Nobuhiro Iwamatsu <[email protected]>
Reviewed-by Matt Fleming <[email protected]>
Reviewed-by Dan Williams <[email protected]>
Acked-by Maciej Sosnowski <[email protected]>

---
v5: Fix some bug.
Add Cyclic extention API (got hint from dw_dmac.c)

Have you run this with CONFIG_PROVE_LOCKING=y? I suspect it will find some issues. It looks like desc_lock in the interrupt handler is only protecting updates to the CHCR register. In other places desc_lock is protecting descriptor chain updates. And the code varies from spin_lock to spin_lock_bh? If you can't move all register manipulations to bh or process context then you will most likely need a separate register_lock which can be taken with spin_lock_irq... see what CONFIG_PROVE_LOCKING reports.

Quoted 9 lines
drivers/dma/Kconfig +1 -0
index 3b3c01b..0a27f3c 100644
@@ -81,6 +81,14 @@ config MX3_IPU_IRQS
          To avoid bloating the irq_desc[] array we allocate a sufficient
          number of IRQ slots and map them dynamically to specific sources.
 
+config SH_DMAE

drivers/dma/Kconfig config MX3_IPU_IRQS · line 94

Quoted 10 lines
drivers/dma/Kconfig +7 -0
+       tristate "Renesas SuperH DMAC support"
+       depends on SUPERH && SH_DMA
+       depends on !SH_DMA_API
+       select DMA_ENGINE
+       help
+         Enable support for the Renesas SuperH DMA controllers.
+
 config DMA_ENGINE
        bool

This will collide with the TXX9_DMAC config option now sitting in Ralf's tree. Please put this entry somewhere before MX3_IPU.

Regards,
Dan

author
#3 lore raw
In reply to Nobuhiro Iwamatsu

Hi, Dan.

Thank you for your check.

Quoted 13 lines · Dan Williams
Quoted 11 lines · Nobuhiro Iwamatsu

This supported all DMA channels, and it was tested in SH7722, SH7780 and SH7763.
This can not use with SH DMA API.

Signed-off-by Nobuhiro Iwamatsu <[email protected]>
Reviewed-by Matt Fleming <[email protected]>
Reviewed-by Dan Williams <[email protected]>
Acked-by Maciej Sosnowski <[email protected]>

---
v5: Fix some bug.
Add Cyclic extention API (got hint from dw_dmac.c)

Quoted 8 lines

Have you run this with CONFIG_PROVE_LOCKING=y? I suspect it will find some issues. It looks like desc_lock in the interrupt handler is only protecting updates to the CHCR register. In other places desc_lock is protecting descriptor chain updates. And the code varies from spin_lock to spin_lock_bh? If you can't move all register manipulations to bh or process context then you will most likely need a separate register_lock which can be taken with spin_lock_irq... see what CONFIG_PROVE_LOCKING reports.

OK, I check this point, and send report.

Quoted 10 lines
Quoted 10 lines
drivers/dma/Kconfig +0 -0
index 3b3c01b..0a27f3c 100644
@@ -81,6 +81,14 @@ config MX3_IPU_IRQS
          To avoid bloating the irq_desc[] array we allocate a sufficient
          number of IRQ slots and map them dynamically to specific

sources.

Quoted 14 lines

drivers/dma/Kconfig config MX3_IPU_IRQS · line 93

Quoted 11 lines
drivers/dma/Kconfig +8 -0
+config SH_DMAE
+       tristate "Renesas SuperH DMAC support"
+       depends on SUPERH && SH_DMA
+       depends on !SH_DMA_API
+       select DMA_ENGINE
+       help
+         Enable support for the Renesas SuperH DMA controllers.
+
 config DMA_ENGINE
        bool

This will collide with the TXX9_DMAC config option now sitting in Ralf's tree. Please put this entry somewhere before MX3_IPU.

OK, I fix this next patch.

Best regards,
Nobuhiro