PCI:Add SPEAr13xx PCie support
Subsystems (7)
cover PCI:Add SPEAr13xx PCie support
First five patches are improvement and fixes for SPEAr13xx support.
Next three patches improves pcie designware driver and fixes the IO translation bug. IO translation bug fix leads to the working of PCIe EP devices connected to RC through switch.
PCIe driver support for SPEAr1310/40 platform board is added.
These patches are tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Mohit Kumar (4):
SPEAr13xx: Correct dt field name for stmmac phy-addr
SPEAr13xx: defconfig: Update
MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
MAINTAINERS: Add Synopsis Designware PCIe driver maintainer
Pratyush Anand (8):
SPEAr13xx: Move SPEAr1340 definitions to header file
SPEAr13xx: Add SPEAr1310 PCIe register definitions
SPEAr13xx: Fix static mapping table
clk: SPEAr13xx: Fix pcie clock name
pcie: designware: Move register definition to the header file
pcie: designware: add dw_pcie prefix before cfg_read/write
pcie: designware: Fix IO transfers
pcie: SPEAr13xx: Add designware pcie support
MAINTAINERS | 13 + arch/arm/boot/dts/spear13xx.dtsi | 55 +++- arch/arm/configs/spear13xx_defconfig | 15 + arch/arm/mach-spear/Kconfig | 1 + arch/arm/mach-spear/include/mach/spear.h | 132 +++++++- arch/arm/mach-spear/spear1340.c | 54 --- arch/arm/mach-spear/spear13xx.c | 2 +- drivers/clk/spear/spear1310_clock.c | 6 +- drivers/clk/spear/spear1340_clock.c | 2 +- drivers/pci/host/Kconfig | 5 + drivers/pci/host/Makefile | 2 + drivers/pci/host/pci-exynos.c | 5 +- drivers/pci/host/pcie-designware.c | 70 +--- drivers/pci/host/pcie-designware.h | 46 +++- drivers/pci/host/pcie-spear13xx.c | 564 ++++++++++++++++++++++++++++++ 15 files changed, 850 insertions(+), 122 deletions(-) create mode 100644 drivers/pci/host/pcie-spear13xx.c
PATCH 1/12 SPEAr13xx: Correct dt field name for stmmac phy-addr
DT field name for the phy address changed since kernel 3.10. Set the snps,phy-addr to 0xffffffff so that the driver probes for the phy.
--- arch/arm/boot/dts/spear13xx.dtsi | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
arch/arm/boot/dts/spear13xx.dtsi +1 -0
@@ -155,6 +155,7 @@ gmac0: eth at e2000000 { compatible = "st,spear600-gmac"; + snps,phy-addr = <0xffffffff>; reg = <0xe2000000 0x8000>; interrupts = <0 33 0x4 0 34 0x4>;
Signature · 1 line
1.7.0.1
PATCH 2/12 SPEAr13xx: Move SPEAr1340 definitions to header file
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
Move SPEAr1340 definitions to header files so that theese can be used by other code too.
--- arch/arm/mach-spear/include/mach/spear.h | 55 ++++++++++++++++++++++++++++++ arch/arm/mach-spear/spear1340.c | 54 ----------------------------- 2 files changed, 55 insertions(+), 54 deletions(-)
arch/arm/mach-spear/include/mach/spear.h +55 -0
@@ -86,6 +86,61 @@/* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE UART_BASE +/* PCIe/SATA Base addresses */ +#define SPEAR1340_SATA_BASE UL(0xB1000000) +#define SPEAR1340_PCIE_BASE UL(0xB1000000) + +/* Power Management Registers */ +#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100) +#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104) +#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108) + +#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318) +#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C) +#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320) + +/* PCIE - SATA configuration registers */ +#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424) +/* PCIE CFG MASks */ +#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11) +#define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10) +#define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9) +#define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8) +#define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4) +#define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3) +#define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2) +#define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1) +#define SPEAR1340_PCIE_SATA_SEL_PCIE (0) +#define SPEAR1340_PCIE_SATA_SEL_SATA (1) +#define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F +#define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \ + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \ + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \ + SPEAR1340_PCIE_CFG_POWERUP_RESET | \ + SPEAR1340_PCIE_CFG_DEVICE_PRESENT) +#define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \ + SPEAR1340_SATA_CFG_PM_CLK_EN | \ + SPEAR1340_SATA_CFG_POWERUP_RESET | \ + SPEAR1340_SATA_CFG_RX_CLK_EN | \ + SPEAR1340_SATA_CFG_TX_CLK_EN) + +#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428) +#define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31) +#define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27) +#define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27) +#define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27) +#define SPEAR1340_MIPHY_PLL_RATIO_TOP (x) (x << 0) +#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \ + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ + SPEAR1340_MIPHY_CLK_REF_DIV2 | \ + SPEAR1340_MIPHY_PLL_RATIO_TOP(60)) +#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \ + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120)) +#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \ + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ + SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) + +#endif /* SPEAR13XX */ #endif /* __MACH_SPEAR_H */
arch/arm/mach-spear/spear1340.c +0 -54
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1.7.0.1
PATCH 3/12 SPEAr13xx: Add SPEAr1310 PCIe register definitions
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
Add SPEAr1310 Misc register definitions for PCIe.
--- arch/arm/mach-spear/include/mach/spear.h | 73 ++++++++++++++++++++++++++++++ 1 files changed, 73 insertions(+), 0 deletions(-)
arch/arm/mach-spear/include/mach/spear.h +73 -0
@@ -140,6 +140,79 @@ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) +#define VA_SPEAR1310_PCIE_SATA_CFG (VA_MISC_BASE + 0x3A4) +#define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31) +#define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30) +#define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29) +#define SPEAR1310_PCIE_SATA2_SEL_SATA (1 << 31) +#define SPEAR1310_PCIE_SATA1_SEL_SATA (1 << 30) +#define SPEAR1310_PCIE_SATA0_SEL_SATA (1 << 29) +#define SPEAR1310_SATA2_CFG_TX_CLK_EN (1 << 27) +#define SPEAR1310_SATA2_CFG_RX_CLK_EN (1 << 26) +#define SPEAR1310_SATA2_CFG_POWERUP_RESET (1 << 25) +#define SPEAR1310_SATA2_CFG_PM_CLK_EN (1 << 24) +#define SPEAR1310_SATA1_CFG_TX_CLK_EN (1 << 23) +#define SPEAR1310_SATA1_CFG_RX_CLK_EN (1 << 22) +#define SPEAR1310_SATA1_CFG_POWERUP_RESET (1 << 21) +#define SPEAR1310_SATA1_CFG_PM_CLK_EN (1 << 20) +#define SPEAR1310_SATA0_CFG_TX_CLK_EN (1 << 19) +#define SPEAR1310_SATA0_CFG_RX_CLK_EN (1 << 18) +#define SPEAR1310_SATA0_CFG_POWERUP_RESET (1 << 17) +#define SPEAR1310_SATA0_CFG_PM_CLK_EN (1 << 16) +#define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT (1 << 11) +#define SPEAR1310_PCIE2_CFG_POWERUP_RESET (1 << 10) +#define SPEAR1310_PCIE2_CFG_CORE_CLK_EN (1 << 9) +#define SPEAR1310_PCIE2_CFG_AUX_CLK_EN (1 << 8) +#define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT (1 << 7) +#define SPEAR1310_PCIE1_CFG_POWERUP_RESET (1 << 6) +#define SPEAR1310_PCIE1_CFG_CORE_CLK_EN (1 << 5) +#define SPEAR1310_PCIE1_CFG_AUX_CLK_EN (1 << 4) +#define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT (1 << 3) +#define SPEAR1310_PCIE0_CFG_POWERUP_RESET (1 << 2) +#define SPEAR1310_PCIE0_CFG_CORE_CLK_EN (1 << 1) +#define SPEAR1310_PCIE0_CFG_AUX_CLK_EN (1 << 0) + +#define SPEAR1310_PCIE_CFG_MASK (x) ((0xF << (x * 4)) | (1 << (x + 29))) +#define SPEAR1310_SATA_CFG_MASK (x) ((0xF << (x * 4 + 16)) | \ + (1 << (x + 29))) +#define SPEAR1310_PCIE_CFG_VAL (x) \ + (SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \ + SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \ + SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \ + SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \ + SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT) +#define SPEAR1310_SATA_CFG_VAL (x) \ + (SPEAR1310_PCIE_SATA##x##_SEL_SATA | \ + SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \ + SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \ + SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \ + SPEAR1310_SATA##x##_CFG_TX_CLK_EN) + +#define VA_SPEAR1310_PCIE_MIPHY_CFG_1 (VA_MISC_BASE + 0x3A8) +#define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT (1 << 31) +#define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 (1 << 28) +#define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP (x) (x << 16) +#define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT (1 << 15) +#define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 (1 << 12) +#define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP (x) (x << 0) +#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF) +#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16) +#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \ + (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \ + SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \ + SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \ + SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \ + SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \ + SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60)) +#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \ + (SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120)) +#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \ + (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \ + SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \ + SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \ + SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25)) + +#define VA_SPEAR1310_PCIE_MIPHY_CFG_2 (VA_MISC_BASE + 0x3AC)#endif /* SPEAR13XX */
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1.7.0.1
PATCH 4/12 SPEAr13xx: Fix static mapping table
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr13xx was using virtual address space 0xFE000000 to map physical address space 0xB3000000. pci_remap_io uses 0xFEE00000 as virtual address. So change 0xFE000000 to 0xF9000000.
--- arch/arm/mach-spear/include/mach/spear.h | 4 ++-- arch/arm/mach-spear/spear13xx.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/mach-spear/include/mach/spear.h +2 -2
@@ -52,10 +52,10 @@#ifdef CONFIG_ARCH_SPEAR13XX #define PERIP_GRP2_BASE UL(0xB3000000) -#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) +#define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)#define MCIF_SDHCI_BASE UL(0xB3000000)#define SYSRAM0_BASE UL(0xB3800000) -#define VA_SYSRAM0_BASE IOMEM(0xFE800000) +#define VA_SYSRAM0_BASE IOMEM(0xF9800000)#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)#define PERIP_GRP1_BASE UL(0xE0000000)
arch/arm/mach-spear/spear13xx.c +1 -1
@@ -52,10 +52,10 @@ void __init spear13xx_l2x0_init(void)/* * Following will create 16MB static virtual/physical mappings * PHYSICAL VIRTUAL -* 0xB3000000 0xFE000000 * 0xE0000000 0xFD000000 * 0xEC000000 0xFC000000 * 0xED000000 0xFB000000 +* 0xB3000000 0xF9000000 */ struct map_desc spear13xx_io_desc[]__initdata = { {
Signature · 1 line
1.7.0.1
PATCH 5/12 clk: SPEAr13xx: Fix pcie clock name
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
Follow dt clock naming convention for PCIe clocks.
--- drivers/clk/spear/spear1310_clock.c | 6 +++--- drivers/clk/spear/spear1340_clock.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-)
drivers/clk/spear/spear1310_clock.c +3 -3
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) clk =clk_register_gate (NULL ,"pcie_sata_0_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_0_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.0" ); +clk_register_clkdev (clk,NULL ,"b1000000.pcie" );clk_register_clkdev (clk,NULL ,"b1000000.ahci" ); clk =clk_register_gate (NULL ,"pcie_sata_1_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_1_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.1" ); +clk_register_clkdev (clk,NULL ,"b1800000.pcie" );clk_register_clkdev (clk,NULL ,"b1800000.ahci" ); clk =clk_register_gate (NULL ,"pcie_sata_2_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_2_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.2" ); +clk_register_clkdev (clk,NULL ,"b4000000.pcie" );clk_register_clkdev (clk,NULL ,"b4000000.ahci" ); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
drivers/clk/spear/spear1340_clock.c +1 -1
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base) clk =clk_register_gate (NULL ,"pcie_sata_clk" ,"ahb_clk" ,0 ,SPEAR1340_PERIP1_CLK_ENB ,SPEAR1340_PCIE_SATA_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie" ); +clk_register_clkdev (clk,NULL ,"b1000000.pcie" );clk_register_clkdev (clk,NULL ,"b1000000.ahci" ); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
Signature · 1 line
1.7.0.1
PATCH 6/12 pcie: designware: Move register definition to the header file
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
Move synopsis specific register definition from source file to header file, so that they can be re-used by other files if needed.
--- drivers/pci/host/pcie-designware.c | 42 ------------------------------------ drivers/pci/host/pcie-designware.h | 42 ++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 42 deletions(-)
drivers/pci/host/pcie-designware.c +0 -42
@@ -23,48 +23,6 @@#include "pcie-designware.h" -/* Synopsis specific PCIE configuration registers */ -#define PCIE_PORT_LINK_CONTROL 0x710 -#define PORT_LINK_MODE_MASK (0x3f << 16) -#define PORT_LINK_MODE_1_LANES (0x1 << 16) -#define PORT_LINK_MODE_2_LANES (0x3 << 16) -#define PORT_LINK_MODE_4_LANES (0x7 << 16) - -#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C -#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) -#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) -#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) -#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) -#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) - -#define PCIE_MSI_ADDR_LO 0x820 -#define PCIE_MSI_ADDR_HI 0x824 -#define PCIE_MSI_INTR0_ENABLE 0x828 -#define PCIE_MSI_INTR0_MASK 0x82C -#define PCIE_MSI_INTR0_STATUS 0x830 - -#define PCIE_ATU_VIEWPORT 0x900 -#define PCIE_ATU_REGION_INBOUND (0x1 << 31) -#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) -#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) -#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) -#define PCIE_ATU_CR1 0x904 -#define PCIE_ATU_TYPE_MEM (0x0 << 0) -#define PCIE_ATU_TYPE_IO (0x2 << 0) -#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) -#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) -#define PCIE_ATU_CR2 0x908 -#define PCIE_ATU_ENABLE (0x1 << 31) -#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) -#define PCIE_ATU_LOWER_BASE 0x90C -#define PCIE_ATU_UPPER_BASE 0x910 -#define PCIE_ATU_LIMIT 0x914 -#define PCIE_ATU_LOWER_TARGET 0x918 -#define PCIE_ATU_BUS (x) (((x) & 0xff) << 24) -#define PCIE_ATU_DEV (x) (((x) & 0x1f) << 19) -#define PCIE_ATU_FUNC (x) (((x) & 0x7) << 16) -#define PCIE_ATU_UPPER_TARGET 0x91C -static struct hw_pci dw_pci;static unsigned long global_io_offset;
drivers/pci/host/pcie-designware.h +42 -0
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1.7.0.1
PATCH 7/12 pcie: designware: add dw_pcie prefix before cfg_read/write
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
cfg_read/write function are designware pcie specific. Add dw_pcie prefix to avoid collision in global name space.
--- drivers/pci/host/pci-exynos.c | 5 +++-- drivers/pci/host/pcie-designware.c | 23 ++++++++++++++--------- drivers/pci/host/pcie-designware.h | 4 ++-- 3 files changed, 19 insertions(+), 13 deletions(-)
drivers/pci/host/pci-exynos.c +3 -2
@@ -468,7 +468,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,int ret;exynos_pcie_sideband_dbi_r_mode (pp, true); - ret =cfg_read (pp->dbi_base + (where & ~0x3 ), where, size, val); + ret =dw_pcie_cfg_read (pp->dbi_base + (where & ~0x3 ), where, size, val);exynos_pcie_sideband_dbi_r_mode (pp, false);return ret; }
@@ -479,7 +479,8 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,int ret;exynos_pcie_sideband_dbi_w_mode (pp, true); - ret =cfg_write (pp->dbi_base + (where & ~0x3 ), where, size, val); + ret =dw_pcie_cfg_write (pp->dbi_base + (where & ~0x3 ), + where, size, val);exynos_pcie_sideband_dbi_w_mode (pp, false);return ret; }
drivers/pci/host/pcie-designware.c +14 -9
@@ -32,7 +32,7 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)return sys->private_data; } -int cfg_read (void __iomem *addr,int where,int size,u32 *val) +int dw_pcie_cfg_read (void __iomem *addr,int where,int size,u32 *val) { *val =readl (addr);
@@ -46,7 +46,7 @@ int cfg_read(void __iomem *addr, int where, int size, u32 *val)return PCIBIOS_SUCCESSFUL ; } -int cfg_write (void __iomem *addr,int where,int size,u32 val) +int dw_pcie_cfg_write (void __iomem *addr,int where,int size,u32 val) {if (size ==4 )writel (val, addr);
@@ -84,7 +84,8 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,if (pp->ops->rd_own_conf) ret = pp->ops->rd_own_conf (pp, where, size, val);else - ret =cfg_read (pp->dbi_base + (where & ~0x3 ), where, size, val); + ret =dw_pcie_cfg_read (pp->dbi_base + (where & ~0x3 ), where, + size, val);return ret; }
@@ -97,8 +98,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,if (pp->ops->wr_own_conf) ret = pp->ops->wr_own_conf (pp, where, size, val);else - ret =cfg_write (pp->dbi_base + (where & ~0x3 ), where, size, - val); + ret =dw_pcie_cfg_write (pp->dbi_base + (where & ~0x3 ), where, + size, val);return ret; }
@@ -534,11 +535,13 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,if (bus->parent->number == pp->root_bus_nr) {dw_pcie_prog_viewport_cfg0 (pp, busdev); - ret =cfg_read (pp->va_cfg0_base + address, where, size, val); + ret =dw_pcie_cfg_read (pp->va_cfg0_base + address, where, size, + val);dw_pcie_prog_viewport_mem_outbound (pp); }else {dw_pcie_prog_viewport_cfg1 (pp, busdev); - ret =cfg_read (pp->va_cfg1_base + address, where, size, val); + ret =dw_pcie_cfg_read (pp->va_cfg1_base + address, where, size, + val);dw_pcie_prog_viewport_io_outbound (pp); }
@@ -557,11 +560,13 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,if (bus->parent->number == pp->root_bus_nr) {dw_pcie_prog_viewport_cfg0 (pp, busdev); - ret =cfg_write (pp->va_cfg0_base + address, where, size, val); + ret =dw_pcie_cfg_write (pp->va_cfg0_base + address, where, size, + val);dw_pcie_prog_viewport_mem_outbound (pp); }else {dw_pcie_prog_viewport_cfg1 (pp, busdev); - ret =cfg_write (pp->va_cfg1_base + address, where, size, val); + ret =dw_pcie_cfg_write (pp->va_cfg1_base + address, where, size, + val);dw_pcie_prog_viewport_io_outbound (pp); }
drivers/pci/host/pcie-designware.h +2 -2
@@ -66,8 +66,8 @@ struct pcie_host_ops {void (*host_init)(struct pcie_port *pp); }; -int cfg_read (void __iomem *addr,int where,int size,u32 *val); -int cfg_write (void __iomem *addr,int where,int size,u32 val); +int dw_pcie_cfg_read (void __iomem *addr,int where,int size,u32 *val); +int dw_pcie_cfg_write (void __iomem *addr,int where,int size,u32 val);void dw_handle_msi_irq (struct pcie_port *pp);void dw_pcie_msi_init (struct pcie_port *pp);int dw_pcie_link_up (struct pcie_port *pp);
Signature · 1 line
1.7.0.1
PATCH 8/12 pcie: designware: Fix IO transfers
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
pp->io_base which is the input of the outbound IO address translation unit should be the cpu address, it was programmed wrongly to realio address.
We should pass global_io_offset rather than sys->io_offset to pci_ioremap_io, so we map the new window into the first available spot in the Linux view of the I/O space.
We must also pass cpu address instead of realio address to pci_ioremap_io.
This patch fixes above issue. It has been tested with Lecroy PTC in AIC mode and Pericom PI7C9X2G303EL PCIe switch, which does not work otherwise.
--- drivers/pci/host/pcie-designware.c | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-)
drivers/pci/host/pcie-designware.c +2 -3
@@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp) + global_io_offset); pp->config.io_size =resource_size (&pp->io); pp->config.io_bus_addr = range.pci_addr; + pp->io_base = range.cpu_addr; }if (restype ==IORESOURCE_MEM ) {of_pci_range_to_resource (&range, np, &pp->mem);
@@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) pp->cfg0_base = pp->cfg.start; pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size; - pp->io_base = pp->io.start; pp->mem_base = pp->mem.start; pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
@@ -573,7 +573,6 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,return ret; } -static int dw_pcie_valid_config (struct pcie_port *pp,struct pci_bus *bus,int dev) {
@@ -667,7 +666,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)if (global_io_offset <SZ_1M && pp->config.io_size >0 ) { sys->io_offset = global_io_offset - pp->config.io_bus_addr; -pci_ioremap_io (sys->io_offset, pp->io.start); +pci_ioremap_io (global_io_offset, pp->io_base); global_io_offset +=SZ_64K ;pci_add_resource_offset (&sys->resources, &pp->io, sys->io_offset);
Signature · 1 line
1.7.0.1
PATCH 9/12 pcie: SPEAr13xx: Add designware pcie support
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add SPEAr13xx PCIe driver based on designware controller driver.
SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works for ahci mode.
To use these patches on SPEAr1340/1310 evaluation board, do the necessary modifications on board and enable (okay) pcie from respective evb dtsi file.
--- arch/arm/boot/dts/spear13xx.dtsi | 54 ++++- arch/arm/mach-spear/Kconfig | 1 + drivers/pci/host/Kconfig | 5 + drivers/pci/host/Makefile | 2 + drivers/pci/host/pcie-spear13xx.c | 564 +++++++++++++++++++++++++++++++++++++ 5 files changed, 623 insertions(+), 3 deletions(-) create mode 100644 drivers/pci/host/pcie-spear13xx.c
arch/arm/boot/dts/spear13xx.dtsi +51 -3
@@ -83,8 +83,8 @@ #size-cells = <1>; compatible = "simple-bus"; ranges = <0x50000000 0x50000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x02000000 + 0x80000000 0x80000000 0x20000000 + 0xb0000000 0xb0000000 0x22000000 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>;
@@ -210,7 +210,54 @@ usbh1_id = <1>; status = "disabled"; }; - + pcie at b1000000 { + compatible = "st,spear13xx-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000 + 0xeb800000 0x1000>; + interrupts = <0 68 0x4>; + pcie_id = <0>; + pcie_is_gen1 = <0>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + pcie at b1800000 { + compatible = "st,spear13xx-pcie", "snps,dw-pcie"; + reg = <0xb1800000 0x4000 + 0xeb804000 0x1000>; + interrupts = <0 69 0x4>; + pcie_id = <1>; + pcie_is_gen1 = <0>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + pcie at b4000000 { + compatible = "st,spear13xx-pcie", "snps,dw-pcie"; + reg = <0xb4000000 0x4000 + 0xeb808000 0x1000>; + interrupts = <0 70 0x4>; + pcie_id = <2>; + pcie_is_gen1 = <0>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; apb { #address-cells = <1>; #size-cells = <1>;
@@ -334,6 +381,7 @@ reg = <0xe07008c4 0x4>; thermal_flags = <0x7000>; }; + }; }; };
arch/arm/mach-spear/Kconfig +1 -0
@@ -26,6 +26,7 @@ config ARCH_SPEAR13XX select MIGHT_HAVE_CACHE_L2X0 select PINCTRL select USE_OF + select PCI help Supports for ARM's SPEAR13XX family
drivers/pci/host/Kconfig +5 -0
@@ -33,4 +33,9 @@ config PCI_RCAR_GEN2 There are 3 internal PCI controllers available with a single built-in EHCI/OHCI host controller present on each one. +config PCIE_SPEAR13XX + bool "STMicroelectronics SPEAr PCIe controller" + depends on ARCH_SPEAR13XX + select PCIEPORTBUS + select PCIE_DW endmenu
drivers/pci/host/Makefile +2 -0
@@ -4,3 +4,5 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o +ccflags-$(CONFIG_PCIE_SPEAR13XX) := -Iarch/arm/mach-spear/include/ +obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
drivers/pci/host/pcie-spear13xx.c new file +564 -0
564 lines not on this page · raw message
Signature · 1 line
1.7.0.1
PATCH 10/12 SPEAr13xx: defconfig: Update
In reply to Mohit KumarEnable EABI, OEABI, VFP and NFS configs in default configuration file for SPEAr13xx.
Enable PCIe support for SPEAr13xx.
--- arch/arm/configs/spear13xx_defconfig | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-)
arch/arm/configs/spear13xx_defconfig +15 -0
@@ -11,13 +11,24 @@ CONFIG_ARCH_SPEAR13XX=y CONFIG_MACH_SPEAR1310=y CONFIG_MACH_SPEAR1340=y # CONFIG_SWP_EMULATE is not set +CONFIG_PCI_MSI=y +CONFIG_PCIE_SPEAR13XX=y CONFIG_SMP=y # CONFIG_SMP_ON_UP is not set # CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_VFP=y CONFIG_BINFMT_MISC=y CONFIG_NET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_OF_PARTS=y
@@ -27,6 +38,7 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_SD=y CONFIG_ATA=y # CONFIG_SATA_PMP is not set CONFIG_SATA_AHCI_PLATFORM=y
@@ -66,6 +78,7 @@ CONFIG_USB=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SPEAR=y
@@ -84,6 +97,8 @@ CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m
Signature · 1 line
1.7.0.1
PATCH 11/12 MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
In reply to Mohit KumarAdd Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.
--- MAINTAINERS | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)
MAINTAINERS +6 -0
@@ -6462,6 +6462,12 @@ L: linux-pci at vger.kernel.org S: Maintained F: drivers/pci/host/pci-exynos.c +PCIE DRIVER FOR ST SPEAR13XX +M: Mohit Kumar <[email protected]> +L: linux-pci at vger.kernel.org +S: Maintained +F: drivers/pci/host/pcie-spear13xx.c + PCMCIA SUBSYSTEM P: Linux PCMCIA Team L: linux-pcmcia at lists.infradead.org
Signature · 1 line
1.7.0.1
PATCH 12/12 MAINTAINERS: Add Synopsis Designware PCIe driver maintainer
In reply to Mohit KumarAdd Mohit Kumar and Jingoo Han as maintainer for Synopsis Designware PCIe driver.
--- MAINTAINERS | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-)
MAINTAINERS +7 -0
@@ -6468,6 +6468,13 @@ L: linux-pci at vger.kernel.org S: Maintained F: drivers/pci/host/pcie-spear13xx.c +PCIE DRIVER FOR SYNOPSIS DESIGNWARE CONTROLLER +M: Mohit Kumar <[email protected]> +M: Jingoo Han <[email protected]> +L: linux-pci at vger.kernel.org +S: Maintained +F: drivers/pci/host/pcie-designware.c + PCMCIA SUBSYSTEM P: Linux PCMCIA Team L: linux-pcmcia at lists.infradead.org
Signature · 1 line
1.7.0.1
PATCH 8/12 pcie: designware: Fix IO transfers
In reply to Mohit KumarQuoted 17 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
pp->io_basewhich is the input of the outbound IO address translation unit should be the cpu address, it was programmed wrongly to realio address.We should pass
global_io_offsetrather thansys->io_offsettopci_ioremap_io, so we map the new window into the first available spot in the Linux view of the I/O space.We must also pass cpu address instead of realio address to
pci_ioremap_io.This patch fixes above issue. It has been tested with Lecroy PTC in AIC mode and Pericom PI7C9X2G303EL PCIe switch, which does not work otherwise.
Quoted 8 lines
Signed-off-by Pratyush Anand <[email protected]>Tested-by Mohit Kumar <[email protected]>Tested-by Tim Harvey <[email protected]>Cc Arnd Bergmann <[email protected]>Cc Marek Vasut <[email protected]>Cc Richard Zhu <[email protected]>Cc linux-pci at vger.kernel.orgCc spear-devel at list.st.com
Best regards,
Marek Vasut
PATCH 10/12 SPEAr13xx: defconfig: Update
In reply to Mohit KumarQuoted 61 lines · Mohit KUMAR
Enable EABI, OEABI, VFP and NFS configs in default configuration file for SPEAr13xx.
Enable PCIe support for SPEAr13xx.
Signed-off-by Pratyush Anand<[email protected]>Signed-off-by Mohit Kumar<[email protected]>Cc Mohit Kumar<[email protected]>Cc Viresh Kumar<[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.org--- arch/arm/configs/spear13xx_defconfig | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-)arch/arm/configs/spear13xx_defconfig +13
-0@@ -11,13 +11,24 @@ CONFIG_ARCH_SPEAR13XX=y CONFIG_MACH_SPEAR1310=y CONFIG_MACH_SPEAR1340=y # CONFIG_SWP_EMULATE is not set +CONFIG_PCI_MSI=y +CONFIG_PCIE_SPEAR13XX=y CONFIG_SMP=y # CONFIG_SMP_ON_UP is not set # CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_VFP=y CONFIG_BINFMT_MISC=y CONFIG_NET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_OF_PARTS=y@@ -27,6 +38,7 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_SD=y CONFIG_ATA=y # CONFIG_SATA_PMP is not set CONFIG_SATA_AHCI_PLATFORM=y@@ -66,6 +78,7 @@ CONFIG_USB=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SPEAR=y
arch/arm/configs/spear13xx_defconfig CONFIG_VFAT_FS=m · line 101
Quoted 5 lines
arch/arm/configs/spear13xx_defconfig +2
-0@@ -84,6 +97,8 @@ CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y
Its better to enable CONFIG_FUSE_FS also in case you want to work with fully functional NFS in userspace.
~Rajeev
Quoted 3 lines
arch/arm/configs/spear13xx_defconfig +0
-0CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m
PATCH 1/12 SPEAr13xx: Correct dt field name for stmmac phy-addr
In reply to Mohit KumarQuoted 18 lines · Mohit KUMAR
DT field name for the phy address changed since kernel 3.10. Set the snps,phy-addr to
0xffffffffso that the driver probes for the phy.Signed-off-by Mohit Kumar<[email protected]>Cc Pratyush Anand<[email protected]>Cc Viresh Kumar<[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.orgCc devicetree at vger.kernel.org--- arch/arm/boot/dts/spear13xx.dtsi | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)arch/arm/boot/dts/spear13xx.dtsi +0
-0
arch/arm/boot/dts/spear13xx.dtsi line 158
Quoted 4 lines
arch/arm/boot/dts/spear13xx.dtsi +1
-0@@ -155,6 +155,7 @@ gmac0: eth at e2000000 { compatible = "st,spear600-gmac"; + snps,phy-addr =<0xffffffff>;
Don't you think it should be st,phy-addr =<0xffffffff>, as the manufacturer is 'st' as the compatible suggest
~Rajeev
Quoted 3 lines
arch/arm/boot/dts/spear13xx.dtsi +0
-0reg =<0xe2000000 0x8000>; interrupts =<0 33 0x4 0 34 0x4>;
PATCH 1/12 SPEAr13xx: Correct dt field name for stmmac phy-addr
Recheck the subject line, you are not doing any correction.
Quoted 34 lines · Rajeev KUMAR
Quoted 18 lines · Mohit KUMAR
DT field name for the phy address changed since kernel 3.10. Set the snps,phy-addr to
0xffffffffso that the driver probes for the phy.Signed-off-by Mohit Kumar<[email protected]>Cc Pratyush Anand<[email protected]>Cc Viresh Kumar<[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.orgCc devicetree at vger.kernel.org--- arch/arm/boot/dts/spear13xx.dtsi | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)arch/arm/boot/dts/spear13xx.dtsi +0
-0arch/arm/boot/dts/spear13xx.dtsi line 158
Quoted 4 lines
arch/arm/boot/dts/spear13xx.dtsi +1
-0@@ -155,6 +155,7 @@ gmac0: eth at e2000000 { compatible = "st,spear600-gmac"; + snps,phy-addr =<0xffffffff>;Don't you think it should be st,phy-addr =<0xffffffff>, as the manufacturer is 'st' as the compatible suggest
~Rajeev
Quoted 3 lines
arch/arm/boot/dts/spear13xx.dtsi +0
-0reg =<0xe2000000 0x8000>; interrupts =<0 33 0x4 0 34 0x4>;
PATCH 8/12 pcie: designware: Fix IO transfers
In reply to Marek VasutQuoted 27 lines · Marek Vasut
Quoted 17 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
pp->io_basewhich is the input of the outbound IO address translation unit should be the cpu address, it was programmed wrongly to realio address.We should pass
global_io_offsetrather thansys->io_offsettopci_ioremap_io, so we map the new window into the first available spot in the Linux view of the I/O space.We must also pass cpu address instead of realio address to
pci_ioremap_io.This patch fixes above issue. It has been tested with Lecroy PTC in AIC mode and Pericom PI7C9X2G303EL PCIe switch, which does not work otherwise.
Quoted 8 lines
Signed-off-by Pratyush Anand <[email protected]>Tested-by Mohit Kumar <[email protected]>Tested-by Tim Harvey <[email protected]>Cc Arnd Bergmann <[email protected]>Cc Marek Vasut <[email protected]>Cc Richard Zhu <[email protected]>Cc linux-pci at vger.kernel.orgCc spear-devel at list.st.com
Quoted 8 lines
Acked-by Marek Vasut <[email protected]>Best regards,
Marek Vasut
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Signature · 8 lines
Thanks, Jagan. -------- Jagannadha Sutradharudu Teki, E: jagannadh.teki at gmail.com, P: +91-9676773388 Engineer - System Software Hacker U-boot - SPI Custodian and Zynq APSOC Ln: http://www.linkedin.com/in/jaganteki
PATCH 6/12 pcie: designware: Move register definition to the header file
In reply to Mohit KumarQuoted 109 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
Move synopsis specific register definition from source file to header file, so that they can be re-used by other files if needed.
Signed-off-by Pratyush Anand <[email protected]>Cc Mohit Kumar <[email protected]>Cc Jingoo Han <[email protected]>Cc spear-devel at list.st.comCc linux-pci at vger.kernel.org--- drivers/pci/host/pcie-designware.c | 42 ------------------------------------ drivers/pci/host/pcie-designware.h | 42 ++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 42 deletions(-)drivers/pci/host/pcie-designware.c +0
-42@@ -23,48 +23,6 @@#include "pcie-designware.h" -/* Synopsis specific PCIE configuration registers */ -#define PCIE_PORT_LINK_CONTROL 0x710 -#define PORT_LINK_MODE_MASK (0x3f << 16) -#define PORT_LINK_MODE_1_LANES (0x1 << 16) -#define PORT_LINK_MODE_2_LANES (0x3 << 16) -#define PORT_LINK_MODE_4_LANES (0x7 << 16) - -#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C -#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) -#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) -#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) -#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) -#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) - -#define PCIE_MSI_ADDR_LO 0x820 -#define PCIE_MSI_ADDR_HI 0x824 -#define PCIE_MSI_INTR0_ENABLE 0x828 -#define PCIE_MSI_INTR0_MASK 0x82C -#define PCIE_MSI_INTR0_STATUS 0x830 - -#define PCIE_ATU_VIEWPORT 0x900 -#define PCIE_ATU_REGION_INBOUND (0x1 << 31) -#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) -#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) -#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) -#define PCIE_ATU_CR1 0x904 -#define PCIE_ATU_TYPE_MEM (0x0 << 0) -#define PCIE_ATU_TYPE_IO (0x2 << 0) -#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) -#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) -#define PCIE_ATU_CR2 0x908 -#define PCIE_ATU_ENABLE (0x1 << 31) -#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) -#define PCIE_ATU_LOWER_BASE 0x90C -#define PCIE_ATU_UPPER_BASE 0x910 -#define PCIE_ATU_LIMIT 0x914 -#define PCIE_ATU_LOWER_TARGET 0x918 -#define PCIE_ATU_BUS (x) (((x) & 0xff) << 24) -#define PCIE_ATU_DEV (x) (((x) & 0x1f) << 19) -#define PCIE_ATU_FUNC (x) (((x) & 0x7) << 16) -#define PCIE_ATU_UPPER_TARGET 0x91C -static struct hw_pci dw_pci;static unsigned long global_io_offset;drivers/pci/host/pcie-designware.h +33
-0@@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp);void dw_pcie_setup_rc (struct pcie_port *pp);int dw_pcie_host_init (struct pcie_port *pp); +/* Synopsis specific PCIE configuration registers */ +#define PCIE_PORT_LINK_CONTROL 0x710 +#define PORT_LINK_MODE_MASK (0x3f << 16) +#define PORT_LINK_MODE_1_LANES (0x1 << 16) +#define PORT_LINK_MODE_2_LANES (0x3 << 16) +#define PORT_LINK_MODE_4_LANES (0x7 << 16) + +#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) +#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) +#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) +#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) +#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) + +#define PCIE_MSI_ADDR_LO 0x820 +#define PCIE_MSI_ADDR_HI 0x824 +#define PCIE_MSI_INTR0_ENABLE 0x828 +#define PCIE_MSI_INTR0_MASK 0x82C +#define PCIE_MSI_INTR0_STATUS 0x830 + +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_TYPE_MEM (0x0 << 0) +#define PCIE_ATU_TYPE_IO (0x2 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_CR2 0x908 +#define PCIE_ATU_ENABLE (0x1 << 31) +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
drivers/pci/host/pcie-designware.h int dw_pcie_link_up(struct pcie_port *pp); · line 119
Quoted 10 lines
drivers/pci/host/pcie-designware.h +9
-0+#define PCIE_ATU_LOWER_BASE 0x90C +#define PCIE_ATU_UPPER_BASE 0x910 +#define PCIE_ATU_LIMIT 0x914 +#define PCIE_ATU_LOWER_TARGET 0x918 +#define PCIE_ATU_BUS (x) (((x) & 0xff) << 24) +#define PCIE_ATU_DEV (x) (((x) & 0x1f) << 19) +#define PCIE_ATU_FUNC (x) (((x) & 0x7) << 16) +#define PCIE_ATU_UPPER_TARGET 0x91C +#endif /* _PCIE_DESIGNWARE_H */
Seems like none were using these headers except pcie-designware.c - if ie the case
better to place it same place as before.
Signature · 8 lines
Thanks, Jagan. -------- Jagannadha Sutradharudu Teki, E: jagannadh.teki at gmail.com, P: +91-9676773388 Engineer - System Software Hacker U-boot - SPI Custodian and Zynq APSOC Ln: http://www.linkedin.com/in/jaganteki
PATCH 7/12 pcie: designware: add dw_pcie prefix before cfg_read/write
In reply to Mohit KumarQuoted 132 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
cfg_read/write function are designware pcie specific. Add
dw_pcieprefix to avoid collision in global name space.Signed-off-by Pratyush Anand <[email protected]>Cc Mohit Kumar <[email protected]>Cc Jingoo Han <[email protected]>Cc spear-devel at list.st.comCc linux-pci at vger.kernel.org--- drivers/pci/host/pci-exynos.c | 5 +++-- drivers/pci/host/pcie-designware.c | 23 ++++++++++++++--------- drivers/pci/host/pcie-designware.h | 4 ++-- 3 files changed, 19 insertions(+), 13 deletions(-)drivers/pci/host/pci-exynos.c +3
-2@@ -468,7 +468,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,int ret;exynos_pcie_sideband_dbi_r_mode (pp, true); - ret =cfg_read (pp->dbi_base + (where & ~0x3 ), where, size, val); + ret =dw_pcie_cfg_read (pp->dbi_base + (where & ~0x3 ), where, size, val);exynos_pcie_sideband_dbi_r_mode (pp, false);return ret; }@@ -479,7 +479,8 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,int ret;exynos_pcie_sideband_dbi_w_mode (pp, true); - ret =cfg_write (pp->dbi_base + (where & ~0x3 ), where, size, val); + ret =dw_pcie_cfg_write (pp->dbi_base + (where & ~0x3 ), + where, size, val);exynos_pcie_sideband_dbi_w_mode (pp, false);return ret; }drivers/pci/host/pcie-designware.c +14
-9@@ -32,7 +32,7 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)return sys->private_data; } -int cfg_read (void __iomem *addr,int where,int size,u32 *val) +int dw_pcie_cfg_read (void __iomem *addr,int where,int size,u32 *val) { *val =readl (addr);@@ -46,7 +46,7 @@ int cfg_read(void __iomem *addr, int where, int size, u32 *val)return PCIBIOS_SUCCESSFUL ; } -int cfg_write (void __iomem *addr,int where,int size,u32 val) +int dw_pcie_cfg_write (void __iomem *addr,int where,int size,u32 val) {if (size ==4 )writel (val, addr);@@ -84,7 +84,8 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,if (pp->ops->rd_own_conf) ret = pp->ops->rd_own_conf (pp, where, size, val);else - ret =cfg_read (pp->dbi_base + (where & ~0x3 ), where, size, val); + ret =dw_pcie_cfg_read (pp->dbi_base + (where & ~0x3 ), where, + size, val);return ret; }@@ -97,8 +98,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,if (pp->ops->wr_own_conf) ret = pp->ops->wr_own_conf (pp, where, size, val);else - ret =cfg_write (pp->dbi_base + (where & ~0x3 ), where, size, - val); + ret =dw_pcie_cfg_write (pp->dbi_base + (where & ~0x3 ), where, + size, val);return ret; }@@ -534,11 +535,13 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,if (bus->parent->number == pp->root_bus_nr) {dw_pcie_prog_viewport_cfg0 (pp, busdev); - ret =cfg_read (pp->va_cfg0_base + address, where, size, val); + ret =dw_pcie_cfg_read (pp->va_cfg0_base + address, where, size, + val);dw_pcie_prog_viewport_mem_outbound (pp); }else {dw_pcie_prog_viewport_cfg1 (pp, busdev); - ret =cfg_read (pp->va_cfg1_base + address, where, size, val); + ret =dw_pcie_cfg_read (pp->va_cfg1_base + address, where, size, + val);dw_pcie_prog_viewport_io_outbound (pp); }@@ -557,11 +560,13 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,if (bus->parent->number == pp->root_bus_nr) {dw_pcie_prog_viewport_cfg0 (pp, busdev); - ret =cfg_write (pp->va_cfg0_base + address, where, size, val); + ret =dw_pcie_cfg_write (pp->va_cfg0_base + address, where, size, + val);dw_pcie_prog_viewport_mem_outbound (pp); }else {dw_pcie_prog_viewport_cfg1 (pp, busdev); - ret =cfg_write (pp->va_cfg1_base + address, where, size, val); + ret =dw_pcie_cfg_write (pp->va_cfg1_base + address, where, size, + val);dw_pcie_prog_viewport_io_outbound (pp); }drivers/pci/host/pcie-designware.h +2
-3@@ -66,8 +66,8 @@ struct pcie_host_ops {void (*host_init)(struct pcie_port *pp); }; -int cfg_read (void __iomem *addr,int where,int size,u32 *val); -int cfg_write (void __iomem *addr,int where,int size,u32 val); +int dw_pcie_cfg_read (void __iomem *addr,int where,int size,u32 *val); +int dw_pcie_cfg_write (void __iomem *addr,int where,int size,u32 val);void dw_handle_msi_irq (struct pcie_port *pp);void dw_pcie_msi_init (struct pcie_port *pp);int dw_pcie_link_up (struct pcie_port *pp); --1.7.0.1
Quoted 4 lines
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Thanks, Jagan. -------- Jagannadha Sutradharudu Teki, E: jagannadh.teki at gmail.com, P: +91-9676773388 Engineer - System Software Hacker U-boot - SPI Custodian and Zynq APSOC Ln: http://www.linkedin.com/in/jaganteki
PATCH 6/12 pcie: designware: Move register definition to the header file
In reply to Jagan TekiHello Jagan,
Quoted 128 lines
-----Original Message-----
From: Jagan Teki [mailto:jagannadh.teki at gmail.com]
Sent: Wednesday, December 11, 2013 5:09 PM
To: Mohit KUMAR DCG
Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Pratyush ANAND; Jingoo Han; spear-devel
Subject: Re: [PATCH 06/12] pcie: designware: Move register definition to the header fileQuoted 5 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
Move synopsis specific register definition from source file to header file, so that they can be re-used by other files if needed.
Quoted 8 lines
Signed-off-by Pratyush Anand <[email protected]>Cc Mohit Kumar <[email protected]>Cc Jingoo Han <[email protected]>Cc spear-devel at list.st.comCc linux-pci at vger.kernel.org--- drivers/pci/host/pcie-designware.c | 42 ------------------------------------ drivers/pci/host/pcie-designware.h | 42++++++++++++++++++++++++++++++++++++
Quoted 103 lines
2 files changed, 42 insertions(+), 42 deletions(-)drivers/pci/host/pcie-designware.c +0
-11@@ -23,48 +23,6 @@#include "pcie-designware.h" -/* Synopsis specific PCIE configuration registers */ -#define PCIE_PORT_LINK_CONTROL 0x710 -#define PORT_LINK_MODE_MASK (0x3f << 16) -#define PORT_LINK_MODE_1_LANES (0x1 << 16) -#define PORT_LINK_MODE_2_LANES (0x3 << 16) -#define PORT_LINK_MODE_4_LANES (0x7 << 16) - -#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C -#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) -#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) -#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) -#define
PORT_LOGIC_LINK_WIDTH_2_LANES(0x2<< 8) -#definePORT_LOGIC_LINK_WIDTH_4_LANES(0x4<< 8)drivers/pci/host/pcie-designware.c +0
-29- -#define PCIE_MSI_ADDR_LO 0x820 -#define PCIE_MSI_ADDR_HI 0x824 -#define PCIE_MSI_INTR0_ENABLE 0x828 -#define PCIE_MSI_INTR0_MASK 0x82C -#define PCIE_MSI_INTR0_STATUS 0x830 - -#define PCIE_ATU_VIEWPORT 0x900 -#define PCIE_ATU_REGION_INBOUND (0x1 << 31) -#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) -#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) -#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) -#define PCIE_ATU_CR1 0x904 -#define PCIE_ATU_TYPE_MEM (0x0 << 0) -#define PCIE_ATU_TYPE_IO (0x2 << 0) -#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) -#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) -#define PCIE_ATU_CR2 0x908 -#define PCIE_ATU_ENABLE (0x1 << 31) -#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) -#define PCIE_ATU_LOWER_BASE 0x90C -#define PCIE_ATU_UPPER_BASE 0x910 -#define PCIE_ATU_LIMIT 0x914 -#define PCIE_ATU_LOWER_TARGET 0x918 -#define PCIE_ATU_BUS (x) (((x) & 0xff) << 24) -#define PCIE_ATU_DEV (x) (((x) & 0x1f) << 19) -#define PCIE_ATU_FUNC (x) (((x) & 0x7) << 16) -#define PCIE_ATU_UPPER_TARGET 0x91C -static struct hw_pci dw_pci; static unsigned long global_io_offset; diff --git
a/drivers/pci/host/pcie-designware.hb/drivers/pci/host/pcie-designware.h
index c15379b..da1ed35 100644drivers/pci/host/pcie-designware.h +0
-0@@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp); void
dw_pcie_setup_rc(struct pcie_port *pp); intdw_pcie_host_init(struct pcie_port *pp);drivers/pci/host/pcie-designware.h +38
-0+/* Synopsis specific PCIE configuration registers */ +#define PCIE_PORT_LINK_CONTROL 0x710 +#define PORT_LINK_MODE_MASK (0x3f << 16) +#define PORT_LINK_MODE_1_LANES (0x1 << 16) +#define PORT_LINK_MODE_2_LANES (0x3 << 16) +#define PORT_LINK_MODE_4_LANES (0x7 << 16) + +#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) +#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) +#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) #define +PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) #define +PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) + +#define PCIE_MSI_ADDR_LO 0x820 +#define PCIE_MSI_ADDR_HI 0x824 +#define PCIE_MSI_INTR0_ENABLE 0x828 +#define PCIE_MSI_INTR0_MASK 0x82C +#define PCIE_MSI_INTR0_STATUS 0x830 + +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_TYPE_MEM (0x0 << 0) +#define PCIE_ATU_TYPE_IO (0x2 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_CR2 0x908 +#define PCIE_ATU_ENABLE (0x1 << 31) +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) +#define PCIE_ATU_LOWER_BASE 0x90C +#define PCIE_ATU_UPPER_BASE 0x910 +#define PCIE_ATU_LIMIT 0x914 +#define PCIE_ATU_LOWER_TARGET 0x918 +#define PCIE_ATU_BUS (x) (((x) & 0xff) << 24)
Quoted 8 lines
drivers/pci/host/pcie-designware.h int dw_pcie_link_up(struct pcie_port *pp); · line 119
Quoted 5 lines
drivers/pci/host/pcie-designware.h +4
-0+#define PCIE_ATU_DEV (x) (((x) & 0x1f) << 19) +#define PCIE_ATU_FUNC (x) (((x) & 0x7) << 16) +#define PCIE_ATU_UPPER_TARGET 0x91C +#endif /* _PCIE_DESIGNWARE_H */ Seems like none were using these headers except
pcie-designware.c- if ie the case better to place it same place as before.
- We have include these and used few like ' PCIE_LINK_WIDTH_SPEED_CONTROL ' for SPEAr13xx platform, so move these to the separate header file.
Thanks
Mohit
Quoted 9 lines
--
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki at gmail.com, P: +91-9676773388 Engineer - System Software Hacker U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki
PATCH 6/12 pcie: designware: Move register definition to the header file
Quoted 139 lines · Mohit KUMAR DCG
Hello Jagan,
Quoted 128 lines
-----Original Message-----
From: Jagan Teki [mailto:jagannadh.teki at gmail.com]
Sent: Wednesday, December 11, 2013 5:09 PM
To: Mohit KUMAR DCG
Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Pratyush ANAND; Jingoo Han; spear-devel
Subject: Re: [PATCH 06/12] pcie: designware: Move register definition to the header fileQuoted 5 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
Move synopsis specific register definition from source file to header file, so that they can be re-used by other files if needed.
Quoted 8 lines
Signed-off-by Pratyush Anand <[email protected]>Cc Mohit Kumar <[email protected]>Cc Jingoo Han <[email protected]>Cc spear-devel at list.st.comCc linux-pci at vger.kernel.org--- drivers/pci/host/pcie-designware.c | 42 ------------------------------------ drivers/pci/host/pcie-designware.h | 42++++++++++++++++++++++++++++++++++++
Quoted 103 lines
2 files changed, 42 insertions(+), 42 deletions(-)drivers/pci/host/pcie-designware.c +0
-11@@ -23,48 +23,6 @@#include "pcie-designware.h" -/* Synopsis specific PCIE configuration registers */ -#define PCIE_PORT_LINK_CONTROL 0x710 -#define PORT_LINK_MODE_MASK (0x3f << 16) -#define PORT_LINK_MODE_1_LANES (0x1 << 16) -#define PORT_LINK_MODE_2_LANES (0x3 << 16) -#define PORT_LINK_MODE_4_LANES (0x7 << 16) - -#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C -#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) -#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) -#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) -#define
PORT_LOGIC_LINK_WIDTH_2_LANES(0x2<< 8) -#definePORT_LOGIC_LINK_WIDTH_4_LANES(0x4<< 8)drivers/pci/host/pcie-designware.c +0
-29- -#define PCIE_MSI_ADDR_LO 0x820 -#define PCIE_MSI_ADDR_HI 0x824 -#define PCIE_MSI_INTR0_ENABLE 0x828 -#define PCIE_MSI_INTR0_MASK 0x82C -#define PCIE_MSI_INTR0_STATUS 0x830 - -#define PCIE_ATU_VIEWPORT 0x900 -#define PCIE_ATU_REGION_INBOUND (0x1 << 31) -#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) -#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) -#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) -#define PCIE_ATU_CR1 0x904 -#define PCIE_ATU_TYPE_MEM (0x0 << 0) -#define PCIE_ATU_TYPE_IO (0x2 << 0) -#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) -#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) -#define PCIE_ATU_CR2 0x908 -#define PCIE_ATU_ENABLE (0x1 << 31) -#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) -#define PCIE_ATU_LOWER_BASE 0x90C -#define PCIE_ATU_UPPER_BASE 0x910 -#define PCIE_ATU_LIMIT 0x914 -#define PCIE_ATU_LOWER_TARGET 0x918 -#define PCIE_ATU_BUS (x) (((x) & 0xff) << 24) -#define PCIE_ATU_DEV (x) (((x) & 0x1f) << 19) -#define PCIE_ATU_FUNC (x) (((x) & 0x7) << 16) -#define PCIE_ATU_UPPER_TARGET 0x91C -static struct hw_pci dw_pci; static unsigned long global_io_offset; diff --git
a/drivers/pci/host/pcie-designware.hb/drivers/pci/host/pcie-designware.h
index c15379b..da1ed35 100644drivers/pci/host/pcie-designware.h +0
-0@@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp); void
dw_pcie_setup_rc(struct pcie_port *pp); intdw_pcie_host_init(struct pcie_port *pp);drivers/pci/host/pcie-designware.h +38
-0+/* Synopsis specific PCIE configuration registers */ +#define PCIE_PORT_LINK_CONTROL 0x710 +#define PORT_LINK_MODE_MASK (0x3f << 16) +#define PORT_LINK_MODE_1_LANES (0x1 << 16) +#define PORT_LINK_MODE_2_LANES (0x3 << 16) +#define PORT_LINK_MODE_4_LANES (0x7 << 16) + +#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) +#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) +#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) #define +PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) #define +PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) + +#define PCIE_MSI_ADDR_LO 0x820 +#define PCIE_MSI_ADDR_HI 0x824 +#define PCIE_MSI_INTR0_ENABLE 0x828 +#define PCIE_MSI_INTR0_MASK 0x82C +#define PCIE_MSI_INTR0_STATUS 0x830 + +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_TYPE_MEM (0x0 << 0) +#define PCIE_ATU_TYPE_IO (0x2 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_CR2 0x908 +#define PCIE_ATU_ENABLE (0x1 << 31) +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) +#define PCIE_ATU_LOWER_BASE 0x90C +#define PCIE_ATU_UPPER_BASE 0x910 +#define PCIE_ATU_LIMIT 0x914 +#define PCIE_ATU_LOWER_TARGET 0x918 +#define PCIE_ATU_BUS (x) (((x) & 0xff) << 24)Quoted 8 lines
drivers/pci/host/pcie-designware.h int dw_pcie_link_up(struct pcie_port *pp); · line 119
Quoted 5 lines
drivers/pci/host/pcie-designware.h +4
-0+#define PCIE_ATU_DEV (x) (((x) & 0x1f) << 19) +#define PCIE_ATU_FUNC (x) (((x) & 0x7) << 16) +#define PCIE_ATU_UPPER_TARGET 0x91C +#endif /* _PCIE_DESIGNWARE_H */ Seems like none were using these headers except
pcie-designware.c- if ie the case better to place it same place as before.
Quoted 3 lines
- We have include these and used few like '
PCIE_LINK_WIDTH_SPEED_CONTROL' for SPEAr13xx platform, so move these to the separate header file.
Signature · 8 lines
Thanks, Jagan. -------- Jagannadha Sutradharudu Teki, E: jagannadh.teki at gmail.com, P: +91-9676773388 Engineer - System Software Hacker U-boot - SPI Custodian and Zynq APSOC Ln: http://www.linkedin.com/in/jaganteki
PATCH 8/12 pcie: designware: Fix IO transfers
In reply to Mohit KumarQuoted 8 lines · Mohit Kumar
Signed-off-by Pratyush Anand <[email protected]>Tested-by Mohit Kumar <[email protected]>Tested-by Tim Harvey <[email protected]>Cc Arnd Bergmann <[email protected]>Cc Marek Vasut <[email protected]>Cc Richard Zhu <[email protected]>Cc linux-pci at vger.kernel.orgCc spear-devel at list.st.com
PATCH 6/12 pcie: designware: Move register definition to the header file
In reply to Mohit KUMAR DCGQuoted 6 lines · Mohit KUMAR DCG
Quoted 3 lines
Seems like none were using these headers except
pcie-designware.c- if ie the case better to place it same place as before.- We have include these and used few like '
PCIE_LINK_WIDTH_SPEED_CONTROL' for SPEAr13xx platform, so move these to the separate header file.
I think it's better not to touch any of the registers from a platform-specific driver. Better make a high-level function in the common code that the spear driver can call to change this register.
Arnd
PATCH 5/12 clk: SPEAr13xx: Fix pcie clock name
In reply to Mohit KumarQuoted 4 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
Follow dt clock naming convention for PCIe clocks.
I think in the future, the spear clocks really need to get moved into DT representations, as we do for other platforms, which will get rid of a lot of code in drivers/clk, including all the clkdev registration.
Arnd
PATCH 2/12 SPEAr13xx: Move SPEAr1340 definitions to header file
In reply to Mohit KumarQuoted 4 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
Move SPEAr1340 definitions to header files so that theese can be used by other code too.
This looks like a regression, we intentionally made them private and they should be moved into a proper driver instead of being globally visible.
arch/arm/mach-spear/include/mach/spear.h line 91
Quoted 11 lines
arch/arm/mach-spear/include/mach/spear.h +3
-0@@ -86,6 +86,61 @@/* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE UART_BASE +/* PCIe/SATA Base addresses */ +#define SPEAR1340_SATA_BASE UL(0xB1000000) +#define SPEAR1340_PCIE_BASE UL(0xB1000000)
These should be in DT only.
arch/arm/mach-spear/include/mach/spear.h line 100
Quoted 8 lines
arch/arm/mach-spear/include/mach/spear.h +8
-0+/* Power Management Registers */ +#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100) +#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104) +#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108) + +#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318) +#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C) +#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320)
The RST bits should probably go into a drivers/reset driver. Not sure what the other registers do, but I'm sure we can find a driver for these too, possibly they should be part of the PHY driver?
Quoted 6 lines
arch/arm/mach-spear/include/mach/spear.h +0
-2@@ -22,60 +22,6 @@#include <mach/spear.h> /* FIXME: Move SATA PHY code into a standalone driver */ - -
arch/arm/mach-spear/include/mach/spear.h line 36
Quoted 10 lines
arch/arm/mach-spear/include/mach/spear.h +0
-10-/* PCIE - SATA configuration registers */ -#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424) -/* PCIE CFG MASks */ -#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11) -#define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10) -#define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9) -#define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8) -#define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4) -#define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3) -#define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
You leave the FIXME in place but move away the definitions it talks about. Please fix the problem instead.
Arnd
PATCH 6/12 pcie: designware: Move register definition to the header file
In reply to Arnd BergmannQuoted 11 lines · Arnd Bergmann
Quoted 6 lines · Mohit KUMAR DCG
Quoted 3 lines
Seems like none were using these headers except
pcie-designware.c- if ie the case better to place it same place as before.- We have include these and used few like '
PCIE_LINK_WIDTH_SPEED_CONTROL' for SPEAr13xx platform, so move these to the separate header file.I think it's better not to touch any of the registers from a platform-specific driver. Better make a high-level function in the common code that the spear driver can call to change this register.
I also agree with Arnd's opinion.
Best regards,
Jingoo Han
PATCH 3/12 SPEAr13xx: Add SPEAr1310 PCIe register definitions
In reply to Mohit KumarQuoted 5 lines · Mohit Kumar
arch/arm/mach-spear/include/mach/spear.h +0
-0
arch/arm/mach-spear/include/mach/spear.h line 149
Quoted 10 lines
arch/arm/mach-spear/include/mach/spear.h +7
-0@@ -140,6 +140,79 @@ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) +#define VA_SPEAR1310_PCIE_SATA_CFG (VA_MISC_BASE + 0x3A4) +#define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31) +#define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30) +#define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29) +#define SPEAR1310_PCIE_SATA2_SEL_SATA (1 << 31) +#define SPEAR1310_PCIE_SATA1_SEL_SATA (1 << 30) +#define SPEAR1310_PCIE_SATA0_SEL_SATA (1 << 29)
These should definitely be part of the PHY driver.
Regarding style, don't use a hardcoded VA_MISC_BASE constant here, but find the right address in the driver, and instead of shifting bits, just use hexadecimal notation:
#define SPEAR1310_PCIE_SATA2_SEL_PCIE 0x80000000
#define SPEAR1310_PCIE_SATA1_SEL_PCIE 0x40000000
...
However, if you have a "reset" driver, you can use #reset-cells=<1> and pass the bit as the reset specifier.
Arnd
PATCH 9/12 pcie: SPEAr13xx: Add designware pcie support
In reply to Mohit Kumardrivers/pci/host/pcie-spear13xx.c line 24
Quoted 10 lines · Mohit Kumar
drivers/pci/host/pcie-spear13xx.c new file +10
-0+#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/pci.h> +#include <linux/platform_device.h> +#include <linux/resource.h> +#include <mach/spear.h>
This won't actually build: you cannot access mach/*.h header files from outside of mach-spear!
drivers/pci/host/pcie-spear13xx.c line 35
Quoted 8 lines
drivers/pci/host/pcie-spear13xx.c new file +8
-0+struct spear13xx_pcie { +void __iomem *phy_base; +void __iomem *app_base; +struct clk *clk; +struct pcie_port pp; +int id; +int is_gen1; +};
The pcie driver shouldn't have direct access to the phy registers, use a phy driver for that.
drivers/pci/host/pcie-spear13xx.c line 197
Quoted 7 lines
drivers/pci/host/pcie-spear13xx.c new file +6
-0+static int workaround_linkup_spear1340 (struct spear13xx_pcie *spear13xx_pcie) +{ +} + +static int spear13xx_pcie_establish_link (struct pcie_port *pp) +{
These should move into the phy driver.
drivers/pci/host/pcie-spear13xx.c line 257
Quoted 3 lines
drivers/pci/host/pcie-spear13xx.c new file +3
-0+/* txdetectrx workaround for SPEAr1310 */ +if (of_machine_is_compatible ("st,spear1310" )) +writeb (0x00 , spear13xx_pcie->phy_base +0x16 );
Don't use of_machine_is_compatible() to test for features or bugs of a particular device. Instead use a binary property in the specific device node, or key it off of the device's "compatible" value if there are a lot of differences. You seem to have a couple of these to test for one or the other PHY implementation, those will go away when you have a proper driver for them.
Arnd
PATCH 8/12 pcie: designware: Fix IO transfers
In reply to Mohit KumarQuoted 17 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
pp->io_basewhich is the input of the outbound IO address translation unit should be the cpu address, it was programmed wrongly to realio address.We should pass
global_io_offsetrather thansys->io_offsettopci_ioremap_io, so we map the new window into the first available spot in the Linux view of the I/O space.We must also pass cpu address instead of realio address to
pci_ioremap_io.This patch fixes above issue. It has been tested with Lecroy PTC in AIC mode and Pericom PI7C9X2G303EL PCIe switch, which does not work otherwise.
Quoted 8 lines
Signed-off-by Pratyush Anand <[email protected]>Tested-by Mohit Kumar <[email protected]>Tested-by Tim Harvey <[email protected]>Cc Arnd Bergmann <[email protected]>Cc Marek Vasut <[email protected]>Cc Richard Zhu <[email protected]>Cc linux-pci at vger.kernel.orgCc spear-devel at list.st.com
Best regards,
Jingoo Han
Quoted 3 lines
--- drivers/pci/host/pcie-designware.c | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-)
PATCH 1/12 SPEAr13xx: Correct dt field name for stmmac phy-addr
In reply to Rajeev kumarQuoted 20 lines · Rajeev kumar
Quoted 19 lines · Mohit KUMAR
DT field name for the phy address changed since kernel 3.10. Set the snps,phy-addr to
0xffffffffso that the driver probes for the phy.Signed-off-by Mohit Kumar<[email protected]>Cc Pratyush Anand<[email protected]>Cc Viresh Kumar<[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.orgCc devicetree at vger.kernel.org--- arch/arm/boot/dts/spear13xx.dtsi | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)arch/arm/boot/dts/spear13xx.dtsi +0
-0@@ -155,6 +155,7 @@
Quoted 6 lines
arch/arm/boot/dts/spear13xx.dtsi
Quoted 3 lines
arch/arm/boot/dts/spear13xx.dtsi +1
-0gmac0: eth at e2000000 { compatible = "st,spear600-gmac"; + snps,phy-addr =<0xffffffff>;Don't you think it should be st,phy-addr =<0xffffffff>, as the manufacturer is 'st' as the compatible suggest
Hi Rajeev Kumar,
According to the Documentation, it guides to use 'snps' prefix.
In my humble opinion,
'gmac' is a Synopsys based IP. Thus, if 'snps,phy-addr' is not ST specific, 'snps' prefix can be used.
./Documentation/devicetree/bindings/net/stmmac.txt
- snps,phy-addr phy address to connect to.
Best regards,
Jingoo Han
PATCH 7/12 pcie: designware: add dw_pcie prefix before cfg_read/write
In reply to Mohit KumarQuoted 11 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
cfg_read/write function are designware pcie specific. Add
dw_pcieprefix to avoid collision in global name space.Signed-off-by Pratyush Anand <[email protected]>Cc Mohit Kumar <[email protected]>Cc Jingoo Han <[email protected]>Cc spear-devel at list.st.comCc linux-pci at vger.kernel.org
It looks good. Also, I tested this patch on Exynos platform.
Best regards,
Jingoo Han
Quoted 5 lines
--- drivers/pci/host/pci-exynos.c | 5 +++-- drivers/pci/host/pcie-designware.c | 23 ++++++++++++++--------- drivers/pci/host/pcie-designware.h | 4 ++-- 3 files changed, 19 insertions(+), 13 deletions(-)
PATCH 7/12 pcie: designware: add dw_pcie prefix before cfg_read/write
In reply to Jagan TekiQuoted 15 lines · Jagan Teki
Quoted 14 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
cfg_read/write function are designware pcie specific. Add
dw_pcieprefix to avoid collision in global name space.Signed-off-by Pratyush Anand <[email protected]>Cc Mohit Kumar <[email protected]>Cc Jingoo Han <[email protected]>Cc spear-devel at list.st.comCc linux-pci at vger.kernel.org--- drivers/pci/host/pci-exynos.c | 5 +++-- drivers/pci/host/pcie-designware.c | 23 ++++++++++++++--------- drivers/pci/host/pcie-designware.h | 4 ++--
[....]
Quoted 1 line
Please use ' Reviewed-by', instead of 'Acked-by'.
It will apply to other patches, too.
According to the ./Documentation/SubmittingPatches,
Acked-by: is often used by the maintainer of the affected code when that maintainer neither contributed to nor forwarded the patch.
Reviewed-by:, instead, indicates that the patch has been reviewed and found acceptable according to the Reviewer's Statement:
Best regards,
Jingoo Han
PATCH 8/12 pcie: designware: Fix IO transfers
In reply to Jagan TekiQuoted 30 lines · Jagan Teki
Quoted 29 lines · Marek Vasut
Quoted 17 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
pp->io_basewhich is the input of the outbound IO address translation unit should be the cpu address, it was programmed wrongly to realio address.We should pass
global_io_offsetrather thansys->io_offsettopci_ioremap_io, so we map the new window into the first available spot in the Linux view of the I/O space.We must also pass cpu address instead of realio address to
pci_ioremap_io.This patch fixes above issue. It has been tested with Lecroy PTC in AIC mode and Pericom PI7C9X2G303EL PCIe switch, which does not work otherwise.
Quoted 8 lines
Signed-off-by Pratyush Anand <[email protected]>Tested-by Mohit Kumar <[email protected]>Tested-by Tim Harvey <[email protected]>Cc Arnd Bergmann <[email protected]>Cc Marek Vasut <[email protected]>Cc Richard Zhu <[email protected]>Cc linux-pci at vger.kernel.orgCc spear-devel at list.st.comAcked-by Marek Vasut <[email protected]>
Quoted 8 lines
Quoted 6 lines
Best regards,
Marek Vasut
--
To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo at vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
As I said, please use 'Reviewed-by' instead of 'Acked-by'.
Best regards,
Jingoo Han
PATCH 11/12 MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
In reply to Mohit KumarQuoted 7 lines · Mohit Kumar
Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.
Signed-off-by Mohit Kumar <[email protected]>Signed-off-by Pratyush Anand <[email protected]>Cc Jingoo Han <[email protected]>Cc linux-pci at vger.kernel.org
Best regards,
Jingoo Han
Quoted 23 lines
--- MAINTAINERS | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)MAINTAINERS +6
-1@@ -6462,6 +6462,12 @@ L: linux-pci at vger.kernel.org S: Maintained F: drivers/pci/host/pci-exynos.c +PCIE DRIVER FOR ST SPEAR13XX +M: Mohit Kumar <[email protected]> +L: linux-pci at vger.kernel.org +S: Maintained +F: drivers/pci/host/pcie-spear13xx.c + PCMCIA SUBSYSTEM P: Linux PCMCIA Team L: linux-pcmcia at lists.infradead.org --1.7.0.1
PATCH 1/12 SPEAr13xx: Correct dt field name for stmmac phy-addr
In reply to Jingoo HanQuoted 28 lines · Jingoo Han
Quoted 20 lines · Rajeev kumar
Quoted 19 lines · Mohit KUMAR
DT field name for the phy address changed since kernel 3.10. Set the snps,phy-addr to
0xffffffffso that the driver probes for the phy.Signed-off-by Mohit Kumar<[email protected]>Cc Pratyush Anand<[email protected]>Cc Viresh Kumar<[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.orgCc devicetree at vger.kernel.org--- arch/arm/boot/dts/spear13xx.dtsi | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)arch/arm/boot/dts/spear13xx.dtsi +0
-0@@ -155,6 +155,7 @@Quoted 6 lines
arch/arm/boot/dts/spear13xx.dtsi
Quoted 3 lines
arch/arm/boot/dts/spear13xx.dtsi +1
-0gmac0: eth at e2000000 { compatible = "st,spear600-gmac"; + snps,phy-addr =<0xffffffff>;Don't you think it should be st,phy-addr =<0xffffffff>, as the manufacturer is 'st' as the compatible suggest
Quoted 8 lines
Hi Rajeev Kumar,
According to the Documentation, it guides to use 'snps' prefix.
In my humble opinion,
'gmac' is a Synopsys based IP. Thus, if 'snps,phy-addr' is not ST specific, 'snps' prefix can be used.
Very much true, I raise the point just becuase compatible = "st,spear600-gmac". Check the manufacturer name here.
~Rajeev
Quoted 6 lines
./Documentation/devicetree/bindings/net/stmmac.txt
- snps,phy-addr phy address to connect to.Best regards,
Jingoo Han
PATCH 1/12 SPEAr13xx: Correct dt field name for stmmac phy-addr
Hi,
Quoted 39 lines · Rajeev kumar
Quoted 38 lines · Jingoo Han
Quoted 23 lines · Rajeev kumar
Quoted 21 lines · Mohit KUMAR
DT field name for the phy address changed since kernel 3.10. Set the snps,phy-addr to
0xffffffffso that the driver probes for the phy.Signed-off-by Mohit Kumar<[email protected]>Cc Pratyush Anand<[email protected]>Cc Viresh Kumar<[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.orgCc devicetree at vger.kernel.org--- arch/arm/boot/dts/spear13xx.dtsi | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)arch/arm/boot/dts/spear13xx.dtsi +0
-0@@ -155,6 +155,7 @@Quoted 7 lines
arch/arm/boot/dts/spear13xx.dtsi
Quoted 3 lines
arch/arm/boot/dts/spear13xx.dtsi +1
-0gmac0: eth at e2000000 { compatible = "st,spear600-gmac"; + snps,phy-addr =<0xffffffff>;Don't you think it should be st,phy-addr =<0xffffffff>, as the manufacturer is 'st' as the compatible suggest
Hi Rajeev Kumar,
According to the Documentation, it guides to use 'snps' prefix.
Quoted 8 lines
Quoted 4 lines
In my humble opinion,
'gmac' is a Synopsys based IP. Thus, if 'snps,phy-addr' is not ST specific, 'snps' prefix can be used.Very much true, I raise the point just becuase compatible = "st,spear600-gmac". Check the manufacturer name here.
As documented, "st,spear600-gmac" is there for backwards compatibility. It should really be updated to '"snps,dwmac-<version>", "snps,dwmac"'.
Quoted 2 lines
Quoted 2 lines
./Documentation/devicetree/bindings/net/stmmac.txt
- snps,phy-addr phy address to connect to.
About the "snps,phy-addr" property, Florian recently raised the issue that this is !standard. I am currently implementing proper DT ethernet phy node support for stmmac. Just a heads up. :)
ChenYu
PATCH 10/12 SPEAr13xx: defconfig: Update
In reply to Rajeev kumarHello Rajeev,
Quoted 13 lines
-----Original Message-----
From: Rajeev KUMAR
Sent: Wednesday, December 11, 2013 4:17 PM
To: Mohit KUMAR DCG
Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Pratyush ANAND; Viresh Kumar; spear-devel
Subject: Re: [PATCH 10/12] SPEAr13xx: defconfig: UpdateQuoted 4 lines · Mohit KUMAR
Enable EABI, OEABI, VFP and NFS configs in default configuration file for SPEAr13xx.
Enable PCIe support for SPEAr13xx.
[...]
Quoted 6 lines
arch/arm/configs/spear13xx_defconfig CONFIG_VFAT_FS=m · line 101
Quoted 3 lines
CONFIG_JFFS2_FS=yarch/arm/configs/spear13xx_defconfig +2
-0+CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=yIts better to enable
CONFIG_FUSE_FSalso in case you want to work with fully functional NFS in userspace.
- OK, will enable this option.
Thanks
Mohit
PATCH 6/12 pcie: designware: Move register definition to the header file
In reply to Jingoo HanHello Arnd,
Quoted 17 lines
-----Original Message-----
From: Jingoo Han [mailto:jg1.han at samsung.com]
Sent: Thursday, December 12, 2013 4:19 AM
To: Mohit KUMAR DCG; 'Arnd Bergmann'
Cc: linux-arm-kernel at lists.infradead.org; 'Jagan Teki'; linux- pci at vger.kernel.org; spear-devel; Pratyush ANAND; 'Jingoo Han'
Subject: Re: [PATCH 06/12] pcie: designware: Move register definition to the header fileQuoted 7 lines · Arnd Bergmann
Quoted 6 lines · Mohit KUMAR DCG
Quoted 3 lines
Seems like none were using these headers except
pcie-designware.c
- if ie the case better to place it same place as before.- We have include these and used few like '
PCIE_LINK_WIDTH_SPEED_CONTROL' for SPEAr13xx platform, so move
Quoted 7 lines
these to the separate header file.
Quoted 4 lines
I think it's better not to touch any of the registers from a platform-specific driver. Better make a high-level function in the common code that the spear driver can call to change this register.
I also agree with Arnd's opinion.
- As suggested, I will implement required functions in dw driver and hence no need to move register definitions.
Regards
Mohit
PATCH 5/12 clk: SPEAr13xx: Fix pcie clock name
In reply to Arnd BergmannHello Arnd,
Quoted 9 lines
-----Original Message-----
From: Arnd Bergmann [mailto:arnd at arndb.de]
Sent: Thursday, December 12, 2013 4:13 AM
To: linux-arm-kernel at lists.infradead.org
Cc: Mohit KUMAR DCG; linux-pci at vger.kernel.org; Pratyush ANAND; spear- devel; Viresh Kumar
Subject: Re: [PATCH 05/12] clk: SPEAr13xx: Fix pcie clock nameOn Wednesday 11 December 2013, Mohit Kumar wrote:
Quoted 8 lines
Quoted 4 lines
From: Pratyush Anand <[email protected]>
Follow dt clock naming convention for PCIe clocks.
I think in the future, the spear clocks really need to get moved into DT representations, as we do for other platforms, which will get rid of a lot of code in
drivers/clk, including all the clkdev registration.
- Let it be this way for now. May be we will improve it in next cycle.
Thanks
Mohit
PATCH 1/12 SPEAr13xx: Correct dt field name for stmmac phy-addr
In reply to Chen-Yu TsaiHello Shiraz/Viresh,
Quoted 69 lines
-----Original Message-----
From: wens213 at gmail.com [mailto:wens213 at gmail.com] On Behalf Of Chen-Yu Tsai
Sent: Thursday, December 12, 2013 9:37 AM
To: Rajeev KUMAR
Cc: Jingoo Han; Pratyush ANAND; devicetree at vger.kernel.org; Mohit KUMAR DCG; spear-devel; Viresh Kumar; linux-pci at vger.kernel.org; linux- arm-kernel at lists.infradead.org; Florian Fainelli
Subject: Re: [PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy- addrHi,
Quoted 39 lines · Rajeev kumar
Quoted 38 lines · Jingoo Han
Quoted 23 lines · Rajeev kumar
Quoted 21 lines · Mohit KUMAR
DT field name for the phy address changed since kernel 3.10. Set the snps,phy-addr to
0xffffffffso that the driver probes for the phy.Signed-off-by Mohit Kumar<[email protected]>Cc Pratyush Anand<[email protected]>Cc Viresh Kumar<[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.orgCc devicetree at vger.kernel.org--- arch/arm/boot/dts/spear13xx.dtsi | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)arch/arm/boot/dts/spear13xx.dtsi +0
-0@@ -155,6 +155,7 @@Quoted 7 lines
arch/arm/boot/dts/spear13xx.dtsi
Quoted 3 lines
arch/arm/boot/dts/spear13xx.dtsi +1
-0gmac0: eth at e2000000 { compatible = "st,spear600-gmac"; + snps,phy-addr =<0xffffffff>;Don't you think it should be st,phy-addr =<0xffffffff>, as the manufacturer is 'st' as the compatible suggest
Hi Rajeev Kumar,
According to the Documentation, it guides to use 'snps' prefix.
Quoted 8 lines
Quoted 4 lines
In my humble opinion,
'gmac' is a Synopsys based IP. Thus, if 'snps,phy-addr' is not ST specific, 'snps' prefix can be used.Very much true, I raise the point just becuase compatible = "st,spear600-gmac". Check the manufacturer name here.
As documented, "st,spear600-gmac" is there for backwards compatibility. It should really be updated to '"snps,dwmac-<version>", "snps,dwmac"'.
Quoted 7 lines
Quoted 2 lines
Quoted 2 lines
./Documentation/devicetree/bindings/net/stmmac.txt
- snps,phy-addr phy address to connect to.About the "snps,phy-addr" property, Florian recently raised the issue that this is !standard. I am currently implementing proper DT ethernet phy node support for stmmac. Just a heads up. :)
- Any comment on this?
Regards
Mohit
PATCH 5/12 clk: SPEAr13xx: Fix pcie clock name
In reply to Mohit KUMAR DCGQuoted 6 lines · Mohit KUMAR DCG
Quoted 4 lines
I think in the future, the spear clocks really need to get moved into DT representations, as we do for other platforms, which will get rid of a lot of code in
drivers/clk, including all the clkdev registration.- Let it be this way for now. May be we will improve it in next cycle
Fair enough. This will be a major change that doesn't have to delay the PCIe driver, just make sure you can address the other comments I made for now.
The clock situation will have to be worked out though before the bindings can be considered stable, because you will have to add mandatory 'clocks' properties to a lot of them.
Arnd
PATCH 2/12 SPEAr13xx: Move SPEAr1340 definitions to header file
In reply to Arnd BergmannHello Arnd,
Quoted 44 lines
-----Original Message-----
From: Arnd Bergmann [mailto:arnd at arndb.de]
Sent: Thursday, December 12, 2013 4:18 AM
To: linux-arm-kernel at lists.infradead.org
Cc: Mohit KUMAR DCG; linux-pci at vger.kernel.org; Pratyush ANAND; spear- devel; Viresh Kumar
Subject: Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header fileQuoted 4 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
Move SPEAr1340 definitions to header files so that theese can be used by other code too.
This looks like a regression, we intentionally made them private and they should be moved into a proper driver instead of being globally visible.
arch/arm/mach-spear/include/mach/spear.h line 86
Quoted 7 lines
arch/arm/mach-spear/include/mach/spear.h +0
-0@@ -86,6 +86,61 @@/* Debug uart for linux, will be used for debug and uncompress messages */
arch/arm/mach-spear/include/mach/spear.h line 91
Quoted 5 lines
arch/arm/mach-spear/include/mach/spear.h +3
-0#define SPEAR_DBG_UART_BASE UART_BASE +/* PCIe/SATA Base addresses */ +#define SPEAR1340_SATA_BASE UL(0xB1000000) +#define SPEAR1340_PCIE_BASE UL(0xB1000000)These should be in DT only.
arch/arm/mach-spear/include/mach/spear.h line 93
Quoted 2 lines
arch/arm/mach-spear/include/mach/spear.h +2
-0+/* Power Management Registers */ +#define SPEAR1340_PCM_CFG (VA_MISC_BASE +
0x100)arch/arm/mach-spear/include/mach/spear.h line 94
Quoted 1 line
arch/arm/mach-spear/include/mach/spear.h +1
-0+#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104)arch/arm/mach-spear/include/mach/spear.h line 95
Quoted 1 line
arch/arm/mach-spear/include/mach/spear.h +1
-0+#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE +
0x108)arch/arm/mach-spear/include/mach/spear.h line 97
Quoted 2 lines
arch/arm/mach-spear/include/mach/spear.h +2
-0+ +#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318)
Quoted 8 lines
arch/arm/mach-spear/include/mach/spear.h line 98
Quoted 1 line
arch/arm/mach-spear/include/mach/spear.h +1
-0+#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C)arch/arm/mach-spear/include/mach/spear.h line 99
Quoted 1 line
arch/arm/mach-spear/include/mach/spear.h +1
-0+#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320)The RST bits should probably go into a
drivers/resetdriver. Not sure what the other registers do, but I'm sure we can find a driver for these too, possibly they should be part of the PHY driver?
- Perhaps if we implement phy and reset driver then we may not require to move these definitions and it will address most of your comments on SPEar13xx pcie driver. I am understanding and working on this.l
Regards
Mohit
PATCH 9/12 pcie: SPEAr13xx: Add designware pcie support
In reply to Arnd BergmannHello Arnd,
Quoted 9 lines
-----Original Message-----
From: Arnd Bergmann [mailto:arnd at arndb.de]
Sent: Thursday, December 12, 2013 4:31 AM
To: linux-arm-kernel at lists.infradead.org
Cc: Mohit KUMAR DCG; linux-pci at vger.kernel.org; Pratyush ANAND; Jingoo Han; Viresh Kumar; spear-devel
Subject: Re: [PATCH 09/12] pcie: SPEAr13xx: Add designware pcie supportOn Wednesday 11 December 2013, Mohit Kumar wrote:
Quoted 13 lines
drivers/pci/host/pcie-spear13xx.c line 24
Quoted 10 lines
drivers/pci/host/pcie-spear13xx.c new file +10
-0+#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/pci.h> +#include <linux/platform_device.h> +#include <linux/resource.h> +#include <mach/spear.h> This won't actually build: you cannot access mach/*.h header files from outside of mach-spear!
- OK, will fix it.
Quoted 12 lines
drivers/pci/host/pcie-spear13xx.c line 35
Quoted 9 lines
drivers/pci/host/pcie-spear13xx.c new file +8
-0+struct spear13xx_pcie { +void __iomem *phy_base; +void __iomem *app_base; +struct clk *clk; +struct pcie_port pp; +int id; +int is_gen1; +};The pcie driver shouldn't have direct access to the phy registers, use a phy driver for that.
- OK. In few workarounds we have to access controller as well as phy registers, How we should handle such cases if we separate out phy driver from here? Should it be through phy global functions called from pcie driver?
Thanks
Mohit
PATCH 9/12 pcie: SPEAr13xx: Add designware pcie support
Quoted 2 lines · Mohit KUMAR DCG
Quoted 1 line · Arnd Bergmann
On Wednesday 11 December 2013, Mohit Kumar wrote:
[.....]
Quoted 12 lines
Quoted 11 lines
drivers/pci/host/pcie-spear13xx.c line 35
Quoted 8 lines
drivers/pci/host/pcie-spear13xx.c new file +8
-0+struct spear13xx_pcie { +void __iomem *phy_base; +void __iomem *app_base; +struct clk *clk; +struct pcie_port pp; +int id; +int is_gen1; +};The pcie driver shouldn't have direct access to the phy registers, use a phy driver for that.
Quoted 3 lines
- OK. In few workarounds we have to access controller as well as phy registers, How we should handle such cases if we separate out phy driver from here? Should it be through phy global functions called from pcie driver?
Arnd, do you mean the following?
1. Implement Spear PCIe PHY driver using General PHY framework. ./drivers/phy/phy-spear13xx-pcie.c
2. Call General PHY APIs
./drivers/pci/host/pcie-spear13xx.c
#include <linux/phy/phy.h>
pp->phy = devm_phy_get(pp->dev, ...); phy_power_on(pp->phy); phy_power_off(pp->phy);
Best regards,
Jingoo Han
PATCH 9/12 pcie: SPEAr13xx: Add designware pcie support
Quoted 9 lines · Jingoo Han
Arnd, do you mean the following?
1. Implement Spear PCIe PHY driver using General PHY framework.
./drivers/phy/phy-spear13xx-pcie.c2. Call General PHY APIs
./drivers/pci/host/pcie-spear13xx.c
#include <linux/phy/phy.h>
Quoted 5 lines
pp->phy = devm_phy_get(pp->dev, ...); phy_power_on(pp->phy); phy_power_off(pp->phy);
Yes, exactly.
Of course if the phy driver is licensed from some other company such as designware as well, or if it can handle more than just pcie, the implementation of the phy driver and the binding should reflect that.
Arnd
PATCH 2/12 SPEAr13xx: Move SPEAr1340 definitions to header file
In reply to Mohit KUMAR DCGQuoted 7 lines · Mohit KUMAR DCG
Quoted 3 lines
The RST bits should probably go into a
drivers/resetdriver. Not sure what the other registers do, but I'm sure we can find a driver for these too, possibly they should be part of the PHY driver?- Perhaps if we implement phy and reset driver then we may not require to move these definitions and it will address most of your comments on SPEar13xx pcie driver. I am understanding and working on this.l
Ok, very good.
Arnd
PATCH 8/12 pcie: designware: Fix IO transfers
In reply to Jingoo HanHi Bjorn,
Quoted 4 lines · Jingoo Han
Quoted 3 lines · Jagan Teki
Quoted 2 lines · Marek Vasut
Quoted 1 line · Mohit Kumar
From: Pratyush Anand <[email protected]>
May be you can apply this patch along with 07/12 of this series. V2 of other patches might get delayed because of vacations.
Regards
Pratyush
PATCH 7/12 pcie: designware: add dw_pcie prefix before cfg_read/write
In reply to Mohit KumarQuoted 10 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
cfg_read/write function are designware pcie specific. Add
dw_pcieprefix to avoid collision in global name space.Signed-off-by Pratyush Anand <[email protected]>Cc Mohit Kumar <[email protected]>Cc Jingoo Han <[email protected]>Cc spear-devel at list.st.comCc linux-pci at vger.kernel.org
Applied to pci/host-designware for v3.14, with these acks:
Thanks!
Quoted 126 lines
--- drivers/pci/host/pci-exynos.c | 5 +++-- drivers/pci/host/pcie-designware.c | 23 ++++++++++++++--------- drivers/pci/host/pcie-designware.h | 4 ++-- 3 files changed, 19 insertions(+), 13 deletions(-)drivers/pci/host/pci-exynos.c +3
-2@@ -468,7 +468,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,int ret;exynos_pcie_sideband_dbi_r_mode (pp, true); - ret =cfg_read (pp->dbi_base + (where & ~0x3 ), where, size, val); + ret =dw_pcie_cfg_read (pp->dbi_base + (where & ~0x3 ), where, size, val);exynos_pcie_sideband_dbi_r_mode (pp, false);return ret; }@@ -479,7 +479,8 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,int ret;exynos_pcie_sideband_dbi_w_mode (pp, true); - ret =cfg_write (pp->dbi_base + (where & ~0x3 ), where, size, val); + ret =dw_pcie_cfg_write (pp->dbi_base + (where & ~0x3 ), + where, size, val);exynos_pcie_sideband_dbi_w_mode (pp, false);return ret; }drivers/pci/host/pcie-designware.c +14
-9@@ -32,7 +32,7 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)return sys->private_data; } -int cfg_read (void __iomem *addr,int where,int size,u32 *val) +int dw_pcie_cfg_read (void __iomem *addr,int where,int size,u32 *val) { *val =readl (addr);@@ -46,7 +46,7 @@ int cfg_read(void __iomem *addr, int where, int size, u32 *val)return PCIBIOS_SUCCESSFUL ; } -int cfg_write (void __iomem *addr,int where,int size,u32 val) +int dw_pcie_cfg_write (void __iomem *addr,int where,int size,u32 val) {if (size ==4 )writel (val, addr);@@ -84,7 +84,8 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,if (pp->ops->rd_own_conf) ret = pp->ops->rd_own_conf (pp, where, size, val);else - ret =cfg_read (pp->dbi_base + (where & ~0x3 ), where, size, val); + ret =dw_pcie_cfg_read (pp->dbi_base + (where & ~0x3 ), where, + size, val);return ret; }@@ -97,8 +98,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,if (pp->ops->wr_own_conf) ret = pp->ops->wr_own_conf (pp, where, size, val);else - ret =cfg_write (pp->dbi_base + (where & ~0x3 ), where, size, - val); + ret =dw_pcie_cfg_write (pp->dbi_base + (where & ~0x3 ), where, + size, val);return ret; }@@ -534,11 +535,13 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,if (bus->parent->number == pp->root_bus_nr) {dw_pcie_prog_viewport_cfg0 (pp, busdev); - ret =cfg_read (pp->va_cfg0_base + address, where, size, val); + ret =dw_pcie_cfg_read (pp->va_cfg0_base + address, where, size, + val);dw_pcie_prog_viewport_mem_outbound (pp); }else {dw_pcie_prog_viewport_cfg1 (pp, busdev); - ret =cfg_read (pp->va_cfg1_base + address, where, size, val); + ret =dw_pcie_cfg_read (pp->va_cfg1_base + address, where, size, + val);dw_pcie_prog_viewport_io_outbound (pp); }@@ -557,11 +560,13 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,if (bus->parent->number == pp->root_bus_nr) {dw_pcie_prog_viewport_cfg0 (pp, busdev); - ret =cfg_write (pp->va_cfg0_base + address, where, size, val); + ret =dw_pcie_cfg_write (pp->va_cfg0_base + address, where, size, + val);dw_pcie_prog_viewport_mem_outbound (pp); }else {dw_pcie_prog_viewport_cfg1 (pp, busdev); - ret =cfg_write (pp->va_cfg1_base + address, where, size, val); + ret =dw_pcie_cfg_write (pp->va_cfg1_base + address, where, size, + val);dw_pcie_prog_viewport_io_outbound (pp); }drivers/pci/host/pcie-designware.h +2
-2@@ -66,8 +66,8 @@ struct pcie_host_ops {void (*host_init)(struct pcie_port *pp); }; -int cfg_read (void __iomem *addr,int where,int size,u32 *val); -int cfg_write (void __iomem *addr,int where,int size,u32 val); +int dw_pcie_cfg_read (void __iomem *addr,int where,int size,u32 *val); +int dw_pcie_cfg_write (void __iomem *addr,int where,int size,u32 val);void dw_handle_msi_irq (struct pcie_port *pp);void dw_pcie_msi_init (struct pcie_port *pp);int dw_pcie_link_up (struct pcie_port *pp);Signature · 6 lines
1.7.0.1 -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo at vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
PATCH 8/12 pcie: designware: Fix IO transfers
In reply to Mohit KumarQuoted 17 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
pp->io_basewhich is the input of the outbound IO address translation unit should be the cpu address, it was programmed wrongly to realio address.We should pass
global_io_offsetrather thansys->io_offsettopci_ioremap_io, so we map the new window into the first available spot in the Linux view of the I/O space.We must also pass cpu address instead of realio address to
pci_ioremap_io.This patch fixes above issue. It has been tested with Lecroy PTC in AIC mode and Pericom PI7C9X2G303EL PCIe switch, which does not work otherwise.
Quoted 8 lines
Signed-off-by Pratyush Anand <[email protected]>Tested-by Mohit Kumar <[email protected]>Tested-by Tim Harvey <[email protected]>Cc Arnd Bergmann <[email protected]>Cc Marek Vasut <[email protected]>Cc Richard Zhu <[email protected]>Cc linux-pci at vger.kernel.orgCc spear-devel at list.st.com
Applied to pci/host-designware for v3.14, with these acks:
Thanks!
Quoted 48 lines
--- drivers/pci/host/pcie-designware.c | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-)drivers/pci/host/pcie-designware.c +2
-3@@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp) + global_io_offset); pp->config.io_size =resource_size (&pp->io); pp->config.io_bus_addr = range.pci_addr; + pp->io_base = range.cpu_addr; }if (restype ==IORESOURCE_MEM ) {of_pci_range_to_resource (&range, np, &pp->mem);@@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) pp->cfg0_base = pp->cfg.start; pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size; - pp->io_base = pp->io.start; pp->mem_base = pp->mem.start; pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,@@ -573,7 +573,6 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,return ret; } -static int dw_pcie_valid_config (struct pcie_port *pp,struct pci_bus *bus,int dev) {@@ -667,7 +666,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)if (global_io_offset <SZ_1M && pp->config.io_size >0 ) { sys->io_offset = global_io_offset - pp->config.io_bus_addr; -pci_ioremap_io (sys->io_offset, pp->io.start); +pci_ioremap_io (global_io_offset, pp->io_base); global_io_offset +=SZ_64K ;pci_add_resource_offset (&sys->resources, &pp->io, sys->io_offset);Signature · 6 lines
1.7.0.1 -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo at vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
PATCH 2/12 SPEAr13xx: Move SPEAr1340 definitions to header file
In reply to Arnd BergmannHi Arnd,
Quoted 9 lines
-----Original Message-----
From: Arnd Bergmann [mailto:arnd at arndb.de]
Sent: Sunday, December 15, 2013 12:33 AM
To: Mohit KUMAR DCG
Cc: linux-arm-kernel at lists.infradead.org; linux-pci at vger.kernel.org; Pratyush ANAND; spear-devel; Viresh Kumar
Subject: Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file
Quoted 10 lines
Quoted 9 lines · Mohit KUMAR DCG
Quoted 3 lines
The RST bits should probably go into a
drivers/resetdriver. Not sure what the other registers do, but I'm sure we can find a driver for these too, possibly they should be part of the PHY driver?- Perhaps if we implement phy and reset driver then we may not require to move these definitions and it will address most of your comments on SPEar13xx pcie driver. I am understanding and working on this.l
Though we are almost ready with v2. But few concerns:
There are Spear soc common register used for misc configurations of clock, reset etc for all ips. Few of registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations. For example: sata_miphy_init in arch/arm/mach-spear/spear1340.c also uses these registers.
We have moved all these sata specific spear1340 configurations in a separate driver. On the basis of spear-ahci dt Node this driver's probe is called, which further adds ahci platform driver.
We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in The same driver.
Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework? Or we keep this new driver in arch/arm/mach-spear only.
Regards
Mohit
Quoted 4 lines
Ok, very good.
Arnd
PATCH 2/12 SPEAr13xx: Move SPEAr1340 definitions to header file
Quoted 29 lines · Mohit KUMAR DCG
Hi Arnd,
Quoted 9 lines
-----Original Message-----
From: Arnd Bergmann [mailto:arnd at arndb.de]
Sent: Sunday, December 15, 2013 12:33 AM
To: Mohit KUMAR DCG
Cc: linux-arm-kernel at lists.infradead.org; linux-pci at vger.kernel.org; Pratyush ANAND; spear-devel; Viresh Kumar
Subject: Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header fileQuoted 10 lines
Quoted 9 lines · Mohit KUMAR DCG
Quoted 3 lines
The RST bits should probably go into a
drivers/resetdriver. Not sure what the other registers do, but I'm sure we can find a driver for these too, possibly they should be part of the PHY driver?- Perhaps if we implement phy and reset driver then we may not require to move these definitions and it will address most of your comments on SPEar13xx pcie driver. I am understanding and working on this.l
Though we are almost ready with v2. But few concerns:
There are Spear soc common register used for misc configurations of clock, reset etc for all ips. Few of registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations. For example:
sata_miphy_initinarch/arm/mach-spear/spear1340.calso uses these registers.
Quoted 7 lines
We have moved all these sata specific spear1340 configurations in a separate driver. On the basis of spear-ahci dt Node this driver's probe is called, which further adds ahci platform driver.
We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in The same driver.Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework? Or we keep this new driver in
arch/arm/mach-spearonly.
I think this misc configuration register block resource should be passed to syscon (drivers/mfd/syscon.c) driver.
regmap_update_bits should be used to update these registers and hence to configure pcie/sata settings.
As far as place is concerned, that can be kept into mfd and can be named as spear13xx-syscon.c
Whats your opinion arnd?
Regards
Pratyush
Quoted 8 lines
Regards
MohitQuoted 4 lines
Ok, very good.
Arnd
PATCH 2/12 SPEAr13xx: Move SPEAr1340 definitions to header file
Quoted 17 lines · Pratyush Anand
Quoted 6 lines
Though we are almost ready with v2. But few concerns:
There are Spear soc common register used for misc configurations of clock, reset etc for all ips. Few of registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations. For example:
sata_miphy_initinarch/arm/mach-spear/spear1340.calso uses these registers.Quoted 7 lines
We have moved all these sata specific spear1340 configurations in a separate driver. On the basis of spear-ahci dt Node this driver's probe is called, which further adds ahci platform driver.
We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in The same driver.Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework? Or we keep this new driver in
arch/arm/mach-spearonly.I think this misc configuration register block resource should be passed to syscon (
drivers/mfd/syscon.c) driver.
Quoted 7 lines
regmap_update_bitsshould be used to update these registers and hence to configure pcie/sata settings.As far as place is concerned, that can be kept into mfd and can be named as
spear13xx-syscon.cWhats your opinion arnd?
That sounds exactly like what I would have suggested, thanks!
One question remains, which is what driver should directly use syscon_regmap_lookup_by_phandle() to get the syscon registers themselves, and which ones should use a higher-level abstraction from spear13xx-syscon.c.
We can decide this on a case-by-case basis, but in general I would suggest to have drivers use syscon_regmap_lookup_by_phandle directly as long as it doesn't cause significant code duplication between drivers.
Arnd
PATCH 2/12 SPEAr13xx: Move SPEAr1340 definitions to header file
Quoted 28 lines · Arnd Bergmann
Quoted 17 lines · Pratyush Anand
Quoted 6 lines
Though we are almost ready with v2. But few concerns:
There are Spear soc common register used for misc configurations of clock, reset etc for all ips. Few of registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations. For example:
sata_miphy_initinarch/arm/mach-spear/spear1340.calso uses these registers.Quoted 7 lines
We have moved all these sata specific spear1340 configurations in a separate driver. On the basis of spear-ahci dt Node this driver's probe is called, which further adds ahci platform driver.
We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in The same driver.Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework? Or we keep this new driver in
arch/arm/mach-spearonly.I think this misc configuration register block resource should be passed to syscon (
drivers/mfd/syscon.c) driver.Quoted 7 lines
regmap_update_bitsshould be used to update these registers and hence to configure pcie/sata settings.As far as place is concerned, that can be kept into mfd and can be named as
spear13xx-syscon.cWhats your opinion arnd?
That sounds exactly like what I would have suggested, thanks!
Quoted 7 lines
One question remains, which is what driver should directly use
syscon_regmap_lookup_by_phandle()to get the syscon registers themselves, and which ones should use a higher-level abstraction fromspear13xx-syscon.c.We can decide this on a case-by-case basis, but in general I would suggest to have drivers use
syscon_regmap_lookup_by_phandledirectly as long as it doesn't cause significant code duplication between drivers.
Yes, I think so.
Regards
Pratyush
Quoted 2 lines
Arnd