PCI: Add SPEAr13xx PCIe support
Subsystems (9)
PATCH v2 1/8 SPEAr13xx: Set dt field entry <stmmac, phy-addr> for phy probe
In reply to Mohit KumarDT field name for the phy address changed since kernel 3.10. Set the snps,phy-addr to 0xffffffff so that the driver probes for the phy.
--- arch/arm/boot/dts/spear13xx.dtsi | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
arch/arm/boot/dts/spear13xx.dtsi +1 -0
@@ -155,6 +155,7 @@ gmac0: eth at e2000000 { compatible = "st,spear600-gmac"; + snps,phy-addr = <0xffffffff>; reg = <0xe2000000 0x8000>; interrupts = <0 33 0x4 0 34 0x4>;
Signature · 1 line
1.7.0.1
PATCH v2 2/8 SPEAr13xx: defconfig: Update
In reply to Mohit KumarEnable EABI, OEABI, VFP and NFS configs in default configuration file for SPEAr13xx.
--- arch/arm/configs/spear13xx_defconfig | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-)
arch/arm/configs/spear13xx_defconfig +14 -0
@@ -14,10 +14,19 @@ CONFIG_MACH_SPEAR1340=y CONFIG_SMP=y # CONFIG_SMP_ON_UP is not set # CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_VFP=y CONFIG_BINFMT_MISC=y CONFIG_NET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_OF_PARTS=y
@@ -27,6 +36,7 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_SD=y CONFIG_ATA=y # CONFIG_SATA_PMP is not set CONFIG_SATA_AHCI_PLATFORM=y
@@ -66,6 +76,7 @@ CONFIG_USB=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SPEAR=y
@@ -79,11 +90,14 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_SECURITY=y CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=y CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m
Signature · 1 line
1.7.0.1
PATCH v2 3/8 ahci: Add a driver_data field to struct ahci_platform_data
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
Platform functions passed to the driver may also need some private data. Till, now following approaches have been taken to manage these data:
-- SPEAr13xx platform keep it locally in the files defining platform functions.
-- IMX has created a new ahci platform device as a child of platform device created by DT and then attached this data as the driver_data of ahci's dev->parent.
Adding a driver_data field helps in using the same platform driver as that of created by DT.
--- include/linux/ahci_platform.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
include/linux/ahci_platform.h +1 -0
@@ -28,6 +28,7 @@ struct ahci_platform_data {const struct ata_port_info *ata_port_info;unsigned int force_port_map;unsigned int mask_port_map; + void *driver_data; };#endif /* _AHCI_PLATFORM_H */
Signature · 1 line
1.7.0.1
PATCH v2 4/8 SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to system cfg driver
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
ahci driver needs some platform specific functions which are called at init, exit, suspend and resume conditions. Till now these functions were present in a platform driver with a fixme notes. These functions modifies only misc registers and not any phy register. Same misc registers will also be modified in case of PCIe driver initialization.
Therefore, moving those code from mach-spear/spear1340.c to mfd/spear13xx-cfg.c.
Same file can further be used to add PCIe system configuration part.
--- arch/arm/boot/dts/spear13xx.dtsi | 9 ++ arch/arm/mach-spear/Kconfig | 1 + arch/arm/mach-spear/spear1340.c | 127 +-------------------- drivers/mfd/Makefile | 1 + drivers/mfd/spear13xx-cfg.c | 239 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 251 insertions(+), 126 deletions(-) create mode 100644 drivers/mfd/spear13xx-cfg.c
arch/arm/boot/dts/spear13xx.dtsi +9 -0
@@ -78,6 +78,10 @@ status = "disabled"; }; + cfg { + compatible = "st,spear13xx-cfg"; + }; + ahb { #address-cells = <1>; #size-cells = <1>;
@@ -221,6 +225,11 @@ 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>; + misc: misc at e0700000 { + compatible = "st,spear13xx-misc", "syscon"; + reg = <0xe0700000 0x1000>; + }; + gpio0: gpio at e0600000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xe0600000 0x1000>;
arch/arm/mach-spear/Kconfig +1 -0
@@ -26,6 +26,7 @@ config ARCH_SPEAR13XX select MIGHT_HAVE_CACHE_L2X0 select PINCTRL select USE_OF + select MFD_SYSCON help Supports for ARM's SPEAR13XX family
arch/arm/mach-spear/spear1340.c +1 -126
139 lines not on this page · raw message
drivers/mfd/Makefile +1 -0
@@ -164,3 +164,4 @@ obj-$(CONFIG_MFD_RETU) += retu-mfd.o obj-$(CONFIG_MFD_AS3711) += as3711.o obj-$(CONFIG_MFD_AS3722) += as3722.o obj-$(CONFIG_MFD_STW481X) += stw481x.o +obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx-cfg.o
drivers/mfd/spear13xx-cfg.c new file +239 -0
239 lines not on this page · raw message
Signature · 1 line
1.7.0.1
PATCH v2 5/8 clk: SPEAr13xx: Fix pcie clock name
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
Follow dt clock naming convention for PCIe clocks.
--- drivers/clk/spear/spear1310_clock.c | 6 +++--- drivers/clk/spear/spear1340_clock.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-)
drivers/clk/spear/spear1310_clock.c +3 -3
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) clk =clk_register_gate (NULL ,"pcie_sata_0_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_0_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.0" ); +clk_register_clkdev (clk,NULL ,"b1000000.pcie" );clk_register_clkdev (clk,NULL ,"b1000000.ahci" ); clk =clk_register_gate (NULL ,"pcie_sata_1_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_1_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.1" ); +clk_register_clkdev (clk,NULL ,"b1800000.pcie" );clk_register_clkdev (clk,NULL ,"b1800000.ahci" ); clk =clk_register_gate (NULL ,"pcie_sata_2_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_2_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.2" ); +clk_register_clkdev (clk,NULL ,"b4000000.pcie" );clk_register_clkdev (clk,NULL ,"b4000000.ahci" ); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
drivers/clk/spear/spear1340_clock.c +1 -1
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base) clk =clk_register_gate (NULL ,"pcie_sata_clk" ,"ahb_clk" ,0 ,SPEAR1340_PERIP1_CLK_ENB ,SPEAR1340_PCIE_SATA_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie" ); +clk_register_clkdev (clk,NULL ,"b1000000.pcie" );clk_register_clkdev (clk,NULL ,"b1000000.ahci" ); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
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1.7.0.1
PATCH v2 6/8 SPEAr13xx: Fix static mapping table
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr13xx was using virtual address space 0xFE000000 to map physical address space 0xB3000000. pci_remap_io uses 0xFEE00000 as virtual address. So change 0xFE000000 to 0xF9000000.
--- arch/arm/mach-spear/include/mach/spear.h | 4 ++-- arch/arm/mach-spear/spear13xx.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/mach-spear/include/mach/spear.h +2 -2
@@ -52,10 +52,10 @@#ifdef CONFIG_ARCH_SPEAR13XX #define PERIP_GRP2_BASE UL(0xB3000000) -#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) +#define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)#define MCIF_SDHCI_BASE UL(0xB3000000)#define SYSRAM0_BASE UL(0xB3800000) -#define VA_SYSRAM0_BASE IOMEM(0xFE800000) +#define VA_SYSRAM0_BASE IOMEM(0xF9800000)#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)#define PERIP_GRP1_BASE UL(0xE0000000)
arch/arm/mach-spear/spear13xx.c +1 -1
@@ -52,10 +52,10 @@ void __init spear13xx_l2x0_init(void)/* * Following will create 16MB static virtual/physical mappings * PHYSICAL VIRTUAL -* 0xB3000000 0xFE000000 * 0xE0000000 0xFD000000 * 0xEC000000 0xFC000000 * 0xED000000 0xFB000000 +* 0xB3000000 0xF9000000 */ struct map_desc spear13xx_io_desc[]__initdata = { {
Signature · 1 line
1.7.0.1
PATCH v2 7/8 pcie: SPEAr13xx: Add designware pcie support
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add SPEAr13xx PCIe driver based on designware controller driver.
SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works for ahci mode.
To use these patches on SPEAr1340/1310 evaluation board, do the necessary modifications on board and enable (okay) pcie from respective evb dtsi file.
--- arch/arm/boot/dts/spear13xx.dtsi | 53 +++++- arch/arm/configs/spear13xx_defconfig | 2 + arch/arm/mach-spear/Kconfig | 1 + drivers/mfd/spear13xx-cfg.c | 205 ++++++++++++++++++ drivers/pci/host/Kconfig | 5 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-spear13xx.c | 394 ++++++++++++++++++++++++++++++++++ 7 files changed, 659 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/host/pcie-spear13xx.c
arch/arm/boot/dts/spear13xx.dtsi +51 -2
@@ -87,8 +87,8 @@ #size-cells = <1>; compatible = "simple-bus"; ranges = <0x50000000 0x50000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x02000000 + 0x80000000 0x80000000 0x20000000 + 0xb0000000 0xb0000000 0x22000000 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>;
@@ -215,6 +215,54 @@ status = "disabled"; }; + pcie@b1000000 { + compatible = "st,spear13xx-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000>; + interrupts = <0 68 0x4>; + pcie_id = <0>; + pcie_is_gen1 = <0>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + + pcie@b1800000 { + compatible = "st,spear13xx-pcie", "snps,dw-pcie"; + reg = <0xb1800000 0x4000>; + interrupts = <0 69 0x4>; + pcie_id = <1>; + pcie_is_gen1 = <0>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + + pcie@b4000000 { + compatible = "st,spear13xx-pcie", "snps,dw-pcie"; + reg = <0xb4000000 0x4000>; + interrupts = <0 70 0x4>; + pcie_id = <2>; + pcie_is_gen1 = <0>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + apb { #address-cells = <1>; #size-cells = <1>;
@@ -343,6 +391,7 @@ reg = <0xe07008c4 0x4>; thermal_flags = <0x7000>; }; + }; }; };
arch/arm/configs/spear13xx_defconfig +2 -0
@@ -11,6 +11,8 @@ CONFIG_ARCH_SPEAR13XX=y CONFIG_MACH_SPEAR1310=y CONFIG_MACH_SPEAR1340=y # CONFIG_SWP_EMULATE is not set +CONFIG_PCI_MSI=y +CONFIG_PCIE_SPEAR13XX=y CONFIG_SMP=y # CONFIG_SMP_ON_UP is not set # CONFIG_ARM_CPU_TOPOLOGY is not set
arch/arm/mach-spear/Kconfig +1 -0
@@ -27,6 +27,7 @@ config ARCH_SPEAR13XX select PINCTRL select USE_OF select MFD_SYSCON + select PCI help Supports for ARM's SPEAR13XX family
drivers/mfd/spear13xx-cfg.c +205 -0
240 lines not on this page · raw message
drivers/pci/host/Kconfig +5 -0
@@ -33,4 +33,9 @@ config PCI_RCAR_GEN2 There are 3 internal PCI controllers available with a single built-in EHCI/OHCI host controller present on each one. +config PCIE_SPEAR13XX + bool "STMicroelectronics SPEAr PCIe controller" + depends on ARCH_SPEAR13XX + select PCIEPORTBUS + select PCIE_DW endmenu
drivers/pci/host/Makefile +1 -0
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o +obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
drivers/pci/host/pcie-spear13xx.c new file +394 -0
394 lines not on this page · raw message
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1.7.0.1
PATCH v2 8/8 MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
In reply to Mohit KumarAdd Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.
--- MAINTAINERS | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)
MAINTAINERS +6 -0
@@ -6462,6 +6462,12 @@ L: [email protected] S: Maintained F: drivers/pci/host/pci-exynos.c +PCIE DRIVER FOR ST SPEAR13XX +M: Mohit Kumar <[email protected]> +L: [email protected] +S: Maintained +F: drivers/pci/host/pcie-spear13xx.c + PCMCIA SUBSYSTEM P: Linux PCMCIA Team L: [email protected]
Signature · 1 line
1.7.0.1
v2 cover PCI: Add SPEAr13xx PCIe support
First five patches are improvement and fixes for SPEAr13xx support.
PCIe driver support for SPEAr1310/40 platform board is added. These patches are tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Modifications for SATA are tested with SPEAr1340-evb board
Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g. pcie designware driver improvements,fixes for IO translation bug, PCIe dw driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA platform code to the system config driver
- Incorporated comments for FUSE_FS option for defconfig
- Incorporated comments to move back the SPEAr1340 definations from .h file
Mohit Kumar (3):
SPEAr13xx: Set dt field entry <stmmac,phy-addr> for phy probe
SPEAr13xx: defconfig: Update
MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
Pratyush Anand (5):
ahci: Add a driver_data field to struct ahci_platform_data
SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to system cfg
driver
clk: SPEAr13xx: Fix pcie clock name
SPEAr13xx: Fix static mapping table
pcie: SPEAr13xx: Add designware pcie support
MAINTAINERS | 6 + arch/arm/boot/dts/spear13xx.dtsi | 63 ++++- arch/arm/configs/spear13xx_defconfig | 16 + arch/arm/mach-spear/Kconfig | 2 + arch/arm/mach-spear/include/mach/spear.h | 4 +- arch/arm/mach-spear/spear1340.c | 127 +--------- arch/arm/mach-spear/spear13xx.c | 2 +- drivers/clk/spear/spear1310_clock.c | 6 +- drivers/clk/spear/spear1340_clock.c | 2 +- drivers/mfd/Makefile | 1 + drivers/mfd/spear13xx-cfg.c | 444 ++++++++++++++++++++++++++++++ drivers/pci/host/Kconfig | 5 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-spear13xx.c | 394 ++++++++++++++++++++++++++ include/linux/ahci_platform.h | 1 + 15 files changed, 939 insertions(+), 135 deletions(-) create mode 100644 drivers/mfd/spear13xx-cfg.c create mode 100644 drivers/pci/host/pcie-spear13xx.c
PATCH v2 3/8 ahci: Add a driver_data field to struct ahci_platform_data
In reply to Mohit Kumarinclude/linux/ahci_platform.h struct ahci_platform_data { · line 31
Quoted 9 lines · Mohit Kumar
include/linux/ahci_platform.h +1
-0@@ -28,6 +28,7 @@ struct ahci_platform_data {const struct ata_port_info *ata_port_info;unsigned int force_port_map;unsigned int mask_port_map; +void *driver_data;
Please use private_data instead for consistency with other ata data structures.
Thanks.
Signature · 1 line
tejun
PATCH v2 6/8 SPEAr13xx: Fix static mapping table
In reply to Mohit KumarQuoted 6 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
SPEAr13xx was using virtual address space
0xFE000000to map physical address space0xB3000000.pci_remap_iouses0xFEE00000as virtual address. So change0xFE000000to0xF9000000.
Quoted 6 lines
Signed-off-by Pratyush Anand <[email protected]>Tested-by Mohit Kumar <[email protected]>Cc Viresh Kumar <[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.orgCc Arnd Bergmann <[email protected]>
Surely this is needed in backports, so please add stable at vger.kernel.org to the Cc list in the changeset text. Otherwise
PATCH v2 4/8 SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to system cfg driver
In reply to Mohit KumarQuoted 5 lines · Mohit Kumar
arch/arm/boot/dts/spear13xx.dtsi +0
-0
arch/arm/boot/dts/spear13xx.dtsi line 87
Quoted 10 lines
arch/arm/boot/dts/spear13xx.dtsi +4
-0@@ -78,6 +78,10 @@ status = "disabled"; }; + cfg { + compatible = "st,spear13xx-cfg"; + }; + ahb { #address-cells = <1>; #size-cells = <1>;
I only saw some of the patches, and did not get a patch with the binding description for this device. Please forward that patch to me, or add it to the series if you didn't have one.
I assume you'd want a phandle pointing to the syscon device in here as well?
Regarding the naming, please do not use 'xx' wildcards in DT compatible strings. Instead, use the exact model name of the first supported version of the hardware (e.g. spear1300 or spear600) that remains compatible. If there are minor variations between the versions, use a list with the most specific version as well as the older ones it's compatible with.
arch/arm/boot/dts/spear13xx.dtsi line 232
Quoted 9 lines
arch/arm/boot/dts/spear13xx.dtsi +5
-0@@ -221,6 +225,11 @@ 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>; + misc: misc at e0700000 { + compatible = "st,spear13xx-misc", "syscon"; + reg = <0xe0700000 0x1000>; + }; +
Same here. Also, I would make this 'misc: syscon at e0700000', since 'misc' does not seem like an appropriate device name.
Quoted 66 lines
arch/arm/boot/dts/spear13xx.dtsi +66
-0+/* SPEAr1340 Registers */ +/* Power Management Registers */ +#define SPEAR1340_PCM_CFG 0x100 + #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800 +#define SPEAR1340_PCM_WKUP_CFG 0x104 +#define SPEAR1340_SWITCH_CTR 0x108 + +#define SPEAR1340_PERIP1_SW_RST 0x318 + #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000 +#define SPEAR1340_PERIP2_SW_RST 0x31C +#define SPEAR1340_PERIP3_SW_RST 0x320 + +/* PCIE - SATA configuration registers */ +#define SPEAR1340_PCIE_SATA_CFG 0x424 + /* PCIE CFG MASks */ + #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11) + #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10) + #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9) + #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8) + #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4) + #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3) + #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2) + #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1) + #define SPEAR1340_PCIE_SATA_SEL_PCIE (0) + #define SPEAR1340_PCIE_SATA_SEL_SATA (1) + #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F + #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \ + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \ + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \ + SPEAR1340_PCIE_CFG_POWERUP_RESET | \ + SPEAR1340_PCIE_CFG_DEVICE_PRESENT) + #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \ + SPEAR1340_SATA_CFG_PM_CLK_EN | \ + SPEAR1340_SATA_CFG_POWERUP_RESET | \ + SPEAR1340_SATA_CFG_RX_CLK_EN | \ + SPEAR1340_SATA_CFG_TX_CLK_EN) + +#define SPEAR1340_PCIE_MIPHY_CFG 0x428 + #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31) + #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27) + #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27) + #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27) + #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0) + #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \ + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ + SPEAR1340_MIPHY_CLK_REF_DIV2 | \ + SPEAR1340_MIPHY_PLL_RATIO_TOP(60)) + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \ + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120)) + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \ + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ + SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) + +struct spear13xx_cfg_priv { + struct regmap *misc; +}; + +/* SATA device registration */ +static void spear1340_sata_miphy_init(struct spear13xx_cfg_priv *cfgpriv) +{ + regmap_update_bits(cfgpriv->misc, SPEAR1340_PCIE_SATA_CFG, + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL); + regmap_update_bits(cfgpriv->misc, SPEAR1340_PCIE_MIPHY_CFG, + SPEAR1340_PCIE_MIPHY_CFG_MASK, + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
arch/arm/boot/dts/spear13xx.dtsi
Quoted 10 lines
arch/arm/boot/dts/spear13xx.dtsi +10
-0+ /* Switch on sata power domain */ + regmap_update_bits(cfgpriv->misc, SPEAR1340_PCM_CFG, + SPEAR1340_PCM_CFG_SATA_POWER_EN, + SPEAR1340_PCM_CFG_SATA_POWER_EN); + msleep(20); + /* Disable PCIE SATA Controller reset */ + regmap_update_bits(cfgpriv->misc, SPEAR1340_PERIP1_SW_RST, + SPEAR1340_PERIP1_SW_RST_SATA, 0); + msleep(20); +}
Looking at the actual code now, this very much looks like it ought to be a "phy" driver and get put in drivers/phy/.
Please see the recent mailing list discussions about making the ahci driver more generic. Once you put this code in a proper phy driver, you should be able to avoid a lot of your workaround and just use the regular ahci-platform driver without any hand-crafted platform data callbacks.
Arnd
PATCH v2 3/8 ahci: Add a driver_data field to struct ahci_platform_data
In reply to Tejun HeoQuoted 13 lines · Tejun Heo
include/linux/ahci_platform.h struct ahci_platform_data { · line 31
Quoted 9 lines · Mohit Kumar
include/linux/ahci_platform.h +1
-0@@ -28,6 +28,7 @@ struct ahci_platform_data {const struct ata_port_info *ata_port_info;unsigned int force_port_map;unsigned int mask_port_map; +void *driver_data;Please use
private_datainstead for consistency with other ata data structures.
Ok.. ll do that in V3.
Thanks for your review.
Regards
Pratyush
Quoted 5 lines
Thanks.
Signature · 1 line
tejun
PATCH v2 6/8 SPEAr13xx: Fix static mapping table
In reply to Arnd BergmannQuoted 14 lines · Arnd Bergmann
Quoted 6 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
SPEAr13xx was using virtual address space
0xFE000000to map physical address space0xB3000000.pci_remap_iouses0xFEE00000as virtual address. So change0xFE000000to0xF9000000.Quoted 6 lines
Signed-off-by Pratyush Anand <[email protected]>Tested-by Mohit Kumar <[email protected]>Cc Viresh Kumar <[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.orgCc Arnd Bergmann <[email protected]>
Quoted 2 lines
Surely this is needed in backports, so please add stable at vger.kernel.org to the Cc list in the changeset text. Otherwise
While sending v3 of series will cc stable list.
Quoted 2 lines
Acked-by Arnd Bergmann <[email protected]>
Thanks :)
Regards
Pratyush
PATCH v2 4/8 SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to system cfg driver
In reply to Arnd BergmannHi Arnd,
Thanks for your valuable comments.
Quoted 9 lines · Arnd Bergmann
Quoted 8 lines · Mohit Kumar
arch/arm/boot/dts/spear13xx.dtsi +0
-0@@ -78,6 +78,10 @@ status = "disabled"; };
Quoted 11 lines
arch/arm/boot/dts/spear13xx.dtsi line 87
Quoted 7 lines
arch/arm/boot/dts/spear13xx.dtsi +4
-0+ cfg { + compatible = "st,spear13xx-cfg"; + }; + ahb { #address-cells = <1>; #size-cells = <1>;I only saw some of the patches, and did not get a patch with the binding description for this device. Please forward that patch to me, or add it to the series if you didn't have one.
It was not there.
Will add a patch for the same in v3.
Quoted 3 lines
I assume you'd want a phandle pointing to the syscon device in here as well?
Since there is only one syscon device in the whole DT, so do I really need to add phandle? Currently I am using syscon_regmap_lookup_by_compatible to find syscon device.
Quoted 7 lines
Regarding the naming, please do not use 'xx' wildcards in DT compatible strings. Instead, use the exact model name of the first supported version of the hardware (e.g. spear1300 or spear600) that remains compatible. If there are minor variations between the versions, use a list with the most specific version as well as the older ones it's compatible with.
Ok..ll take care.
Quoted 5 lines
Quoted 5 lines
arch/arm/boot/dts/spear13xx.dtsi +0
-0@@ -221,6 +225,11 @@ 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>;
Quoted 8 lines
arch/arm/boot/dts/spear13xx.dtsi line 232
Quoted 5 lines
arch/arm/boot/dts/spear13xx.dtsi +5
-0+ misc: misc at e0700000 { + compatible = "st,spear13xx-misc", "syscon"; + reg = <0xe0700000 0x1000>; + }; +Same here. Also, I would make this 'misc: syscon at
e0700000', since 'misc' does not seem like an appropriate device name.
Ok.
Quoted 73 lines
Quoted 73 lines
arch/arm/boot/dts/spear13xx.dtsi +71
-0+/* SPEAr1340 Registers */ +/* Power Management Registers */ +#define SPEAR1340_PCM_CFG 0x100 + #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800 +#define SPEAR1340_PCM_WKUP_CFG 0x104 +#define SPEAR1340_SWITCH_CTR 0x108 + +#define SPEAR1340_PERIP1_SW_RST 0x318 + #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000 +#define SPEAR1340_PERIP2_SW_RST 0x31C +#define SPEAR1340_PERIP3_SW_RST 0x320 + +/* PCIE - SATA configuration registers */ +#define SPEAR1340_PCIE_SATA_CFG 0x424 + /* PCIE CFG MASks */ + #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11) + #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10) + #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9) + #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8) + #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4) + #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3) + #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2) + #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1) + #define SPEAR1340_PCIE_SATA_SEL_PCIE (0) + #define SPEAR1340_PCIE_SATA_SEL_SATA (1) + #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F + #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \ + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \ + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \ + SPEAR1340_PCIE_CFG_POWERUP_RESET | \ + SPEAR1340_PCIE_CFG_DEVICE_PRESENT) + #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \ + SPEAR1340_SATA_CFG_PM_CLK_EN | \ + SPEAR1340_SATA_CFG_POWERUP_RESET | \ + SPEAR1340_SATA_CFG_RX_CLK_EN | \ + SPEAR1340_SATA_CFG_TX_CLK_EN) + +#define SPEAR1340_PCIE_MIPHY_CFG 0x428 + #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31) + #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27) + #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27) + #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27) + #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0) + #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \ + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ + SPEAR1340_MIPHY_CLK_REF_DIV2 | \ + SPEAR1340_MIPHY_PLL_RATIO_TOP(60)) + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \ + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120)) + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \ + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ + SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) + +struct spear13xx_cfg_priv { + struct regmap *misc; +}; + +/* SATA device registration */ +static void spear1340_sata_miphy_init(struct spear13xx_cfg_priv *cfgpriv) +{ + regmap_update_bits(cfgpriv->misc, SPEAR1340_PCIE_SATA_CFG, + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL); + regmap_update_bits(cfgpriv->misc, SPEAR1340_PCIE_MIPHY_CFG, + SPEAR1340_PCIE_MIPHY_CFG_MASK, + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK); + /* Switch on sata power domain */ + regmap_update_bits(cfgpriv->misc, SPEAR1340_PCM_CFG, + SPEAR1340_PCM_CFG_SATA_POWER_EN, + SPEAR1340_PCM_CFG_SATA_POWER_EN); + msleep(20);
Quoted 8 lines
arch/arm/boot/dts/spear13xx.dtsi
Quoted 5 lines
arch/arm/boot/dts/spear13xx.dtsi +5
-0+ /* Disable PCIE SATA Controller reset */ + regmap_update_bits(cfgpriv->misc, SPEAR1340_PERIP1_SW_RST, + SPEAR1340_PERIP1_SW_RST_SATA, 0); + msleep(20); +}Looking at the actual code now, this very much looks like it ought to be a "phy" driver and get put in
drivers/phy/.
Actually these registers are part of common system configurations register space (called as misc space) for SPEAr SOC. So we opted for syscon framework.
PHY registers space starts from 0xEB800000, which can be programmed for various phy specific functions like power management, tx/rx settings, comparator settings etc. In most of the cases phy works with default settings, however there are few exceptions for which we will be adding a phy driver for further improvement of SPEAr drivers.
Regards
Pratyush
Quoted 8 lines
Please see the recent mailing list discussions about making the ahci driver more generic. Once you put this code in a proper phy driver, you should be able to avoid a lot of your workaround and just use the regular ahci-platform driver without any hand-crafted platform data callbacks.
Arnd
PATCH v2 1/8 SPEAr13xx: Set dt field entry <stmmac,phy-addr> for phy probe
In reply to Mohit KumarQuoted 18 lines · Mohit Kumar
DT field name for the phy address changed since kernel 3.10. Set the snps,phy-addr to
0xffffffffso that the driver probes for the phy.Signed-off-by Mohit Kumar <[email protected]>Cc Pratyush Anand <[email protected]>Cc Viresh Kumar <[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.orgCc devicetree at vger.kernel.org--- arch/arm/boot/dts/spear13xx.dtsi | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)arch/arm/boot/dts/spear13xx.dtsi +0
-0
arch/arm/boot/dts/spear13xx.dtsi line 161
Quoted 7 lines
arch/arm/boot/dts/spear13xx.dtsi +1
-0@@ -155,6 +155,7 @@ gmac0: eth at e2000000 { compatible = "st,spear600-gmac"; + snps,phy-addr = <0xffffffff>; reg = <0xe2000000 0x8000>; interrupts = <0 33 0x4 0 34 0x4>;
PATCH v2 2/8 SPEAr13xx: defconfig: Update
In reply to Mohit KumarQuoted 9 lines · Mohit Kumar
Enable EABI, OEABI, VFP and NFS configs in default configuration file for SPEAr13xx.
Signed-off-by Pratyush Anand <[email protected]>Signed-off-by Mohit Kumar <[email protected]>Cc Mohit Kumar <[email protected]>Cc Viresh Kumar <[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.org
PATCH v2 5/8 clk: SPEAr13xx: Fix pcie clock name
In reply to Mohit KumarQuoted 10 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
Follow dt clock naming convention for PCIe clocks.
Signed-off-by Pratyush Anand <[email protected]>Tested-by Mohit Kumar <[email protected]>Cc Viresh Kumar <[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.orgCc Arnd Bergmann <[email protected]>
Quoted 4 lines
--- drivers/clk/spear/spear1310_clock.c | 6 +++--- drivers/clk/spear/spear1340_clock.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-)
PATCH v2 6/8 SPEAr13xx: Fix static mapping table
In reply to Mohit KumarQuoted 39 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
SPEAr13xx was using virtual address space
0xFE000000to map physical address space0xB3000000.pci_remap_iouses0xFEE00000as virtual address. So change0xFE000000to0xF9000000.Signed-off-by Pratyush Anand <[email protected]>Tested-by Mohit Kumar <[email protected]>Cc Viresh Kumar <[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.orgCc Arnd Bergmann <[email protected]>--- arch/arm/mach-spear/include/mach/spear.h | 4 ++-- arch/arm/mach-spear/spear13xx.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)arch/arm/mach-spear/include/mach/spear.h +2
-2@@ -52,10 +52,10 @@#ifdef CONFIG_ARCH_SPEAR13XX #define PERIP_GRP2_BASE UL(0xB3000000) -#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) +#define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)#define MCIF_SDHCI_BASE UL(0xB3000000)#define SYSRAM0_BASE UL(0xB3800000) -#define VA_SYSRAM0_BASE IOMEM(0xFE800000) +#define VA_SYSRAM0_BASE IOMEM(0xF9800000)#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)#define PERIP_GRP1_BASE UL(0xE0000000)arch/arm/mach-spear/spear13xx.c +0
-0
arch/arm/mach-spear/spear13xx.c void __init spear13xx_l2x0_init(void) · line 58
Quoted 8 lines
arch/arm/mach-spear/spear13xx.c +1
-1@@ -52,10 +52,10 @@ void __init spear13xx_l2x0_init(void)/* * Following will create 16MB static virtual/physical mappings * PHYSICAL VIRTUAL -* 0xB3000000 0xFE000000 * 0xE0000000 0xFD000000 * 0xEC000000 0xFC000000 * 0xED000000 0xFB000000 +* 0xB3000000 0xF9000000
Why have you moved this to bottom of list? It was probably kept in increasing order and so please keep the same.
Other than that:
PATCH v2 6/8 SPEAr13xx: Fix static mapping table
Quoted 44 lines · Viresh Kumar
Quoted 43 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
SPEAr13xx was using virtual address space
0xFE000000to map physical address space0xB3000000.pci_remap_iouses0xFEE00000as virtual address. So change0xFE000000to0xF9000000.Signed-off-by Pratyush Anand <[email protected]>Tested-by Mohit Kumar <[email protected]>Cc Viresh Kumar <[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.orgCc Arnd Bergmann <[email protected]>--- arch/arm/mach-spear/include/mach/spear.h | 4 ++-- arch/arm/mach-spear/spear13xx.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)arch/arm/mach-spear/include/mach/spear.h +2
-2@@ -52,10 +52,10 @@#ifdef CONFIG_ARCH_SPEAR13XX #define PERIP_GRP2_BASE UL(0xB3000000) -#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) +#define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)#define MCIF_SDHCI_BASE UL(0xB3000000)#define SYSRAM0_BASE UL(0xB3800000) -#define VA_SYSRAM0_BASE IOMEM(0xFE800000) +#define VA_SYSRAM0_BASE IOMEM(0xF9800000)#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)#define PERIP_GRP1_BASE UL(0xE0000000)arch/arm/mach-spear/spear13xx.c +0
-1@@ -52,10 +52,10 @@ void __init spear13xx_l2x0_init(void)/* * Following will create 16MB static virtual/physical mappings * PHYSICAL VIRTUAL -* 0xB3000000 0xFE000000
Quoted 8 lines
arch/arm/mach-spear/spear13xx.c void __init spear13xx_l2x0_init(void) · line 58
Quoted 4 lines
arch/arm/mach-spear/spear13xx.c +1
-0* 0xE0000000 0xFD000000 * 0xEC000000 0xFC000000 * 0xED000000 0xFB000000 +* 0xB3000000 0xF9000000 Why have you moved this to bottom of list? It was probably kept in increasing order and so please keep the same.
Oh,yes..ll be corrected in v3 of series.
Quoted 4 lines
Other than that:
Acked-by Viresh Kumar <[email protected]>
Thanks.
Regards
Pratyush
PATCH v2 1/8 SPEAr13xx: Set dt field entry <stmmac,phy-addr> for phy probe
In reply to Viresh KumarHi,
Quoted 3 lines · Viresh Kumar
Quoted 2 lines · Mohit Kumar
DT field name for the phy address changed since kernel 3.10. Set the snps,phy-addr to
0xffffffffso that the driver probes for the phy.
This will no longer be required. The default behavior for DT based setups has been changed to auto-detecting the phy.
See http://patchwork.ozlabs.org/patch/312063/
Cheers
ChenYu
Quoted 30 lines
Quoted 16 lines
Signed-off-by Mohit Kumar <[email protected]>Cc Pratyush Anand <[email protected]>Cc Viresh Kumar <[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.orgCc devicetree at vger.kernel.org--- arch/arm/boot/dts/spear13xx.dtsi | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)arch/arm/boot/dts/spear13xx.dtsi +0
-0arch/arm/boot/dts/spear13xx.dtsi line 161
Quoted 7 lines
arch/arm/boot/dts/spear13xx.dtsi +1
-0@@ -155,6 +155,7 @@ gmac0: eth at e2000000 { compatible = "st,spear600-gmac"; + snps,phy-addr = <0xffffffff>; reg = <0xe2000000 0x8000>; interrupts = <0 33 0x4 0 34 0x4>;Acked-by Viresh Kumar <[email protected]>_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH v2 1/8 SPEAr13xx: Set dt field entry <stmmac,phy-addr> for phy probe
Hello Chen,
Quoted 15 lines
-----Original Message-----
From: wens213 at gmail.com [mailto:wens213 at gmail.com] On Behalf Of Chen-Yu Tsai
Sent: Friday, January 24, 2014 11:33 AM
To: Viresh Kumar
Cc: Mohit KUMAR DCG; Pratyush ANAND; spear-devel; linux-arm- kernel at lists.infradead.org; devicetree
Subject: Re: [PATCH V2 1/8] SPEAr13xx: Set dt field entry <stmmac,phy- addr> for phy probeHi,
Quoted 1 line · Viresh Kumar
On Thu, Jan 23, 2014 at 4:02 PM, Mohit Kumar <[email protected]>
Quoted 9 lines
Quoted 2 lines · wrote:
Quoted 2 lines
DT field name for the phy address changed since kernel 3.10. Set the snps,phy-addr to
0xffffffffso that the driver probes for the phy.This will no longer be required. The default behavior for DT based setups has been changed to auto-detecting the phy.
- Thanks, we will test with your patch and remove this one from v3.
Regards
Mohit
Quoted 35 lines
Cheers
ChenYuQuoted 31 lines
Quoted 17 lines
Signed-off-by Mohit Kumar <[email protected]>Cc Pratyush Anand <[email protected]>Cc Viresh Kumar <[email protected]>Cc spear-devel at list.st.comCc linux-arm-kernel at lists.infradead.orgCc devicetree at vger.kernel.org--- arch/arm/boot/dts/spear13xx.dtsi | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)arch/arm/boot/dts/spear13xx.dtsi +0
-0arch/arm/boot/dts/spear13xx.dtsi line 161
Quoted 7 lines
arch/arm/boot/dts/spear13xx.dtsi +1
-0@@ -155,6 +155,7 @@ gmac0: eth at e2000000 { compatible = "st,spear600-gmac"; + snps,phy-addr = <0xffffffff>; reg = <0xe2000000 0x8000>; interrupts = <0 33 0x4 0 34 0x4>;Acked-by Viresh Kumar <[email protected]>_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH V2 7/8] pcie: SPEAr13xx: Add designware pcie support
In reply to Mohit KumarQuoted 28 lines
-----Original Message-----
From: Mohit Kumar [mailto:[email protected]]
Sent: Thursday, January 23, 2014 7:33 PM
Cc: Pratyush Anand; Mohit Kumar; Jingoo Han; Viresh Kumar; [email protected]; linux- [email protected]
Subject: [PATCH V2 7/8] pcie: SPEAr13xx: Add designware pcie supportFrom: Pratyush Anand <[email protected]>
SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add SPEAr13xx PCIe driver based on designware controller driver.
SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works for ahci mode.
To use these patches on SPEAr1340/1310 evaluation board, do the necessary modifications on board and enable (okay) pcie from respective evb dtsi file.Signed-off-by Pratyush Anand <[email protected]>Signed-off-by Mohit Kumar <[email protected]>Cc Mohit Kumar <[email protected]>Cc Jingoo Han <[email protected]>Cc Viresh Kumar <[email protected]>
Quoted 8 lines
--- arch/arm/boot/dts/spear13xx.dtsi | 53 +++++- arch/arm/configs/spear13xx_defconfig | 2 + arch/arm/mach-spear/Kconfig | 1 + drivers/mfd/spear13xx-cfg.c | 205 ++++++++++++++++++ drivers/pci/host/Kconfig | 5 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-spear13xx.c | 394 ++++++++++++++++++++++++++++++++++
(+cc Thierry Reding)
How about changing the file name to 'pci-spear13xx.c'? Now, all PCI host drivers are using the prefix 'pci-', not 'pcie-'.
According to the Thierry Reding's comment,
"I think we should keep these sorted alphabetically. Also Tegra and Marvell are PCIe controllers but they still use the pci- prefix instead of pcie-. Perhaps it'd be good to keep consistency here? I initially chose pci- because from a software point of view it doesn't matter all that much whether it's PCI or PCIe and because the drivers are part of the PCI subsystem. However if Exynos now uses the pcie- prefix it makes it look like Tegra and Marvell are plain old PCI."
(https://groups.google.com/forum/#!msg/linux.kernel/qtimJoNSc3w/_1aayHaG54YJ)
If there is a special reason, please let us know.
Other things look good. :-)
Thank you.
Best regards,
Jingoo Han
Quoted 2 lines
7 files changed, 659 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/host/pcie-spear13xx.c
Re: [PATCH V2 7/8] pcie: SPEAr13xx: Add designware pcie support
Hi Jingoo Han
Quoted 3 lines · Jingoo Han
Quoted 3 lines
-----Orig,
inal Message-----
Quoted 49 lines
Quoted 25 lines
From: Mohit Kumar [mailto:[email protected]]
Sent: Thursday, January 23, 2014 7:33 PM
Cc: Pratyush Anand; Mohit Kumar; Jingoo Han; Viresh Kumar; [email protected]; linux- [email protected]
Subject: [PATCH V2 7/8] pcie: SPEAr13xx: Add designware pcie supportFrom: Pratyush Anand <[email protected]>
SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add SPEAr13xx PCIe driver based on designware controller driver.
SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works for ahci mode.
To use these patches on SPEAr1340/1310 evaluation board, do the necessary modifications on board and enable (okay) pcie from respective evb dtsi file.Signed-off-by Pratyush Anand <[email protected]>Signed-off-by Mohit Kumar <[email protected]>Cc Mohit Kumar <[email protected]>Cc Jingoo Han <[email protected]>Cc Viresh Kumar <[email protected]>Quoted 8 lines
--- arch/arm/boot/dts/spear13xx.dtsi | 53 +++++- arch/arm/configs/spear13xx_defconfig | 2 + arch/arm/mach-spear/Kconfig | 1 + drivers/mfd/spear13xx-cfg.c | 205 ++++++++++++++++++ drivers/pci/host/Kconfig | 5 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-spear13xx.c | 394 ++++++++++++++++++++++++++++++++++(+cc Thierry Reding)
How about changing the file name to '
pci-spear13xx.c'? Now, all PCI host drivers are using the prefix 'pci-', not 'pcie-'.According to the Thierry Reding's comment,
"I think we should keep these sorted alphabetically. Also Tegra and Marvell are PCIe controllers but they still use the pci- prefix instead of pcie-. Perhaps it'd be good to keep consistency here? I initially chose pci- because from a software point of view it doesn't matter all that much whether it's PCI or PCIe and because the drivers are part of the PCI subsystem. However if Exynos now uses the pcie- prefix it makes it look like Tegra and Marvell are plain old PCI."
(https://groups.google.com/forum/#!msg/linux.kernel/qtimJoNSc3w/_1aayHaG54YJ)
Quoted 1 line
If there is a special reason, please let us know.
Only reason is: SPEAr13xx has also a PCI controller compliant with PCI 2.3 specification. However, there is no plan for developing Linux driver for it, as of now.
Regards
Pratyush
Quoted 11 lines
Other things look good. :-)
Thank you.Best regards,
Jingoo HanQuoted 2 lines
7 files changed, 659 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/host/pcie-spear13xx.c
PATCH v2 4/8 SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to system cfg driver
In reply to Pratyush AnandQuoted 9 lines · Pratyush Anand
Quoted 4 lines · Arnd Bergmann
On Thursday 23 January 2014, Mohit Kumar wrote:
I assume you'd want a phandle pointing to the syscon device in here as well?
Since there is only one syscon device in the whole DT, so do I really need to add phandle? Currently I am using
syscon_regmap_lookup_by_compatibleto find syscon device.
I'd much rather use syscon_regmap_lookup_by_phandle than syscon_regmap_lookup_by_compatible, all the time, since this makes the relationship between the devices explicit.
The phandle method also allows you to pass regmap indexes in the same property, which can be handy if two variants of the chip have the same registers at a different offset.
Quoted 80 lines
Quoted 71 lines
Quoted 71 lines
drivers/mfd/spear13xx-cfg.c new file +71
-0+/* SPEAr1340 Registers */ +/* Power Management Registers */ +#define SPEAR1340_PCM_CFG 0x100 +#define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800 +#define SPEAR1340_PCM_WKUP_CFG 0x104 +#define SPEAR1340_SWITCH_CTR 0x108 + +#define SPEAR1340_PERIP1_SW_RST 0x318 +#define SPEAR1340_PERIP1_SW_RST_SATA 0x1000 +#define SPEAR1340_PERIP2_SW_RST 0x31C +#define SPEAR1340_PERIP3_SW_RST 0x320 + +/* PCIE - SATA configuration registers */ +#define SPEAR1340_PCIE_SATA_CFG 0x424 +/* PCIE CFG MASks */ +#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11) +#define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10) +#define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9) +#define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8) +#define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4) +#define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3) +#define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2) +#define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1) +#define SPEAR1340_PCIE_SATA_SEL_PCIE (0) +#define SPEAR1340_PCIE_SATA_SEL_SATA (1) +#define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F +#define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \ + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \ + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \ + SPEAR1340_PCIE_CFG_POWERUP_RESET | \ + SPEAR1340_PCIE_CFG_DEVICE_PRESENT) +#define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \ + SPEAR1340_SATA_CFG_PM_CLK_EN | \ + SPEAR1340_SATA_CFG_POWERUP_RESET | \ + SPEAR1340_SATA_CFG_RX_CLK_EN | \ + SPEAR1340_SATA_CFG_TX_CLK_EN) + +#define SPEAR1340_PCIE_MIPHY_CFG 0x428 +#define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31) +#define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27) +#define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27) +#define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27) +#define SPEAR1340_MIPHY_PLL_RATIO_TOP (x) (x << 0) +#define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF +#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \ + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ + SPEAR1340_MIPHY_CLK_REF_DIV2 | \ + SPEAR1340_MIPHY_PLL_RATIO_TOP(60)) +#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \ + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120)) +#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \ + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ + SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) + +struct spear13xx_cfg_priv { +struct regmap *misc; +}; + +/* SATA device registration */ +static void spear1340_sata_miphy_init (struct spear13xx_cfg_priv *cfgpriv) +{ +regmap_update_bits (cfgpriv->misc,SPEAR1340_PCIE_SATA_CFG , +SPEAR1340_PCIE_SATA_CFG_MASK ,SPEAR1340_SATA_CFG_VAL ); +regmap_update_bits (cfgpriv->misc,SPEAR1340_PCIE_MIPHY_CFG , +SPEAR1340_PCIE_MIPHY_CFG_MASK , +SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK ); +/* Switch on sata power domain */ +regmap_update_bits (cfgpriv->misc,SPEAR1340_PCM_CFG , +SPEAR1340_PCM_CFG_SATA_POWER_EN , +SPEAR1340_PCM_CFG_SATA_POWER_EN ); +msleep (20 );Quoted 8 lines
drivers/mfd/spear13xx-cfg.c line 97
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drivers/mfd/spear13xx-cfg.c new file +5
-0+/* Disable PCIE SATA Controller reset */ +regmap_update_bits (cfgpriv->misc,SPEAR1340_PERIP1_SW_RST , +SPEAR1340_PERIP1_SW_RST_SATA ,0 ); +msleep (20 ); +}Looking at the actual code now, this very much looks like it ought to be a "phy" driver and get put in
drivers/phy/.
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Actually these registers are part of common system configurations register space (called as misc space) for SPEAr SOC. So we opted for syscon framework.
The use of syscon for this is good, I have no objection to that, and was suggesting that you create a logical "phy" device that uses the misc syscon device as a backend.
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PHY registers space starts from
0xEB800000, which can be programmed for various phy specific functions like power management, tx/rx settings, comparator settings etc. In most of the cases phy works with default settings, however there are few exceptions for which we will be adding a phy driver for further improvement of SPEAr drivers.
I see. So while the code you have here could be expressed as a phy driver by itself, there is another part of the SoC that controls the actual phy. How about if you add the phy device node to DT, and write a driver that doesn't actually program the phy registers for now, but does contain the code that you have posted here. That would give you flexibility for future extensions and at the same time let you remove all SPEAr specific code from the actual AHCI driver by using the generic ahci-platform driver.
Arnd
PATCH v2 4/8 SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to system cfg driver
Hi Arnd,
Quoted 22 lines · Arnd Bergmann
Quoted 9 lines · Pratyush Anand
Quoted 4 lines · Arnd Bergmann
On Thursday 23 January 2014, Mohit Kumar wrote:
I assume you'd want a phandle pointing to the syscon device in here as well?
Since there is only one syscon device in the whole DT, so do I really need to add phandle? Currently I am using
syscon_regmap_lookup_by_compatibleto find syscon device.I'd much rather use
syscon_regmap_lookup_by_phandlethansyscon_regmap_lookup_by_compatible, all the time, since this makes the relationship between the devices explicit.The phandle method also allows you to pass regmap indexes in the same property, which can be handy if two variants of the chip have the same registers at a different offset.
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drivers/mfd/spear13xx-cfg.c new file +2
-0+/* SPEAr1340 Registers */ +/* Power Management Registers */
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Looking at the actual code now, this very much looks like it ought to be a "phy" driver and get put in
drivers/phy/.Actually these registers are part of common system configurations register space (called as misc space) for SPEAr SOC. So we opted for syscon framework.
The use of syscon for this is good, I have no objection to that, and was suggesting that you create a logical "phy" device that uses the misc syscon device as a backend.
Quoted 6 lines
PHY registers space starts from
0xEB800000, which can be programmed for various phy specific functions like power management, tx/rx settings, comparator settings etc. In most of the cases phy works with default settings, however there are few exceptions for which we will be adding a phy driver for further improvement of SPEAr drivers.
Quoted 8 lines
I see. So while the code you have here could be expressed as a phy driver by itself, there is another part of the SoC that controls the actual phy. How about if you add the phy device node to DT, and write a driver that doesn't actually program the phy registers for now, but does contain the code that you have posted here. That would give you flexibility for future extensions and at the same time let you remove all SPEAr specific code from the actual AHCI driver by using the generic ahci-platform driver.
OK..
-- will move all these code to a phy driver.
-- so, no need of a new cfg node as of now.
-- will pass syscon phandle to phy driver.
-- currently will keep ahci platform plugin (as it is here) in phy driver. will remove when generic ahci driver is in place.
Regards
Pratyush
Quoted 7 lines
Arnd
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