PCI: dessignware: fixes and cleanup

PATCH In review Mohit Kumar 2 participants 5 messages Feb 27, 2014 – Apr 4, 2014 PCI

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Mohit Kumar

author

2014-02-27 06:01 UTC #1 lore raw

PATCH v2 1/2 PCI: designware: Fix comment for setting number of lanes

In reply to Mohit Kumar

Corrects comment for setting number of lanes.

Signed-off-by Mohit Kumar <[email protected]>

Acked-by Jingoo Han <[email protected]>

Cc Bjorn Helgaas <[email protected]>

Cc [email protected]

---
 drivers/pci/host/pcie-designware.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

drivers/pci/host/pcie-designware.c +1 -1

index 6d23d8c..391966f 100644
@@ -766,7 +766,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 	u32 membase;
 	u32 memlimit;
 
-	/* set the number of lines as 4 */
+	/* set the number of lanes */
 	dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
 	val &= ~PORT_LINK_MODE_MASK;
 	switch (pp->lanes) {

Signature · 1 line

1.7.3.4

Mohit Kumar

author

2014-02-27 06:02 UTC #0 lore raw

v2 cover PCI: dessignware: fixes and cleanup

This patchset fixes iATU programming sequence and correct some comments.

Changes ssince v1:
- Change ssubject line with proper spacing

Signed-off-by Mohit Kumar <[email protected]>

Cc Jingoo Han <[email protected]>

Cc Bjorn Helgaas <[email protected]>

Cc [email protected]

Mohit Kumar (2):
PCI: designware: Fix comment for setting number of lanes
PCI: designware: Fix iATU programming for cfg1, io and mem viewport

 drivers/pci/host/pcie-designware.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

Signature · 1 line

1.7.3.4

Mohit Kumar

author

2014-02-27 06:02 UTC #2 lore raw

PATCH v2 2/2 PCI: designware: Fix iATU programming for cfg1, io and mem viewport

This patch correct iATU programming for cfg1, io and mem viewport. Enable ATU only after configuring it.

Signed-off-by Mohit Kumar <[email protected]>

Signed-off-by Ajay Khandelwal <[email protected]>

Acked-by Jingoo Han <[email protected]>

Cc Bjorn Helgaas <[email protected]>

Cc [email protected]

---
 drivers/pci/host/pcie-designware.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

drivers/pci/host/pcie-designware.c +3 -3

index 391966f..46f4a19 100644
@@ -522,13 +522,13 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
 	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
 			  PCIE_ATU_VIEWPORT);
 	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 	dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
 	dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
 	dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
 			  PCIE_ATU_LIMIT);
 	dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
 	dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
+	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 }
 
 static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)

@@ -537,7 +537,6 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
 			  PCIE_ATU_VIEWPORT);
 	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 	dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
 	dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
 	dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,

@@ -545,6 +544,7 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
 	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
 			  PCIE_ATU_UPPER_TARGET);
+	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 }
 
 static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)

@@ -553,7 +553,6 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
 			  PCIE_ATU_VIEWPORT);
 	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 	dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
 	dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
 	dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,

@@ -561,6 +560,7 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
 	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
 			  PCIE_ATU_UPPER_TARGET);
+	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 }
 
 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,

Signature · 1 line

1.7.3.4

Mohit KUMAR DCG

author

2014-03-24 04:28 UTC #3 lore raw

In reply to Mohit Kumar

SGVsbG8gQmpvcm4sDQoNClBscyBsb29rIGlmIHRoZXNlIHNtYWxsIHBhdGNoZXMgY2FuIGFsc28g YmUgcGlja2VkIGZvciB5b3VyIHRyZWUuDQoNClRoYW5rcw0KTW9oaXQNCg0KPiAtLS0tLU9yaWdp bmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBNb2hpdCBLVU1BUiBEQ0cNCj4gU2VudDogVGh1cnNk YXksIEZlYnJ1YXJ5IDI3LCAyMDE0IDExOjMxIEFNDQo+IFRvOiBiaGVsZ2Fhc0Bnb29nbGUuY29t DQo+IENjOiBNb2hpdCBLVU1BUiBEQ0c7IEppbmdvbyBIYW47IHNwZWFyLWRldmVsOyBsaW51eC1w Y2lAdmdlci5rZXJuZWwub3JnDQo+IFN1YmplY3Q6IFtQQVRDSCBWMiAwLzJdIFBDSTogZGVzc2ln bndhcmU6IGZpeGVzIGFuZCBjbGVhbnVwDQo+IA0KPiBUaGlzIHBhdGNoc2V0IGZpeGVzIGlBVFUg cHJvZ3JhbW1pbmcgc2VxdWVuY2UgYW5kIGNvcnJlY3Qgc29tZQ0KPiBjb21tZW50cy4NCj4gDQo+ IENoYW5nZXMgc3NpbmNlIHYxOg0KPiAJLSBDaGFuZ2Ugc3N1YmplY3QgbGluZSB3aXRoIHByb3Bl ciBzcGFjaW5nDQo+IA0KPiBTaWduZWQtb2ZmLWJ5OiBNb2hpdCBLdW1hciA8bW9oaXQua3VtYXJA c3QuY29tPg0KPiBDYzogSmluZ29vIEhhbiA8amcxLmhhbkBzYW1zdW5nLmNvbT4NCj4gQ2M6IEJq b3JuIEhlbGdhYXMgPGJoZWxnYWFzQGdvb2dsZS5jb20+DQo+IENjOiBzcGVhci1kZXZlbEBsaXN0 LnN0LmNvbQ0KPiBDYzogbGludXgtcGNpQHZnZXIua2VybmVsLm9yZw0KPiANCj4gTW9oaXQgS3Vt YXIgKDIpOg0KPiAgIFBDSTogZGVzaWdud2FyZTogRml4IGNvbW1lbnQgZm9yIHNldHRpbmcgbnVt YmVyIG9mIGxhbmVzDQo+ICAgUENJOiBkZXNpZ253YXJlOiBGaXggaUFUVSBwcm9ncmFtbWluZyBm b3IgY2ZnMSwgaW8gYW5kIG1lbSB2aWV3cG9ydA0KPiANCj4gIGRyaXZlcnMvcGNpL2hvc3QvcGNp ZS1kZXNpZ253YXJlLmMgfCAgICA4ICsrKystLS0tDQo+ICAxIGZpbGVzIGNoYW5nZWQsIDQgaW5z ZXJ0aW9ucygrKSwgNCBkZWxldGlvbnMoLSkNCj4gDQo+IC0tDQo+IDEuNy4zLjQNCg0K

Bjorn Helgaas

maintainer

2014-04-04 16:06 UTC #4 lore raw

In reply to Mohit Kumar

Quoted 11 lines · Mohit Kumar

This patchset fixes iATU programming sequence and correct some comments.
Changes ssince v1:
- Change ssubject line with proper spacing
Signed-off-by Mohit Kumar <[email protected]>
Cc Jingoo Han <[email protected]>
Cc Bjorn Helgaas <[email protected]>
Cc [email protected]
Cc [email protected]

Quoted 6 lines

Mohit Kumar (2):
PCI: designware: Fix comment for setting number of lanes
PCI: designware: Fix iATU programming for cfg1, io and mem viewport
 drivers/pci/host/pcie-designware.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

I applied both to my pending/host-designware branch, which will be rebased and renamed after v3.15-rc1. Thanks!