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ubs: tegra: two fixes and cleanup

PATCH Superseded Stefan Agner 2 participants 7 messages Feb 22, 2014 – Mar 2, 2014

Subsystems (4)
Arm (32-bit) USB Tegra architecture support USB ehci driver

v4 of 5 Superseded Latest is v5 →

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Stefan Agner

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#0 lore raw

v4 cover ubs: tegra: two fixes and cleanup

Only patch 1 is an actual issue while the second patch is something I stumbled upon, and the third is more about housekeeping.

I descieded to ifdef the driver, I think that this is easier to read and does not mix register access style. The function ehci_get_port_speed however don't get a pointer to the usb_ctlr struct and thouse has to work around that. I don't changed the register access style there because of this reason.

The third patch is optional and implements Stephen's suggestion to merge the USB headers. I'm not sure wheater Tegra124 would also profit from this merge, if yes, I think then its definitely worth doing it.

---
Changes since v3:
- Minor cleanup in USB header file

Changes since v2:
- Split into multiple patches
- Using ifdef to account for differences between Tegra20/Tegra30
- Merging of the header files

Changes since v1:
- Take differences between USBD and other USB ports into account port_sc1

---
Stefan Agner (3):
usb: tegra: fix USB2 powerdown for Tegra30 and later
usb: tegra: fix PHY configuration
usb: tegra: combine header file

 arch/arm/include/asm/arch-tegra/usb.h    | 211 ++++++++++++++++++++++++++++++-
 arch/arm/include/asm/arch-tegra114/usb.h | 156 -----------------------
 arch/arm/include/asm/arch-tegra20/usb.h  | 155 -----------------------
 arch/arm/include/asm/arch-tegra30/usb.h  | 168 ------------------------
 board/nvidia/common/board.c              |   1 -
 drivers/usb/host/ehci-tegra.c            |  28 +++-
 6 files changed, 234 insertions(+), 485 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-tegra114/usb.h
 delete mode 100644 arch/arm/include/asm/arch-tegra20/usb.h
 delete mode 100644 arch/arm/include/asm/arch-tegra30/usb.h
Signature · 1 line
1.8.5.4
author
#1 lore raw

PATCH v4 1/3 usb: tegra: fix USB2 powerdown for Tegra30 and later

Clear the forced powerdown bit in the UTMIP_PLL_CFG2_0 register which brings USB2 in UTMI mode to work. This was clearly missing since the forced powerdown bit is set in reset by default for all USB ports.

Acked-by Stephen Warren <[email protected]>
Signed-off-by Stefan Agner <[email protected]>
---
 drivers/usb/host/ehci-tegra.c | 3 +++
 1 file changed, 3 insertions(+)
drivers/usb/host/ehci-tegra.c +3 -0
index 0b42aa5..20e9297 100644
@@ -461,6 +461,9 @@ static int init_utmi_usb_controller(struct fdt_usb *config)
 		if (config->periph_id == PERIPH_ID_USBD)
 			clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
 				     UTMIP_FORCE_PD_SAMP_A_POWERDOWN);
+		if (config->periph_id == PERIPH_ID_USB2)
+			clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
+				     UTMIP_FORCE_PD_SAMP_B_POWERDOWN);
 		if (config->periph_id == PERIPH_ID_USB3)
 			clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
 				     UTMIP_FORCE_PD_SAMP_C_POWERDOWN);
Signature · 1 line
1.8.5.4
author
#2 lore raw

PATCH v4 2/3 usb: tegra: fix PHY configuration

In reply to Stefan Agner

On Tegra30 and later, the PTS (parallel transceiver select) and STS (serial transceiver select) are part of the HOSTPC1_DEVLC_0 register rather than PORTSC1_0 register. Since the reset configuration usually matches the intended configuration, this error did not show up on Tegra30 devices.

Also use the slightly different bit fields of first USB, (USBD) on Tegra20 and move those definitions to the Tegra20 specific header file.

Reviewed-by Stephen Warren <[email protected]>
Signed-off-by Stefan Agner <[email protected]>
---
 arch/arm/include/asm/arch-tegra/usb.h   |  5 -----
 arch/arm/include/asm/arch-tegra20/usb.h |  7 ++++++-
 drivers/usb/host/ehci-tegra.c           | 24 +++++++++++++++++++++---
 3 files changed, 27 insertions(+), 9 deletions(-)
arch/arm/include/asm/arch-tegra/usb.h +0 -5
index a1efd07..35d14e9 100644
@@ -91,11 +91,6 @@
 /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
 #define IC_ENB1					(1 << 3)
 
-/* PORTSC1, USB1, defined for Tegra20 */
-#define PTS1_SHIFT				31
-#define PTS1_MASK				(1 << PTS1_SHIFT)
-#define STS1					(1 << 30)
-
 #define PTS_UTMI	0
 #define PTS_RESERVED	1
 #define PTS_ULPI	2
arch/arm/include/asm/arch-tegra20/usb.h +6 -1
index 3d94cc7..bcd6570 100644
@@ -147,9 +147,14 @@ struct usb_ctlr {
 #define ULPI_DIR_TRIMMER_LOAD			(1 << 24)
 #define ULPI_DIR_TRIMMER_SEL(x)			(((x) & 0x7) << 25)
 
+/* PORTSC1, USB1 */
+#define PTS1_SHIFT				31
+#define PTS1_MASK				(1 << PTS1_SHIFT)
+#define STS1					(1 << 30)
+
 /* PORTSC, USB2, USB3 */
 #define PTS_SHIFT		30
 #define PTS_MASK		(3U << PTS_SHIFT)
-
 #define STS			(1 << 29)
+
 #endif /* _TEGRA20_USB_H_ */
drivers/usb/host/ehci-tegra.c +21 -3
index 20e9297..c6b64b2 100644
@@ -486,9 +486,21 @@ static int init_utmi_usb_controller(struct fdt_usb *config)
 	clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
 
 	/* Select UTMI parallel interface */
-	clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+#if defined(CONFIG_TEGRA20)
+	if (config->periph_id == PERIPH_ID_USBD) {
+		clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK,
+				PTS_UTMI << PTS1_SHIFT);
+		clrbits_le32(&usbctlr->port_sc1, STS1);
+	} else {
+		clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+				PTS_UTMI << PTS_SHIFT);
+		clrbits_le32(&usbctlr->port_sc1, STS);
+	}
+#else
+	clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
 			PTS_UTMI << PTS_SHIFT);
-	clrbits_le32(&usbctlr->port_sc1, STS);
+	clrbits_le32(&usbctlr->hostpc1_devlc, STS);
+#endif
 
 	/* Deassert power down state */
 	clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |

@@ -546,7 +558,13 @@ static int init_ulpi_usb_controller(struct fdt_usb *config)
 			ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
 
 	/* Select ULPI parallel interface */
-	clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
+#if defined(CONFIG_TEGRA20)
+	clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+			PTS_ULPI << PTS_SHIFT);
+#else
+	clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
+			PTS_ULPI << PTS_SHIFT);
+#endif
 
 	/* enable ULPI transceiver */
 	setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
Signature · 1 line
1.8.5.4
author
#3 lore raw

PATCH v4 3/3 usb: tegra: combine header file

In reply to Stefan Agner

Combine the Tegra USB header file into one header file for all SoCs. Use ifdef to account for the difference, especially Tegra20 is quite different from newer SoCs. This avoids duplication especially between Tegra30 and newer devices.

Reviewed-by Stephen Warren <[email protected]>
Signed-off-by Stefan Agner <[email protected]>
---
 arch/arm/include/asm/arch-tegra/usb.h    | 214 +++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra114/usb.h | 156 ----------------------
 arch/arm/include/asm/arch-tegra20/usb.h  | 160 -----------------------
 arch/arm/include/asm/arch-tegra30/usb.h  | 168 ------------------------
 board/nvidia/common/board.c              |   1 -
 drivers/usb/host/ehci-tegra.c            |   1 -
 6 files changed, 214 insertions(+), 486 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-tegra114/usb.h
 delete mode 100644 arch/arm/include/asm/arch-tegra20/usb.h
 delete mode 100644 arch/arm/include/asm/arch-tegra30/usb.h
arch/arm/include/asm/arch-tegra/usb.h +214 -0
index 35d14e9..a22d593 100644
@@ -8,6 +8,189 @@
 #ifndef _TEGRA_USB_H_
 #define _TEGRA_USB_H_
 
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+	/* 0x000 */
+	uint id;
+	uint reserved0;
+	uint host;
+	uint device;
+
+	/* 0x010 */
+	uint txbuf;
+	uint rxbuf;
+	uint reserved1[2];
+
+	/* 0x020 */
+	uint reserved2[56];
+
+	/* 0x100 */
+	u16 cap_length;
+	u16 hci_version;
+	uint hcs_params;
+	uint hcc_params;
+	uint reserved3[5];
+
+	/* 0x120 */
+	uint dci_version;
+	uint dcc_params;
+	uint reserved4[2];
+
+#ifdef CONFIG_TEGRA20
+	/* 0x130 */
+	uint reserved4_2[4];
+
+	/* 0x140 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x150 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint async_tt_sts;
+
+	/* 0x160 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;   /* is this port_sc1 on some controllers? */
+	uint icusb_ctrl;
+
+	/* 0x170 */
+	uint ulpi_viewport;
+	uint reserved7;
+	uint endpt_nak;
+	uint endpt_nak_enable;
+
+	/* 0x180 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x1a0 */
+	uint reserved9;
+	uint otgsc;
+	uint usb_mode;
+	uint endpt_setup_stat;
+
+	/* 0x1b0 */
+	uint reserved10[20];
+
+	/* 0x200 */
+	uint reserved11[0x80];
+#else
+	/* 0x130 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x140 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint reserved5_1;
+
+	/* 0x150 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;
+	uint icusb_ctrl;
+
+	/* 0x160 */
+	uint ulpi_viewport;
+	uint reserved7[3];
+
+	/* 0x170 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x190 */
+	uint reserved9[8];
+
+	/* 0x1b0 */
+	uint reserved10;
+	uint hostpc1_devlc;
+	uint reserved10_1[2];
+
+	/* 0x1c0 */
+	uint reserved10_2[4];
+
+	/* 0x1d0 */
+	uint reserved10_3[4];
+
+	/* 0x1e0 */
+	uint reserved10_4[4];
+
+	/* 0x1f0 */
+	uint reserved10_5;
+	uint otgsc;
+	uint usb_mode;
+	uint reserved10_6;
+
+	/* 0x200 */
+	uint endpt_nak;
+	uint endpt_nak_enable;
+	uint endpt_setup_stat;
+	uint reserved11_1[0x7D];
+#endif
+
+	/* 0x400 */
+	uint susp_ctrl;
+	uint phy_vbus_sensors;
+	uint phy_vbus_wakeup_id;
+	uint phy_alt_vbus_sys;
+
+#ifdef CONFIG_TEGRA20
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[4];
+
+	/* 0x424 */
+	uint ulpi_timing_ctrl_0;
+	uint ulpi_timing_ctrl_1;
+	uint reserved13[53];
+#else
+
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[3];
+
+	/* 0x420 */
+	uint reserved13[56];
+#endif
+
+	/* 0x500 */
+	uint reserved14[64 * 3];
+
+	/* 0x800 */
+	uint utmip_pll_cfg0;
+	uint utmip_pll_cfg1;
+	uint utmip_xcvr_cfg0;
+	uint utmip_bias_cfg0;
+
+	/* 0x810 */
+	uint utmip_hsrx_cfg0;
+	uint utmip_hsrx_cfg1;
+	uint utmip_fslsrx_cfg0;
+	uint utmip_fslsrx_cfg1;
+
+	/* 0x820 */
+	uint utmip_tx_cfg0;
+	uint utmip_misc_cfg0;
+	uint utmip_misc_cfg1;
+	uint utmip_debounce_cfg0;
+
+	/* 0x830 */
+	uint utmip_bat_chrg_cfg0;
+	uint utmip_spare_cfg0;
+	uint utmip_xcvr_cfg1;
+	uint utmip_bias_cfg1;
+};
+
 /* USB1_LEGACY_CTRL */
 #define USB1_NO_LEGACY_MODE		1
 

@@ -27,6 +210,20 @@
 /* USB2_IF_USB_SUSP_CTRL_0 */
 #define ULPI_PHY_ENB				(1 << 13)
 
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
+/* USB2_IF_ULPI_TIMING_CTRL_0 */
+#define ULPI_OUTPUT_PINMUX_BYP			(1 << 10)
+#define ULPI_CLKOUT_PINMUX_BYP			(1 << 11)
+
+/* USB2_IF_ULPI_TIMING_CTRL_1 */
+#define ULPI_DATA_TRIMMER_LOAD			(1 << 0)
+#define ULPI_DATA_TRIMMER_SEL(x)		(((x) & 0x7) << 1)
+#define ULPI_STPDIRNXT_TRIMMER_LOAD		(1 << 16)
+#define ULPI_STPDIRNXT_TRIMMER_SEL(x)	(((x) & 0x7) << 17)
+#define ULPI_DIR_TRIMMER_LOAD			(1 << 24)
+#define ULPI_DIR_TRIMMER_SEL(x)			(((x) & 0x7) << 25)
+#endif
+
 /* USBx_UTMIP_MISC_CFG0 */
 #define UTMIP_SUSPEND_EXIT_ON_EDGE		(1 << 22)
 

@@ -91,6 +288,23 @@
 /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
 #define IC_ENB1					(1 << 3)
 
+#ifdef CONFIG_TEGRA20
+/* PORTSC1, USB1 */
+#define PTS1_SHIFT				31
+#define PTS1_MASK				(1 << PTS1_SHIFT)
+#define STS1					(1 << 30)
+
+/* PORTSC, USB2, USB3 */
+#define PTS_SHIFT		30
+#define PTS_MASK		(3U << PTS_SHIFT)
+#define STS			(1 << 29)
+#else
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_SHIFT				29
+#define PTS_MASK				(0x7U << PTS_SHIFT)
+#define STS						(1 << 28)
+#endif
+
 #define PTS_UTMI	0
 #define PTS_RESERVED	1
 #define PTS_ULPI	2
arch/arm/include/asm/arch-tegra114/usb.h deleted +0 -156

156 lines not on this page · raw message

arch/arm/include/asm/arch-tegra20/usb.h deleted +0 -160

160 lines not on this page · raw message

arch/arm/include/asm/arch-tegra30/usb.h deleted +0 -168

168 lines not on this page · raw message

board/nvidia/common/board.c +0 -1
index e650fed..a07fccc 100644
@@ -31,7 +31,6 @@
 #endif
 #ifdef CONFIG_USB_EHCI_TEGRA
 #include <asm/arch-tegra/usb.h>
-#include <asm/arch/usb.h>
 #include <usb.h>
 #endif
 #ifdef CONFIG_TEGRA_MMC
drivers/usb/host/ehci-tegra.c +0 -1
index c6b64b2..38db18e 100644
@@ -13,7 +13,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch-tegra/usb.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch/usb.h>
 #include <usb.h>
 #include <usb/ulpi.h>
 #include <libfdt.h>
Signature · 1 line
1.8.5.4
#4 lore raw

PATCH v4 3/3 usb: tegra: combine header file

Quoted 7 lines · Stefan Agner

Combine the Tegra USB header file into one header file for all SoCs. Use ifdef to account for the difference, especially Tegra20 is quite different from newer SoCs. This avoids duplication especially between Tegra30 and newer devices.

Reviewed-by Stephen Warren <[email protected]>
Signed-off-by Stefan Agner <[email protected]>
Quoted 7 lines
---
 arch/arm/include/asm/arch-tegra/usb.h    | 214 +++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra114/usb.h | 156 ----------------------
 arch/arm/include/asm/arch-tegra20/usb.h  | 160 -----------------------
 arch/arm/include/asm/arch-tegra30/usb.h  | 168 ------------------------
 board/nvidia/common/board.c              |   1 -
 drivers/usb/host/ehci-tegra.c            |   1 -

Are you planning on sending a later patch which removes arch/arm/include/asm/arch-tegra124/usb.h too?

author
#5 lore raw

PATCH v4 3/3 usb: tegra: combine header file

Am 2014-02-24 19:43, schrieb Stephen Warren:

Quoted 2 lines

Are you planning on sending a later patch which removes arch/arm/include/asm/arch-tegra124/usb.h too?

I did not noticed that file, I created the patch on top of upstream U-Boot. In which branch/repo can I find this file? git.denx.de seems to be down at the moment...

#6 lore raw

PATCH v4 3/3 usb: tegra: combine header file

Quoted 7 lines · Stefan Agner

Am 2014-02-24 19:43, schrieb Stephen Warren:

Quoted 2 lines

Are you planning on sending a later patch which removes arch/arm/include/asm/arch-tegra124/usb.h too?

I did not noticed that file, I created the patch on top of upstream U-Boot. In which branch/repo can I find this file? git.denx.de seems to be down at the moment...

It was recently merged into u-boot.git master branch. (It's been in u-boot-tegra.git for a while longer)