Generic IOMMU pooled allocator
Subsystems (2)
v7 cover Generic IOMMU pooled allocator
Changes from patchv6: moved pool_hash initialization to lib/iommu-common.c and cleaned up code duplication from sun4v/sun4u/ldc.
Sowmini (2):
Break up monolithic iommu table/lock into finer graularity pools and
lock
Make sparc64 use scalable lib/iommu-common.c functions
Sowmini Varadhan (1):
Make LDC use common iommu poll management functions
arch/sparc/include/asm/iommu_64.h | 7 +- arch/sparc/kernel/iommu.c | 174 +++++++-------------------- arch/sparc/kernel/iommu_common.h | 8 -- arch/sparc/kernel/ldc.c | 152 ++++++++++-------------- arch/sparc/kernel/pci_sun4v.c | 179 +++++++++++++---------------- include/linux/iommu-common.h | 48 ++++++++ lib/Makefile | 2 +- lib/iommu-common.c | 235 +++++++++++++++++++++++++++++++++++++ 8 files changed, 475 insertions(+), 330 deletions(-) create mode 100644 include/linux/iommu-common.h create mode 100644 lib/iommu-common.c
RFC PATCH v7 1/3 sparc: Break up monolithic iommu table/lock into finer graularity pools and lock
Investigation of multithreaded iperf experiments on an ethernet interface show the iommu->lock as the hottest lock identified by lockstat, with something of the order of 21M contentions out of 27M acquisitions, and an average wait time of 26 us for the lock. This is not efficient. A more scalable design is to follow the ppc model, where the iommu_table has multiple pools, each stretching over a segment of the map, and with a separate lock for each pool. This model allows for better parallelization of the iommu map search.
This patch adds the iommu range alloc/free function infrastructure.
---
v2 changes:
- incorporate David Miller editorial comments: sparc specific fields moved from iommu-common into sparc's iommu_64.h
- make the npools value an input parameter, for the case when the iommu map size is not very large
- cookie_to_index mapping, and optimizations for span-boundary check, for use case such as LDC.
v3: eliminate iommu_sparc, rearrange the ->demap indirection to
be invoked under the pool lock.
v4: David Miller review changes:
- s/IOMMU_ERROR_CODE/DMA_ERROR_CODE
- page_table_map_base and page_table_shift are unsigned long, not u32.
v5: Feedback from [email protected] and [email protected]
- removed ->cookie_to_index and ->demap indirection: caller should invoke these as needed before calling into the generic allocator
v6: Benh/DaveM discussion eliminationg iommu_tbl_ops, but retaining flush_all
optimization.
v7: one-time initialization of pool_hash from iommu_tbl_pool_init()
include/linux/iommu-common.h | 48 +++++++++ lib/Makefile | 2 +- lib/iommu-common.c | 235 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 284 insertions(+), 1 deletions(-) create mode 100644 include/linux/iommu-common.h create mode 100644 lib/iommu-common.c
include/linux/iommu-common.h new file +48 -0
@@ -0,0 +1,48 @@ +#ifndef _LINUX_IOMMU_COMMON_H +#define _LINUX_IOMMU_COMMON_H + +#include <linux/spinlock_types.h> +#include <linux/device.h> +#include <asm/page.h> + +#define IOMMU_POOL_HASHBITS 4 +#define IOMMU_NR_POOLS (1 << IOMMU_POOL_HASHBITS) + +struct iommu_pool { +unsigned long start; +unsigned long end; +unsigned long hint; +spinlock_t lock; +}; + +struct iommu_table { +unsigned long page_table_map_base; +unsigned long page_table_shift; +unsigned long nr_pools; +void (*flush_all)(struct iommu_table *); +unsigned long poolsize; +struct iommu_pool arena_pool[IOMMU_NR_POOLS ]; +u32 flags; +#define IOMMU_HAS_LARGE_POOL 0x00000001 +#define IOMMU_NO_SPAN_BOUND 0x00000002 +struct iommu_pool large_pool; +unsigned long *map; +}; + +extern void iommu_tbl_pool_init (struct iommu_table *iommu, +unsigned long num_entries, +u32 page_table_shift, +void (*flush_all)(struct iommu_table *), +bool large_pool,u32 npools, +bool skip_span_boundary_check); + +extern unsigned long iommu_tbl_range_alloc (struct device *dev, +struct iommu_table *iommu, +unsigned long npages, +unsigned long *handle); + +extern void iommu_tbl_range_free (struct iommu_table *iommu, +u64 dma_addr,unsigned long npages, +unsigned long entry); + +#endif
lib/Makefile +1 -1
@@ -102,7 +102,7 @@ obj-$(CONFIG_AUDIT_GENERIC) += audit.o obj-$(CONFIG_AUDIT_COMPAT_GENERIC) += compat_audit.o obj-$(CONFIG_SWIOTLB) += swiotlb.o -obj-$(CONFIG_IOMMU_HELPER) += iommu-helper.o +obj-$(CONFIG_IOMMU_HELPER) += iommu-helper.o iommu-common.o obj-$(CONFIG_FAULT_INJECTION) += fault-inject.o obj-$(CONFIG_NOTIFIER_ERROR_INJECTION) += notifier-error-inject.o obj-$(CONFIG_CPU_NOTIFIER_ERROR_INJECT) += cpu-notifier-error-inject.o
lib/iommu-common.c new file +235 -0
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Signature · 1 line
1.7.1
RFC PATCH v7 2/3 sparc: Make sparc64 use scalable lib/iommu-common.c functions
In reply to Sowmini VaradhanIn iperf experiments running linux as the Tx side (TCP client) with 10 threads results in a severe performance drop when TSO is disabled, indicating a weakness in the software that can be avoided by using the scalable IOMMU arena DMA allocation.
Baseline numbers before this patch:
with default settings (TSO enabled) : 9-9.5 Gbps
Disable TSO using ethtool- drops badly: 2-3 Gbps.
After this patch, iperf client with 10 threads, can give a throughput of at least 8.5 Gbps, even when TSO is disabled.
---
v2: moved sparc specific fileds into iommu_sparc
v3: converted all sparc users of iommu, so lot of cleanup and streamlining
v4: David Miller review change:
- s/IOMMU_ERROR_CODE/DMA_ERROR_CODE
- reverts pci_impl.h (now that all iommu usage has been converted)
v5: benh/aik feedback modifies the function signatures: pass in
modified args to iommmu_tbl_pool_init() and iommu_tbl_range_free()
v6: removed iommu_tbl_ops. Pass flush_all as function pointer to
iommu_tbl_pool_init
v7: move pool_hash initialization to iommu_tbl_pool_init()
arch/sparc/include/asm/iommu_64.h | 7 +- arch/sparc/kernel/iommu.c | 174 +++++++++--------------------------- arch/sparc/kernel/iommu_common.h | 8 -- arch/sparc/kernel/pci_sun4v.c | 179 ++++++++++++++++-------------------- 4 files changed, 127 insertions(+), 241 deletions(-)
arch/sparc/include/asm/iommu_64.h +3 -4
@@ -16,6 +16,7 @@#define IOPTE_WRITE 0x0000000000000002UL#define IOMMU_NUM_CTXS 4096 +#include <linux/iommu-common.h> struct iommu_arena {unsigned long *map;
@@ -24,11 +25,10 @@ struct iommu_arena { };struct iommu { +struct iommu_table tbl;spinlock_t lock; -struct iommu_arena arena; -void (*flush_all)(struct iommu *); +u32 dma_addr_mask;iopte_t *page_table; -u32 page_table_map_base;unsigned long iommu_control;unsigned long iommu_tsbbase;unsigned long iommu_flush;
@@ -40,7 +40,6 @@ struct iommu {unsigned long dummy_page_pa;unsigned long ctx_lowest_free;DECLARE_BITMAP (ctx_bitmap,IOMMU_NUM_CTXS ); -u32 dma_addr_mask; };struct strbuf {
arch/sparc/kernel/iommu.c +44 -130
350 lines not on this page · raw message
arch/sparc/kernel/iommu_common.h +0 -8
@@ -48,12 +48,4 @@ static inline int is_span_boundary(unsigned long entry, return iommu_is_span_boundary(entry, nr, shift, boundary_size); } -unsigned long iommu_range_alloc (struct device *dev, -struct iommu *iommu, -unsigned long npages, -unsigned long *handle); -void iommu_range_free (struct iommu *iommu, -dma_addr_t dma_addr, -unsigned long npages); -#endif /* _IOMMU_COMMON_H */
arch/sparc/kernel/pci_sun4v.c +80 -99
340 lines not on this page · raw message
Signature · 1 line
1.7.1
RFC PATCH v7 3/3 sparc: Make LDC use common iommu poll management functions
In reply to Sowmini VaradhanNote that this conversion is only being done to consolidate the code and ensure that the common code provides the sufficient abstraction. It is not expected to result in any noticeable performance improvement, as there is typically one ldc_iommu per vnet_port, and each one has 8k entries, with a typical request for 1-4 pages. Thus LDC uses npools = 1.
---
v3: added this file to be a consumer of the common iommu library
v4: removed ->cookie_to_index and ->demap from iommu_tbl_ops and instead
inline these calls into ldc before calling into iommu-common
v6: remove iommu_tbl_ops
v7: move pool_hash initialization to iommu_tbl_pool_init
arch/sparc/kernel/ldc.c | 152 ++++++++++++++++++++--------------------------- 1 files changed, 64 insertions(+), 88 deletions(-)
arch/sparc/kernel/ldc.c +64 -88
@@ -15,6 +15,7 @@#include <linux/list.h> #include <linux/init.h> #include <linux/bitmap.h> +#include <linux/iommu-common.h> #include <asm/hypervisor.h> #include <asm/iommu.h>
@@ -27,6 +28,10 @@#define DRV_MODULE_VERSION "1.1"#define DRV_MODULE_RELDATE "July 22, 2008" +#define COOKIE_PGSZ_CODE 0xf000000000000000ULL +#define COOKIE_PGSZ_CODE_SHIFT 60ULL + + static char version[] DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";#define LDC_PACKET_SIZE 64
@@ -98,10 +103,10 @@ static const struct ldc_mode_ops stream_ops;int ldom_domaining_enabled;struct ldc_iommu { -/* Protects arena alloc/free. */ +/* Protects ldc_unmap. */ spinlock_t lock; -struct iommu_arena arena;struct ldc_mtable_entry *page_table; +struct iommu_table iommu_table; };struct ldc_channel {
@@ -998,31 +1003,59 @@ static void free_queue(unsigned long num_entries, struct ldc_packet *q)free_pages ((unsigned long )q, order); } +static unsigned long ldc_cookie_to_index (u64 cookie,void *arg) +{ +u64 szcode = cookie >>COOKIE_PGSZ_CODE_SHIFT ; +/* struct ldc_iommu *ldc_iommu = (struct ldc_iommu *)arg; */ + + cookie &= ~COOKIE_PGSZ_CODE ; + +return (cookie >> (13ULL + (szcode *3ULL ))); +} + +static void ldc_demap (struct ldc_iommu *iommu,unsigned long id,u64 cookie, +unsigned long entry,unsigned long npages) +{ +struct ldc_mtable_entry *base; +unsigned long i, shift; + + shift = (cookie >>COOKIE_PGSZ_CODE_SHIFT ) *3 ; + base = iommu->page_table + entry; +for (i =0 ; i < npages; i++) { +if (base->cookie) +sun4v_ldc_revoke (id, cookie + (i << shift), + base->cookie); + base->mte =0 ; + } +} +/* XXX Make this configurable... XXX */ #define LDC_IOTABLE_SIZE (8 * 1024) -static int ldc_iommu_init (struct ldc_channel *lp) +static int ldc_iommu_init (const char *name,struct ldc_channel *lp) {unsigned long sz, num_tsb_entries, tsbsize, order; -struct ldc_iommu *iommu = &lp->iommu; +struct ldc_iommu *ldc_iommu = &lp->iommu; +struct iommu_table *iommu = &ldc_iommu->iommu_table;struct ldc_mtable_entry *table;unsigned long hv_err;int err; num_tsb_entries =LDC_IOTABLE_SIZE ; tsbsize = num_tsb_entries *sizeof (struct ldc_mtable_entry ); - -spin_lock_init (&iommu->lock); +spin_lock_init (&ldc_iommu->lock); sz = num_tsb_entries /8 ; sz = (sz +7UL ) & ~7UL ; - iommu->arena.map =kzalloc (sz,GFP_KERNEL ); -if (!iommu->arena.map) { + iommu->map =kzalloc (sz,GFP_KERNEL ); +if (!iommu->map) { printk(KERN_ERR PFX "Alloc of arena map failed, sz=%lu\n", sz);return -ENOMEM ; } - - iommu->arena.limit = num_tsb_entries; +iommu_tbl_pool_init (iommu, num_tsb_entries,PAGE_SHIFT , +NULL , false/* no large pool */ , +1 /* npools */ , + true/* skip span boundary check */ ); order =get_order (tsbsize);
@@ -1037,7 +1070,7 @@ static int ldc_iommu_init(struct ldc_channel *lp)memset (table,0 ,PAGE_SIZE << order); - iommu->page_table = table; + ldc_iommu->page_table = table; hv_err =sun4v_ldc_set_map_table (lp->id,__pa (table), num_tsb_entries);
@@ -1049,31 +1082,32 @@ static int ldc_iommu_init(struct ldc_channel *lp) out_free_table:free_pages ((unsigned long ) table, order); - iommu->page_table =NULL ; + ldc_iommu->page_table =NULL ; out_free_map: -kfree (iommu->arena.map); - iommu->arena.map =NULL ; +kfree (iommu->map); + iommu->map =NULL ;return err; }static void ldc_iommu_release (struct ldc_channel *lp) { -struct ldc_iommu *iommu = &lp->iommu; +struct ldc_iommu *ldc_iommu = &lp->iommu; +struct iommu_table *iommu = &ldc_iommu->iommu_table;unsigned long num_tsb_entries, tsbsize, order; (void )sun4v_ldc_set_map_table (lp->id,0 ,0 ); - num_tsb_entries = iommu->arena.limit; + num_tsb_entries = iommu->poolsize * iommu->nr_pools; tsbsize = num_tsb_entries *sizeof (struct ldc_mtable_entry ); order =get_order (tsbsize); -free_pages ((unsigned long ) iommu->page_table, order); - iommu->page_table =NULL ; +free_pages ((unsigned long ) ldc_iommu->page_table, order); + ldc_iommu->page_table =NULL ; -kfree (iommu->arena.map); - iommu->arena.map =NULL ; +kfree (iommu->map); + iommu->map =NULL ; } struct ldc_channel *ldc_alloc(unsigned long id,
@@ -1140,7 +1174,7 @@ struct ldc_channel *ldc_alloc(unsigned long id, lp->id = id; - err =ldc_iommu_init (lp); + err =ldc_iommu_init (name, lp);if (err) goto out_free_ldc;
@@ -1885,40 +1919,6 @@ int ldc_read(struct ldc_channel *lp, void *buf, unsigned int size) }EXPORT_SYMBOL (ldc_read); -static long arena_alloc (struct ldc_iommu *iommu,unsigned long npages) -{ -struct iommu_arena *arena = &iommu->arena; -unsigned long n, start, end, limit; -int pass; - - limit = arena->limit; - start = arena->hint; - pass =0 ; - -again: - n =bitmap_find_next_zero_area (arena->map, limit, start, npages,0 ); - end = n + npages; -if (unlikely (end >= limit)) { -if (likely (pass <1 )) { - limit = start; - start =0 ; - pass++; - goto again; - }else { -/* Scanned the whole thing, give up. */ -return -1 ; - } - } -bitmap_set (arena->map, n, npages); - - arena->hint = end; - -return n; -} - -#define COOKIE_PGSZ_CODE 0xf000000000000000ULL -#define COOKIE_PGSZ_CODE_SHIFT 60ULL -static u64 pagesize_code (void ) {switch (PAGE_SIZE ) {
@@ -1945,23 +1945,13 @@ static u64 make_cookie(u64 index, u64 pgsz_code, u64 page_offset) page_offset); } -static u64 cookie_to_index (u64 cookie,unsigned long *shift) -{ -u64 szcode = cookie >>COOKIE_PGSZ_CODE_SHIFT ; - - cookie &= ~COOKIE_PGSZ_CODE ; - - *shift = szcode *3 ; - -return (cookie >> (13ULL + (szcode *3ULL ))); -}static struct ldc_mtable_entry *alloc_npages (struct ldc_iommu *iommu,unsigned long npages) {long entry; - entry =arena_alloc (iommu, npages); + entry =iommu_tbl_range_alloc (NULL , &iommu->iommu_table, npages,NULL );if (unlikely (entry <0 ))return NULL ;
@@ -2090,7 +2080,7 @@ int ldc_map_sg(struct ldc_channel *lp, struct ldc_trans_cookie *cookies, int ncookies, unsigned int map_perm) { - unsigned long i, npages, flags; + unsigned long i, npages;struct ldc_mtable_entry *base;struct cookie_state state;struct ldc_iommu *iommu;
@@ -2109,9 +2099,7 @@ int ldc_map_sg(struct ldc_channel *lp, iommu = &lp->iommu; -spin_lock_irqsave (&iommu->lock, flags); base =alloc_npages (iommu, npages); -spin_unlock_irqrestore (&iommu->lock, flags);if (!base)return -ENOMEM ;
@@ -2136,7 +2124,7 @@ int ldc_map_single(struct ldc_channel *lp, struct ldc_trans_cookie *cookies, int ncookies, unsigned int map_perm) { - unsigned long npages, pa, flags; + unsigned long npages, pa;struct ldc_mtable_entry *base;struct cookie_state state;struct ldc_iommu *iommu;
@@ -2152,9 +2140,7 @@ int ldc_map_single(struct ldc_channel *lp, iommu = &lp->iommu; -spin_lock_irqsave (&iommu->lock, flags); base =alloc_npages (iommu, npages); -spin_unlock_irqrestore (&iommu->lock, flags);if (!base)return -ENOMEM ;
@@ -2172,35 +2158,25 @@ int ldc_map_single(struct ldc_channel *lp, }EXPORT_SYMBOL (ldc_map_single); +static void free_npages (unsigned long id,struct ldc_iommu *iommu,u64 cookie,u64 size) { -struct iommu_arena *arena = &iommu->arena; -unsigned long i, shift, index, npages; -struct ldc_mtable_entry *base; +unsigned long npages, entry; npages =PAGE_ALIGN (((cookie & ~PAGE_MASK ) + size)) >>PAGE_SHIFT ; - index =cookie_to_index (cookie, &shift); - base = iommu->page_table + index; -BUG_ON (index > arena->limit || - (index + npages) > arena->limit); - -for (i =0 ; i < npages; i++) { -if (base->cookie) -sun4v_ldc_revoke (id, cookie + (i << shift), - base->cookie); - base->mte =0 ; -__clear_bit (index + i, arena->map); - } + entry =ldc_cookie_to_index (cookie, iommu); +ldc_demap (iommu, id, cookie, entry, npages); +iommu_tbl_range_free (&iommu->iommu_table, cookie, npages, entry); }void ldc_unmap (struct ldc_channel *lp,struct ldc_trans_cookie *cookies,int ncookies) {struct ldc_iommu *iommu = &lp->iommu; -unsigned long flags;int i; +unsigned long flags;spin_lock_irqsave (&iommu->lock, flags);for (i =0 ; i < ncookies; i++) {
Signature · 1 line
1.7.1
David Miller
maintainerFrom: Sowmini Varadhan <[email protected]>
Date: Wed, 25 Mar 2015 13:34:45 -0400
Quoted 3 lines
Changes from patchv6: moved
pool_hashinitialization tolib/iommu-common.cand cleaned up code duplication from sun4v/sun4u/ldc.
Looks good to me.
PowerPC folks, what do you think?
Quoted 10 lines · David Miller
From: Sowmini Varadhan <[email protected]>
Date: Wed, 25 Mar 2015 13:34:45 -0400Quoted 3 lines
Changes from patchv6: moved
pool_hashinitialization tolib/iommu-common.cand cleaned up code duplication from sun4v/sun4u/ldc.Looks good to me.
PowerPC folks, what do you think?
I'll give it another look today.
Cheers,
Ben.
Quoted 6 lines · Benjamin Herrenschmidt
Quoted 1 line
PowerPC folks, what do you think?
I'll give it another look today.
Cheers,
Ben.
Hi Ben,
did you have a chance to look at this?
--Sowmini
Re: [PATCH v7 RFC 1/3] sparc: Break up monolithic iommu table/lock into finer graularity pools and lock
In reply to Sowmini VaradhanQuoted 9 lines · Sowmini Varadhan
Investigation of multithreaded iperf experiments on an ethernet interface show the
iommu->lockas the hottest lock identified by lockstat, with something of the order of 21M contentions out of 27M acquisitions, and an average wait time of 26 us for the lock. This is not efficient. A more scalable design is to follow the ppc model, where theiommu_tablehas multiple pools, each stretching over a segment of the map, and with a separate lock for each pool. This model allows for better parallelization of the iommu map search.
.../...
Quoted 7 lines
include/linux/iommu-common.h new file +0
-0
include/linux/iommu-common.h line 9
Quoted 9 lines
include/linux/iommu-common.h new file +9
-0@@ -0,0 +1,48 @@ +#ifndef _LINUX_IOMMU_COMMON_H +#define _LINUX_IOMMU_COMMON_H + +#include <linux/spinlock_types.h> +#include <linux/device.h> +#include <asm/page.h> + +#define IOMMU_POOL_HASHBITS 4 +#define IOMMU_NR_POOLS (1 << IOMMU_POOL_HASHBITS)
I don't like those macros. You changed the value from what we had on powerpc. It could be that the new values are as good for us but I'd like to do a bit differently. Can you make the bits a variable ? Or at least an arch-provided macro which we can change later if needed ?
include/linux/iommu-common.h line 18
Quoted 8 lines
include/linux/iommu-common.h new file +8
-0+struct iommu_pool { +unsigned long start; +unsigned long end; +unsigned long hint; +spinlock_t lock; +}; + +struct iommu_table {
Let's make it clear that this is for allocation of DMA space only, it would thus make my life easier when adapting powerpc to use a different names, something like "struct iommu_area" works for me, or "iommu alloc_region" .. whatever you fancy the most.
include/linux/iommu-common.h line 20
Quoted 2 lines
include/linux/iommu-common.h new file +2
-0+unsigned long page_table_map_base; +unsigned long page_table_shift;
Minor nit but I'm not fan of the naming here, maybe just use entry_shift ? I don't like too long identifiers :) Same for base, could just be "base" or "table_base".
include/linux/iommu-common.h line 22
Quoted 2 lines
include/linux/iommu-common.h new file +2
-0+unsigned long nr_pools; +void (*flush_all)(struct iommu_table *);
Call this "lazy_flush", document that it is optional and when it is called.
include/linux/iommu-common.h line 24
Quoted 2 lines
include/linux/iommu-common.h new file +2
-0+unsigned long poolsize; +struct iommu_pool arena_pool[IOMMU_NR_POOLS ];
Why adding the 'arena' prefix ? What was wrong with "pools" in the powerpc imlementation ?
Quoted 47 lines
include/linux/iommu-common.h new file +24
-0+u32 flags; +#define IOMMU_HAS_LARGE_POOL 0x00000001 +#define IOMMU_NO_SPAN_BOUND 0x00000002 +struct iommu_pool large_pool; + unsigned long *map; +}; + +extern void iommu_tbl_pool_init (struct iommu_table *iommu, +unsigned long num_entries, +u32 page_table_shift, +void (*flush_all)(struct iommu_table *), +bool large_pool,u32 npools, +bool skip_span_boundary_check); + +extern unsigned long iommu_tbl_range_alloc (struct device *dev, +struct iommu_table *iommu, +unsigned long npages, +unsigned long *handle); + +extern void iommu_tbl_range_free (struct iommu_table *iommu, +u64 dma_addr,unsigned long npages, +unsigned long entry); + +#endif lib/Makefile +1
-1@@ -102,7 +102,7 @@ obj-$(CONFIG_AUDIT_GENERIC) += audit.o obj-$(CONFIG_AUDIT_COMPAT_GENERIC) += compat_audit.o obj-$(CONFIG_SWIOTLB) += swiotlb.o -obj-$(CONFIG_IOMMU_HELPER) += iommu-helper.o +obj-$(CONFIG_IOMMU_HELPER) += iommu-helper.o iommu-common.o obj-$(CONFIG_FAULT_INJECTION) += fault-inject.o obj-$(CONFIG_NOTIFIER_ERROR_INJECTION) += notifier-error-inject.o obj-$(CONFIG_CPU_NOTIFIER_ERROR_INJECT) += cpu-notifier-error-inject.olib/iommu-common.c new file +4
-0@@ -0,0 +1,235 @@ +/* +* IOMMU mmap management and range allocation functions. +* Based almost entirely upon the powerpc iommu allocator. +*/
lib/iommu-common.c line 14
Quoted 10 lines
lib/iommu-common.c new file +10
-0+ +#include <linux/export.h> +#include <linux/bitmap.h> +#include <linux/bug.h> +#include <linux/iommu-helper.h> +#include <linux/iommu-common.h> +#include <linux/dma-mapping.h> +#include <linux/hash.h> + +#define IOMMU_LARGE_ALLOC 15
Make that a variable, here too, the arch might want to tweak it.
I think 15 is actually not a good value for powerpc with 4k iommu pages and 64k PAGE_SIZE, we should make the above some kind of factor of PAGE_SHIFT - iommu_page_shift.
Quoted 75 lines
lib/iommu-common.c new file +75
-0+static DEFINE_PER_CPU(unsigned int, iommu_pool_hash); + +static void setup_iommu_pool_hash (void ) +{ +unsigned int i; +static bool do_once; + +if (do_once) +return ; + do_once = true; +for_each_possible_cpu (i) +per_cpu (iommu_pool_hash, i) =hash_32 (i,IOMMU_POOL_HASHBITS ); +} + +/* +* Initialize iommu_pool entries for the iommu_table. `num_entries' +* is the number of table entries. If `large_pool' is set to true, +* the top 1/4 of the table will be set aside for pool allocations +* of more than IOMMU_LARGE_ALLOC pages. +*/ +extern void iommu_tbl_pool_init (struct iommu_table *iommu, +unsigned long num_entries, +u32 page_table_shift, +void (*flush_all)(struct iommu_table *), +bool large_pool,u32 npools, +bool skip_span_boundary_check) +{ +unsigned int start, i; +struct iommu_pool *p = &(iommu->large_pool); + +setup_iommu_pool_hash (); +if (npools =0 ) + iommu->nr_pools =IOMMU_NR_POOLS ; +else + iommu->nr_pools = npools; +BUG_ON (npools >IOMMU_NR_POOLS ); + + iommu->page_table_shift = page_table_shift; + iommu->flush_all = flush_all; + start =0 ; +if (skip_span_boundary_check) + iommu->flags |=IOMMU_NO_SPAN_BOUND ; +if (large_pool) + iommu->flags |=IOMMU_HAS_LARGE_POOL ; + +if (!large_pool) + iommu->poolsize = num_entries/iommu->nr_pools; +else + iommu->poolsize = (num_entries *3 /4 )/iommu->nr_pools; +for (i =0 ; i < iommu->nr_pools; i++) { +spin_lock_init (&(iommu->arena_pool[i].lock)); + iommu->arena_pool[i].start = start; + iommu->arena_pool[i].hint = start; + start += iommu->poolsize;/* start for next pool */ + iommu->arena_pool[i].end = start -1 ; + } +if (!large_pool) +return ; +/* initialize large_pool */ +spin_lock_init (&(p->lock)); + p->start = start; + p->hint = p->start; + p->end = num_entries; +} +EXPORT_SYMBOL (iommu_tbl_pool_init); + +unsigned long iommu_tbl_range_alloc (struct device *dev, +struct iommu_table *iommu, +unsigned long npages, +unsigned long *handle) +{ +unsigned int pool_hash =__this_cpu_read (iommu_pool_hash); +unsigned long n, end, start, limit, boundary_size; +struct iommu_pool *arena; +int pass =0 ;
lib/iommu-common.c line 100
Quoted 10 lines
lib/iommu-common.c new file +10
-0+unsigned int pool_nr; +unsigned int npools = iommu->nr_pools; +unsigned long flags; +bool large_pool = ((iommu->flags &IOMMU_HAS_LARGE_POOL ) !=0 ); +bool largealloc = (large_pool && npages >IOMMU_LARGE_ALLOC ); +unsigned long shift; + +/* Sanity check */ +if (unlikely (npages =0 )) { +printk_ratelimited ("npages = 0\n" );
You removed the WARN_ON here which had the nice property of giving you a backtrace which points to the offender. The above message alone is useless.
lib/iommu-common.c line 105
Quoted 5 lines
lib/iommu-common.c new file +5
-0+return DMA_ERROR_CODE ; + } + +if (largealloc) { + arena = &(iommu->large_pool);
Nit but here too, why change "pool" to "arena" ?
lib/iommu-common.c line 118
Quoted 13 lines
lib/iommu-common.c new file +13
-0+spin_lock_irqsave (&arena->lock, flags); + pool_nr =0 ;/* to keep compiler happy */ + }else { +/* pick out pool_nr */ + pool_nr = pool_hash & (npools -1 ); + arena = &(iommu->arena_pool[pool_nr]); + +/* find first available unlocked pool */ +while (!spin_trylock_irqsave (&(arena->lock), flags)) { + pool_nr = (pool_nr +1 ) & (iommu->nr_pools -1 ); + arena = &(iommu->arena_pool[pool_nr]); + } + }
I am not certain about the "first unlocked pool"... We take the lock for a fairly short amount of time, I have the gut feeling that the cache line bouncing introduced by looking at a different pool may well cost more than waiting a bit longer. Did do some measurements of that optimisation ?
Quoted 8 lines
lib/iommu-common.c new file +8
-0+ again: +if (pass =0 && handle && *handle && + (*handle >= arena->start) && (*handle < arena->end)) + start = *handle; +else + start = arena->hint; + + limit = arena->end;
lib/iommu-common.c line 137
Quoted 10 lines
lib/iommu-common.c new file +10
-0+ +/* The case below can happen if we have a small segment appended +* to a large, or when the previous alloc was at the very end of +* the available space. If so, go back to the beginning and flush. +*/ +if (start >= limit) { + start = arena->start; +if (!large_pool && iommu->flush_all !=NULL ) + iommu->flush_all (iommu); + }
I am not too fan of the 2 copies of that logic. On the other hand you may have no choice since we do need to do the flush when we wrap even if we end up failing or pool hopping.
Quoted 27 lines
lib/iommu-common.c new file +27
-0+ +if (dev) + boundary_size =ALIGN (dma_get_seg_boundary (dev) +1 , +1 << iommu->page_table_shift); +else + boundary_size =ALIGN (1UL <<32 ,1 << iommu->page_table_shift); + + shift = iommu->page_table_map_base >> iommu->page_table_shift; + boundary_size = boundary_size >> iommu->page_table_shift; +/* +* if the skip_span_boundary_check had been set during init, we set +* things up so that iommu_is_span_boundary() merely checks if the +* (index + npages) < num_tsb_entries +*/ +if ((iommu->flags &IOMMU_NO_SPAN_BOUND ) !=0 ) { + shift =0 ; + boundary_size = iommu->poolsize * iommu->nr_pools; + } + n =iommu_area_alloc (iommu->map, limit, start, npages, shift, + boundary_size,0 ); +if (n =-1 ) { +if (likely (pass =0 )) { +/* First failure, rescan from the beginning. */ + arena->hint = arena->start; +if (!large_pool && iommu->flush_all !=NULL ) + iommu->flush_all (iommu); + pass++;
lib/iommu-common.c line 174
Quoted 10 lines
lib/iommu-common.c new file +10
-0+ goto again; + }else if (!largealloc && pass <= iommu->nr_pools) { +spin_unlock (&(arena->lock)); + pool_nr = (pool_nr +1 ) & (iommu->nr_pools -1 ); + arena = &(iommu->arena_pool[pool_nr]); +while (!spin_trylock (&(arena->lock))) { + pool_nr = (pool_nr +1 ) & (iommu->nr_pools -1 ); + arena = &(iommu->arena_pool[pool_nr]); + } + arena->hint = arena->start;
Here you just "wrapped" that new pool, so you need to do a flush. I'm thinking you should probably use a local "need_flush" bool, which applies to the current pool. You would do a test & call flush before releasing a pool lock (so right above this or on function exit). To make things simpler, the below becomes:
lib/iommu-common.c line 182
Quoted 8 lines
lib/iommu-common.c new file +8
-0+ pass++; + goto again; + }else { +/* give up */ +spin_unlock_irqrestore (&(arena->lock), flags); +return DMA_ERROR_CODE ; + } + }
else {
n = DMA_ERROR_CODE;
goto bail;
}So you have only one exit point.
Quoted 53 lines
lib/iommu-common.c new file +53
-0+ + end = n + npages; + + arena->hint = end; + +/* Update handle for SG allocations */ +if (handle) + *handle = end; +spin_unlock_irqrestore (&(arena->lock), flags); + +return n; +} +EXPORT_SYMBOL (iommu_tbl_range_alloc); + +static struct iommu_pool *get_pool (struct iommu_table *tbl, +unsigned long entry) +{ +struct iommu_pool *p; +unsigned long largepool_start = tbl->large_pool.start; +bool large_pool = ((tbl->flags &IOMMU_HAS_LARGE_POOL ) !=0 ); + +/* The large pool is the last pool at the top of the table */ +if (large_pool && entry >= largepool_start) { + p = &tbl->large_pool; + }else { +unsigned int pool_nr = entry / tbl->poolsize; + +BUG_ON (pool_nr >= tbl->nr_pools); + p = &tbl->arena_pool[pool_nr]; + } +return p; +} + +/* Caller supplies the index of the entry into the iommu map table +* itself when the mapping from dma_addr to the entry is not the +* default addr->entry mapping below. +*/ +void iommu_tbl_range_free (struct iommu_table *iommu,u64 dma_addr, +unsigned long npages,unsigned long entry) +{ +struct iommu_pool *pool; +unsigned long flags; +unsigned long shift = iommu->page_table_shift; + +if (entry =DMA_ERROR_CODE )/* use default addr->entry mapping */ + entry = (dma_addr - iommu->page_table_map_base) >> shift; + pool =get_pool (iommu, entry); + +spin_lock_irqsave (&(pool->lock), flags); +bitmap_clear (iommu->map, entry, npages); +spin_unlock_irqrestore (&(pool->lock), flags); +} +EXPORT_SYMBOL (iommu_tbl_range_free);
Re: [PATCH v7 RFC 1/3] sparc: Break up monolithic iommu table/lock into finer graularity pools and lock
Quoted 8 lines · Benjamin Herrenschmidt
include/linux/iommu-common.h line 9
Quoted 3 lines
include/linux/iommu-common.h new file +3
-0+ +#define IOMMU_POOL_HASHBITS 4 +#define IOMMU_NR_POOLS (1 << IOMMU_POOL_HASHBITS)I don't like those macros. You changed the value from what we had on powerpc. It could be that the new values are as good for us but I'd like to do a bit differently. Can you make the bits a variable ? Or at least an arch-provided macro which we can change later if needed ?
Actuallly, this are just the upper bound (16) on the number of pools.
The actual number is selected by the value passed to the iommu_tbl_range_init(), and is not hard-coded (as was the case with the power-pc code).
Thus powerpc can continue to use 4 pools without any loss of generality.
:
Quoted 4 lines
Let's make it clear that this is for allocation of DMA space only, it would thus make my life easier when adapting powerpc to use a different names, something like "struct
iommu_area" works for me, or "iommualloc_region" .. whatever you fancy the most.
:
Quoted 2 lines
Why adding the 'arena' prefix ? What was wrong with "pools" in the powerpc imlementation ?
for the same reason you want to re-baptize iommu_table above- at the time, I was doing it to minimize conflicts with existing usage. But I can rename everything if you like.
Quoted 7 lines
Quoted 1 line
+#define
IOMMU_LARGE_ALLOC15Make that a variable, here too, the arch might want to tweak it.
I think 15 is actually not a good value for powerpc with 4k iommu pages and 64k
PAGE_SIZE, we should make the above some kind of factor ofPAGE_SHIFT-iommu_page_shift.
Ok.
Quoted 7 lines
lib/iommu-common.c line 100
Quoted 3 lines
lib/iommu-common.c new file +3
-0+/* Sanity check */ +if (unlikely (npages =0 )) { +printk_ratelimited ("npages = 0\n" );You removed the
WARN_ONhere which had the nice property of giving you a backtrace which points to the offender. The above message alone is useless.
yes, the original code was generating checkpatch warnings and errors. That's why I removed it.
Quoted 5 lines
I am not certain about the "first unlocked pool"... We take the lock for a fairly short amount of time, I have the gut feeling that the cache line bouncing introduced by looking at a different pool may well cost more than waiting a bit longer. Did do some measurements of that optimisation ?
if you are really only taking it for a short amount of time, then the trylock should just succeed, so there is no cache line bouncing.
But yes, I did instrument it with iperf, and there was lock contention on the spinlock, which was eliminted by the trylock.
I'll fix the rest of the variable naming etc nits and send out a new version later today.
--Sowmini
Re: [PATCH v7 RFC 1/3] sparc: Break up monolithic iommu table/lock into finer graularity pools and lock
Quoted 10 lines · Sowmini Varadhan
Quoted 8 lines · Benjamin Herrenschmidt
include/linux/iommu-common.h line 9
Quoted 3 lines
include/linux/iommu-common.h new file +3
-0+ +#define IOMMU_POOL_HASHBITS 4 +#define IOMMU_NR_POOLS (1 << IOMMU_POOL_HASHBITS)I don't like those macros. You changed the value from what we had on powerpc. It could be that the new values are as good for us but I'd like to do a bit differently. Can you make the bits a variable ? Or at least an arch-provided macro which we can change later if needed ?
Quoted 8 lines
Actuallly, this are just the upper bound (16) on the number of pools.
The actual number is selected by the value passed to the
iommu_tbl_range_init(), and is not hard-coded (as was the case with the power-pc code).Thus powerpc can continue to use 4 pools without any loss of generality.
Right, but it affects the way we hash... not a huge deal though.
Quoted 5 lines
:Quoted 4 lines
Let's make it clear that this is for allocation of DMA space only, it would thus make my life easier when adapting powerpc to use a different names, something like "struct
iommu_area" works for me, or "iommualloc_region" .. whatever you fancy the most.
Quoted 7 lines
:
Quoted 2 lines
Why adding the 'arena' prefix ? What was wrong with "pools" in the powerpc imlementation ?
for the same reason you want to re-baptize
iommu_tableabove- at the time, I was doing it to minimize conflicts with existing usage. But I can rename everything if you like.
But in that case it doesn't make much sense and makes the names longer. Those are just "pools", it's sufficient.
Quoted 18 lines
Quoted 7 lines
Quoted 1 line
+#define
IOMMU_LARGE_ALLOC15Make that a variable, here too, the arch might want to tweak it.
I think 15 is actually not a good value for powerpc with 4k iommu pages and 64k
PAGE_SIZE, we should make the above some kind of factor ofPAGE_SHIFT-iommu_page_shift.Ok.
Quoted 7 lines
lib/iommu-common.c line 100
Quoted 3 lines
lib/iommu-common.c new file +3
-0+/* Sanity check */ +if (unlikely (npages =0 )) { +printk_ratelimited ("npages = 0\n" );You removed the
WARN_ONhere which had the nice property of giving you a backtrace which points to the offender. The above message alone is useless.
Quoted 2 lines
yes, the original code was generating checkpatch warnings and errors. That's why I removed it.
Put it back please, and ignore checkpatch, it's become an annoyance more than anything else.
Note that nowadays, you can probably use WARN_ON_ONCE(npages = 0); in place of the whole construct.
Quoted 8 lines
Quoted 5 lines
I am not certain about the "first unlocked pool"... We take the lock for a fairly short amount of time, I have the gut feeling that the cache line bouncing introduced by looking at a different pool may well cost more than waiting a bit longer. Did do some measurements of that optimisation ?
if you are really only taking it for a short amount of time, then the trylock should just succeed, so there is no cache line bouncing.
No that's not my point. The lock is only taken for a short time but might still collide, the bouncing in that case will probably (at least that's my feeling) hurt more than help.
However, I have another concern with your construct. Essentially you spin looking for an unlocked pool without a cpu_relax. Now it's unlikely but you *can* end up eating cycles, which on a high SMT like POWER8 might mean slowing down the actual owner of the pool lock.
Quoted 2 lines
But yes, I did instrument it with iperf, and there was lock contention on the spinlock, which was eliminted by the trylock.
What is iperf ? What does that mean "there was lock contention" ? IE, was the overall performance improved or not ? Removing contention by trading it for cache line bouncing will not necessarily help. I'm not saying this is a bad optimisation but it makes the code messy and I think deserves some solid numbers demonstrating its worth.
Quoted 2 lines
I'll fix the rest of the variable naming etc nits and send out a new version later today.
There was also an actual bug in the case where you hop'ed to a new pool and forgot the flush.
Cheers,
Ben.
Re: [PATCH v7 RFC 1/3] sparc: Break up monolithic iommu table/lock into finer graularity pools and lock
Quoted 9 lines · Benjamin Herrenschmidt
No that's not my point. The lock is only taken for a short time but might still collide, the bouncing in that case will probably (at least that's my feeling) hurt more than help.
However, I have another concern with your construct. Essentially you spin looking for an unlocked pool without a
cpu_relax. Now it's unlikely but you *can* end up eating cycles, which on a high SMT like POWER8 might mean slowing down the actual owner of the pool lock.
So I tried looking at the code, and perhaps there is some arch-specific subtlety here that I am missing, but where does spin_lock itself do the cpu_relax? afaict, LOCK_CONTENDED() itself does not have this.
Quoted 5 lines
What is iperf ? What does that mean "there was lock contention" ? IE, was the overall performance improved or not ? Removing contention by trading it for cache line bouncing will not necessarily help. I'm not saying this is a bad optimisation but it makes the code messy and I think deserves some solid numbers demonstrating its worth.
iperf is a network perf benchmark. I'll try to regenerate some numbers today and get some instrumentation of cache-line bounces vs trylock misses.
Quoted 2 lines
There was also an actual bug in the case where you hop'ed to a new pool and forgot the flush.
yes, thanks for catching that, I'll fix that too, of course.
--Sowmini
Re: [PATCH v7 RFC 1/3] sparc: Break up monolithic iommu table/lock into finer graularity pools and lock
Quoted 4 lines · Sowmini Varadhan
So I tried looking at the code, and perhaps there is some arch-specific subtlety here that I am missing, but where does
spin_lockitself do thecpu_relax? afaict,LOCK_CONTENDED()itself does not have this.
To answer my question:
I'd missed the CONFIG_LOCK_STAT (which David Ahern pointed out to me). the above is only true for the LOCK_STAT case.
In any case, I ran some experiments today: I was running iperf [http://en.wikipedia.org/wiki/Iperf] over ixgbe, which is where I'd noticed the original perf issues for sparc. I was running iperf2 (which is more aggressively threaded than iperf3) with 8, 10, 16, 20 threads, and with TSO turned off. In each case, I was making sure that I was able to reach 9.X Gbps (this is a 10Gbps link)
I dont see any significant difference in the perf profile between the spin_trylock and the spin_lock version (other than, of course, the change to the lock-contention for the trylock version). I looked at the perf profiled cache-misses (works out to about 1400M for 10 threads, with or without the trylock).
I'm still waiting for some of the IB folks to try out the spin_lock version (they had also seen some significant perf improvements from breaking down the monolithic lock into multiple pools, so their workload is also sensitive to this)
But as such, it looks like it doesnt matter much, whether you use the trylock to find the first available pool, or block on the spin_lock. I'll let folks on this list vote on this one (assuming the IB tests also come out without a significant variation between the 2 locking choices).
--Sowmini
Re: [PATCH v7 RFC 1/3] sparc: Break up monolithic iommu table/lock into finer graularity pools and lock
Quoted 9 lines · Sowmini Varadhan
Quoted 4 lines · Sowmini Varadhan
So I tried looking at the code, and perhaps there is some arch-specific subtlety here that I am missing, but where does
spin_lockitself do thecpu_relax? afaict,LOCK_CONTENDED()itself does not have this.To answer my question:
I'd missed theCONFIG_LOCK_STAT(which David Ahern pointed out to me). the above is only true for theLOCK_STATcase.
powerpc:
static inline void arch_spin_lock(arch_spinlock_t *lock)
{
CLEAR_IO_SYNC;
while (1) {
if (likely(__arch_spin_trylock(lock) = 0))
break;
do {
HMT_low();
if (SHARED_PROCESSOR)
__spin_yield(lock);
} while (unlikely(lock->slock != 0));
HMT_medium();
}
}The HMT_* statements are what reduces the thread prio. Additionally, the yield thingy is something that allows us to relinguish out time slice to the partition owning the lock if it's not currently scheduled by the hypervisor.
Quoted 18 lines
In any case, I ran some experiments today: I was running iperf [http://en.wikipedia.org/wiki/Iperf] over ixgbe, which is where I'd noticed the original perf issues for sparc. I was running iperf2 (which is more aggressively threaded than iperf3) with 8, 10, 16, 20 threads, and with TSO turned off. In each case, I was making sure that I was able to reach 9.X Gbps (this is a 10Gbps link)
I dont see any significant difference in the perf profile between the
spin_trylockand thespin_lockversion (other than, of course, the change to the lock-contention for the trylock version). I looked at the perf profiled cache-misses (works out to about 1400M for 10 threads, with or without the trylock).I'm still waiting for some of the IB folks to try out the
spin_lockversion (they had also seen some significant perf improvements from breaking down the monolithic lock into multiple pools, so their workload is also sensitive to this)
Quoted 4 lines
But as such, it looks like it doesnt matter much, whether you use the trylock to find the first available pool, or block on the
spin_lock. I'll let folks on this list vote on this one (assuming the IB tests also come out without a significant variation between the 2 locking choices).
Provided that the IB test doesn't come up with a significant difference, I definitely vote for the simpler version of doing a normal spin_lock.
Cheers,
Ben.
Re: [PATCH v7 RFC 1/3] sparc: Break up monolithic iommu table/lock into finer graularity pools and lock
Quoted 3 lines · Benjamin Herrenschmidt
Provided that the IB test doesn't come up with a significant difference, I definitely vote for the simpler version of doing a normal
spin_lock.
sounds good. let me wait for the confirmation from IB, and I'll send out patchv8 soon after.
FWIW, I'm ok with all the other comments- thanks for the feedback.
--Sowmini