Skip to contentSkip to conversation

J-Core interrupt controller support

PATCH Superseded Rich Felker 3 participants 7 messages Aug 4, 2016 – Aug 16, 2016

Subsystems (3)
Device tree bindings SuperH irqchip drivers

v6 of 9 Superseded Latest is v9 →

lore
Share & tools
lore

Rich Felker

author maintainer
#0 lore raw

v6 cover J-Core interrupt controller support

Updated based on feedback from Thomas Gleixner. Removal of unnecessary data allowed some simplification. Magic numbers have been replaced with meaningful (I hope) macro constants, comments added, and minor style issues fixed.

Also, driver was made conditional in Kconfig to avoid it showing up in configurations where it's not relevant.

Rich

Rich Felker (2):
of: add J-Core interrupt controller bindings
irqchip: add J-Core AIC driver

 .../bindings/interrupt-controller/jcore,aic.txt    | 26 ++++++
 drivers/irqchip/Kconfig                            |  7 ++
 drivers/irqchip/Makefile                           |  1 +
 drivers/irqchip/irq-jcore-aic.c                    | 94 ++++++++++++++++++++++
 4 files changed, 128 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
 create mode 100644 drivers/irqchip/irq-jcore-aic.c
Signature · 1 line
2.8.1
author maintainer
#1 lore raw

PATCH v6 1/2 of: add J-Core interrupt controller bindings

Signed-off-by Rich Felker <[email protected]>
Acked-by Rob Herring <[email protected]>
---
 .../bindings/interrupt-controller/jcore,aic.txt    | 26 ++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt new file +26 -0
new file mode 100644
index 0000000..ee2ad36
@@ -0,0 +1,26 @@
+J-Core Advanced Interrupt Controller
+
+Required properties:
+
+- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
+  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
+  the "aic2" core with 64 interrupts.
+
+- reg: Memory region(s) for configuration. For SMP, there should be one
+  region per cpu, indexed by the sequential, zero-based hardware cpu
+  number.
+
+- interrupt-controller: Identifies the node as an interrupt controller
+
+- #interrupt-cells: Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+
+
+Example:
+
+aic: interrupt-controller@200 {
+	compatible = "jcore,aic2";
+	reg = < 0x200 0x30 0x500 0x30 >;
+	interrupt-controller;
+	#interrupt-cells = <1>;
+};
Signature · 1 line
2.8.1
author maintainer
#2 lore raw

PATCH v6 2/2 irqchip: add J-Core AIC driver

In reply to Rich Felker

There are two versions of the J-Core interrupt controller in use, aic1 which generates interrupts with programmable priorities, but only supports 8 irq lines and maps them to cpu traps in the range 17 to 24, and aic2 which uses traps in the range 64-127 and supports up to 128 irqs, with priorities dependent on the interrupt number. The Linux driver does not make use of priorities anyway.

For simplicity, there is no aic1-specific logic in the driver beyond setting the priority register, which is necessary for interrupts to work at all. Eventually aic1 will likely be phased out, but it's currently in use in deployments and all released bitstream binaries.

Signed-off-by Rich Felker <[email protected]>
---
 drivers/irqchip/Kconfig         |  7 +++
 drivers/irqchip/Makefile        |  1 +
 drivers/irqchip/irq-jcore-aic.c | 94 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 102 insertions(+)
 create mode 100644 drivers/irqchip/irq-jcore-aic.c
drivers/irqchip/Kconfig +7 -0
index 5495a5b..ab84ce3 100644
@@ -156,6 +156,13 @@ config PIC32_EVIC
 	select GENERIC_IRQ_CHIP
 	select IRQ_DOMAIN
 
+config JCORE_AIC
+	bool "J-Core integrated AIC"
+	depends on OF && (SUPERH || COMPILE_TEST)
+	select IRQ_DOMAIN
+	help
+	  Support for the J-Core integrated AIC.
+
 config RENESAS_INTC_IRQPIN
 	bool
 	select IRQ_DOMAIN
drivers/irqchip/Makefile +1 -0
index 4c203b6..ee7e3ca 100644
@@ -40,6 +40,7 @@ obj-$(CONFIG_I8259)			+= irq-i8259.o
 obj-$(CONFIG_IMGPDC_IRQ)		+= irq-imgpdc.o
 obj-$(CONFIG_IRQ_MIPS_CPU)		+= irq-mips-cpu.o
 obj-$(CONFIG_SIRF_IRQ)			+= irq-sirfsoc.o
+obj-$(CONFIG_JCORE_AIC)			+= irq-jcore-aic.o
 obj-$(CONFIG_RENESAS_INTC_IRQPIN)	+= irq-renesas-intc-irqpin.o
 obj-$(CONFIG_RENESAS_IRQC)		+= irq-renesas-irqc.o
 obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o
drivers/irqchip/irq-jcore-aic.c new file +94 -0

94 lines not on this page · raw message

Signature · 1 line
2.8.1
#3 lore raw

Re: [PATCH v6 2/2] irqchip: add J-Core AIC driver

Hi Rich,

Quoted 7 lines · Rich Felker
drivers/irqchip/irq-jcore-aic.c new file +4 -0
 
+int __init aic_irq_of_init(struct device_node *node, struct device_node *parent)
+{
+       unsigned min_irq = JCORE_AIC2_MIN_HWIRQ;
+       unsigned dom_sz = JCORE_AIC_MAX_HWIRQ+1;

drivers/irqchip/irq-jcore-aic.c line 60

Quoted 10 lines
drivers/irqchip/irq-jcore-aic.c new file +10 -0
+       struct irq_domain *domain;
+
+       pr_info("Initializing J-Core AIC\n");
+
+       /* AIC1 needs priority initialization to receive interrupts. */
+       if (of_device_is_compatible(node, "jcore,aic1")) {
+               unsigned cpu;
+
+               for_each_present_cpu(cpu) {
+                       void __iomem *base = of_iomap(node, cpu);

Just double checking, these regions are per-cpu hardware registers, and not related to other functionality at all?

I.e. when booting on an SMP-capable system a kernel compiled with CONFIG_SMP=n, or using the kernel command line option maxcpus= to reduce the number of CPUs, no ill effects happen by not mapping the region and not writing to the register below?

drivers/irqchip/irq-jcore-aic.c line 70

Quoted 10 lines
drivers/irqchip/irq-jcore-aic.c new file +10 -0
+
+                       if (!base) {
+                               pr_err("Unable to map AIC for cpu %u\n", cpu);
+                               return -ENOMEM;
+                       }
+                       __raw_writel(0xffffffff, base + JCORE_AIC1_INTPRI_REG);
+                       iounmap(base);
+               }
+               min_irq = JCORE_AIC1_MIN_HWIRQ;
+       }

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

author maintainer
#4 lore raw

Re: [PATCH v6 2/2] irqchip: add J-Core AIC driver

Quoted 24 lines · Geert Uytterhoeven

Hi Rich,

Quoted 7 lines · Rich Felker
drivers/irqchip/irq-jcore-aic.c new file +4 -0
 
+int __init aic_irq_of_init(struct device_node *node, struct device_node *parent)
+{
+       unsigned min_irq = JCORE_AIC2_MIN_HWIRQ;
+       unsigned dom_sz = JCORE_AIC_MAX_HWIRQ+1;

drivers/irqchip/irq-jcore-aic.c line 60

Quoted 10 lines
drivers/irqchip/irq-jcore-aic.c new file +10 -0
+       struct irq_domain *domain;
+
+       pr_info("Initializing J-Core AIC\n");
+
+       /* AIC1 needs priority initialization to receive interrupts. */
+       if (of_device_is_compatible(node, "jcore,aic1")) {
+               unsigned cpu;
+
+               for_each_present_cpu(cpu) {
+                       void __iomem *base = of_iomap(node, cpu);

Just double checking, these regions are per-cpu hardware registers, and not related to other functionality at all?

Quoted 4 lines

I.e. when booting on an SMP-capable system a kernel compiled with CONFIG_SMP=n, or using the kernel command line option maxcpus= to reduce the number of CPUs, no ill effects happen by not mapping the region and not writing to the register below?

If you're not using a secondary cpu, there's no harm in ignoring its aic completely.

Rich

#5 lore raw
In reply to Rich Felker

Hi Rich,

Quoted 15 lines · Rich Felker

Updated based on feedback from Thomas Gleixner. Removal of unnecessary data allowed some simplification. Magic numbers have been replaced with meaningful (I hope) macro constants, comments added, and minor style issues fixed.

Also, driver was made conditional in Kconfig to avoid it showing up in configurations where it's not relevant.

Rich

Rich Felker (2):
of: add J-Core interrupt controller bindings
irqchip: add J-Core AIC driver

Quoted 7 lines
 .../bindings/interrupt-controller/jcore,aic.txt    | 26 ++++++
 drivers/irqchip/Kconfig                            |  7 ++
 drivers/irqchip/Makefile                           |  1 +
 drivers/irqchip/irq-jcore-aic.c                    | 94 ++++++++++++++++++++++
 4 files changed, 128 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
 create mode 100644 drivers/irqchip/irq-jcore-aic.c

Once -rc1 drops, I'll put this in a branch, irqchip/jcore. You can then include it as a dep for other branches as needed.

thx,

Jason.

#6 lore raw

Hi Rich,

Quoted 24 lines · Jason Cooper
Quoted 15 lines · Rich Felker

Updated based on feedback from Thomas Gleixner. Removal of unnecessary data allowed some simplification. Magic numbers have been replaced with meaningful (I hope) macro constants, comments added, and minor style issues fixed.

Also, driver was made conditional in Kconfig to avoid it showing up in configurations where it's not relevant.

Rich

Rich Felker (2):
of: add J-Core interrupt controller bindings
irqchip: add J-Core AIC driver

Quoted 7 lines
 .../bindings/interrupt-controller/jcore,aic.txt    | 26 ++++++
 drivers/irqchip/Kconfig                            |  7 ++
 drivers/irqchip/Makefile                           |  1 +
 drivers/irqchip/irq-jcore-aic.c                    | 94 ++++++++++++++++++++++
 4 files changed, 128 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
 create mode 100644 drivers/irqchip/irq-jcore-aic.c
Quoted 2 lines

Once -rc1 drops, I'll put this in a branch, irqchip/jcore. You can then include it as a dep for other branches as needed.

This is now up and should appear in -next.

thx,

Jason.