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Update the reset values of the Xilinx ZynqMP QSPI

PATCH Superseded Alistair Francis 3 participants 10 messages Nov 28, 2017 – Dec 1, 2017 Arm/Zynq architecture

v1 of 3 Superseded Latest is v3 →

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Alistair Francis

author
#0 lore raw

cover Update the reset values of the Xilinx ZynqMP QSPI

Update the reset values of the Xilinx ZynqMP QSPI device to match the resister spec here:
https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html

Based-on: [email protected]

Alistair Francis (3):
xilinx_spips: Update the QSPI Mod ID reset value
xilinx_spis: Set all of the reset values
xilinx_spips: Use memset instead of a for loop to zero registers

 hw/ssi/xilinx_spips.c         | 48 ++++++++++++++++++++++++++++++++-----------
 include/hw/ssi/xilinx_spips.h |  2 +-
 2 files changed, 37 insertions(+), 13 deletions(-)
Signature · 1 line
2.14.1
author
#1 lore raw

PATCH 1/3 xilinx_spips: Update the QSPI Mod ID reset value

Update the reset value to match the latest ZynqMP register spec.

Signed-off-by Alistair Francis <[email protected]>

---

 hw/ssi/xilinx_spips.c | 1 +
 1 file changed, 1 insertion(+)
hw/ssi/xilinx_spips.c +1 -0
index ad1b2ba79f..899db814ee 100644
@@ -355,6 +355,7 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d)
     s->regs[R_GQSPI_RX_THRESH] = 1;
     s->regs[R_GQSPI_GFIFO_THRESH] = 1;
     s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK;
+    s->regs[R_MOD_ID] = 0x01090101;
     s->man_start_com_g = false;
     s->gqspi_irqline = 0;
     xlnx_zynqmp_qspips_update_ixr(s);
Signature · 1 line
2.14.1
Reviewed-by on v1 1/3
#2 lore raw

Re: [Qemu-devel] [PATCH-2.12 v1 1/3] xilinx_spips: Update the QSPI Mod ID reset value

Quoted 13 lines · Alistair Francis

Update the reset value to match the latest ZynqMP register spec.

Signed-off-by Alistair Francis <[email protected]>

---

  hw/ssi/xilinx_spips.c | 1 +
  1 file changed, 1 insertion(+)
hw/ssi/xilinx_spips.c +0 -0
index ad1b2ba79f..899db814ee 100644

hw/ssi/xilinx_spips.c static void xlnx_zynqmp_qspips_reset(DeviceState *d) · line 358

Quoted 4 lines
hw/ssi/xilinx_spips.c +1 -0
@@ -355,6 +355,7 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d)
      s->regs[R_GQSPI_RX_THRESH] = 1;
      s->regs[R_GQSPI_GFIFO_THRESH] = 1;
      s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK;
+    s->regs[R_MOD_ID] = 0x01090101;
Reviewed-by KONRAD Frederic <[email protected]>
Quoted 4 lines
hw/ssi/xilinx_spips.c +0 -0
      s->man_start_com_g = false;
      s->gqspi_irqline = 0;
      xlnx_zynqmp_qspips_update_ixr(s);
Reviewed-by on v1 1/3
#3 lore raw

Re: [Qemu-devel] [PATCH-2.12 v1 1/3] xilinx_spips: Update the QSPI Mod ID reset value

In reply to Alistair Francis
Quoted 4 lines · Alistair Francis

Update the reset value to match the latest ZynqMP register spec.

Signed-off-by Alistair Francis <[email protected]>
Reviewed-by Francisco Iglesias <[email protected]>
Quoted 22 lines

---

 hw/ssi/xilinx_spips.c | 1 +
 1 file changed, 1 insertion(+)
hw/ssi/xilinx_spips.c +1 -1
index ad1b2ba79f..899db814ee 100644
@@ -355,6 +355,7 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d)
     s->regs[R_GQSPI_RX_THRESH] = 1;
     s->regs[R_GQSPI_GFIFO_THRESH] = 1;
     s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK;
+    s->regs[R_MOD_ID] = 0x01090101;
     s->man_start_com_g = false;
     s->gqspi_irqline = 0;
     xlnx_zynqmp_qspips_update_ixr(s);
--

2.14.1

author
#4 lore raw

PATCH 2/3 xilinx_spis: Set all of the reset values

In reply to Alistair Francis

Following the ZynqMP register spec let's ensure that all reset values are set.

Signed-off-by Alistair Francis <[email protected]>

---

 hw/ssi/xilinx_spips.c         | 38 +++++++++++++++++++++++++++++++++-----
 include/hw/ssi/xilinx_spips.h |  2 +-
 2 files changed, 34 insertions(+), 6 deletions(-)
hw/ssi/xilinx_spips.c +33 -5
index 899db814ee..1a37f9c7f5 100644
@@ -66,6 +66,7 @@
 
 /* interrupt mechanism */
 #define R_INTR_STATUS       (0x04 / 4)
+#define R_INTR_STATUS_RESET (0x104)
 #define R_INTR_EN           (0x08 / 4)
 #define R_INTR_DIS          (0x0C / 4)
 #define R_INTR_MASK         (0x10 / 4)

@@ -102,6 +103,9 @@
 #define R_SLAVE_IDLE_COUNT  (0x24 / 4)
 #define R_TX_THRES          (0x28 / 4)
 #define R_RX_THRES          (0x2C / 4)
+#define R_GPIO              (0x30 / 4)
+#define R_LPBK_DLY_ADJ      (0x38 / 4)
+#define R_LPBK_DLY_ADJ_RESET (0x33)
 #define R_TXD1              (0x80 / 4)
 #define R_TXD2              (0x84 / 4)
 #define R_TXD3              (0x88 / 4)

@@ -137,11 +141,16 @@
 #define R_GQSPI_SELECT          (0x144 / 4)
     FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1)
 #define R_GQSPI_ISR         (0x104 / 4)
+#define R_GQSPI_ISR_RESET   (0xb84)
 #define R_GQSPI_IER         (0x108 / 4)
 #define R_GQSPI_IDR         (0x10c / 4)
 #define R_GQSPI_IMR         (0x110 / 4)
+#define R_GQSPI_IMR_RESET   (0xfbe)
 #define R_GQSPI_TX_THRESH   (0x128 / 4)
 #define R_GQSPI_RX_THRESH   (0x12c / 4)
+#define R_GQSPI_GPIO_THRESH (0x130 / 4)
+#define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4)
+#define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33)
 #define R_GQSPI_CNFG        (0x100 / 4)
     FIELD(GQSPI_CNFG, MODE_EN, 30, 2)
     FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1)

@@ -177,8 +186,16 @@
     FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1)
     FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1)
     FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8)
-#define R_GQSPI_MOD_ID        (0x168 / 4)
-#define R_GQSPI_MOD_ID_VALUE  0x010A0000
+#define R_GQSPI_MOD_ID        (0x1fc / 4)
+#define R_GQSPI_MOD_ID_RESET  (0x10a0000)
+
+#define R_QSPIDMA_DST_CTRL         (0x80c / 4)
+#define R_QSPIDMA_DST_CTRL_RESET   (0x803ffa00)
+#define R_QSPIDMA_DST_I_MASK       (0x820 / 4)
+#define R_QSPIDMA_DST_I_MASK_RESET (0xfe)
+#define R_QSPIDMA_DST_CTRL2        (0x824 / 4)
+#define R_QSPIDMA_DST_CTRL2_RESET  (0x081bfff8)
+
 /* size of TXRX FIFOs */
 #define RXFF_A          (128)
 #define TXFF_A          (128)

@@ -351,11 +368,22 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d)
     fifo8_reset(&s->rx_fifo_g);
     fifo8_reset(&s->rx_fifo_g);
     fifo32_reset(&s->fifo_g);
-    s->regs[R_GQSPI_TX_THRESH] = 1;
-    s->regs[R_GQSPI_RX_THRESH] = 1;
-    s->regs[R_GQSPI_GFIFO_THRESH] = 1;
+    s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET;
+    s->regs[R_GPIO] = 1;
+    s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET;
+    s->regs[R_GQSPI_GFIFO_THRESH] = 0x10;
     s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK;
     s->regs[R_MOD_ID] = 0x01090101;
+    s->regs[R_GQSPI_ISR] = R_GQSPI_ISR_RESET;
+    s->regs[R_GQSPI_IMR] = R_GQSPI_IMR_RESET;
+    s->regs[R_GQSPI_TX_THRESH] = 1;
+    s->regs[R_GQSPI_RX_THRESH] = 1;
+    s->regs[R_GQSPI_GPIO_THRESH] = 1;
+    s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET;
+    s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET;
+    s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET;
+    s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET;
+    s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET;
     s->man_start_com_g = false;
     s->gqspi_irqline = 0;
     xlnx_zynqmp_qspips_update_ixr(s);
include/hw/ssi/xilinx_spips.h +1 -1
index 75fc94ce5d..d398a4e81c 100644
@@ -32,7 +32,7 @@
 typedef struct XilinxSPIPS XilinxSPIPS;
 
 #define XLNX_SPIPS_R_MAX        (0x100 / 4)
-#define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4)
+#define XLNX_ZYNQMP_SPIPS_R_MAX (0x830 / 4)
 
 /* Bite off 4k chunks at a time */
 #define LQSPI_CACHE_SIZE 1024
Signature · 1 line
2.14.1
#5 lore raw

Re: [Qemu-devel] [PATCH-2.12 v1 2/3] xilinx_spis: Set all of the reset values

On 28 November 2017 at 23:31, Alistair Francis <[email protected]> wrote:

Dear Alistair,

There is a typo in the commit message:
s/xilinx_spis/xilinx_spips/

Following the ZynqMP register spec let's ensure that all reset values

Quoted 49 lines

are set.

Signed-off-by Alistair Francis <[email protected]>

---

 hw/ssi/xilinx_spips.c         | 38 +++++++++++++++++++++++++++++++++-----
 include/hw/ssi/xilinx_spips.h |  2 +-
 2 files changed, 34 insertions(+), 6 deletions(-)
hw/ssi/xilinx_spips.c +9 -0
index 899db814ee..1a37f9c7f5 100644
@@ -66,6 +66,7 @@
 
 /* interrupt mechanism */
 #define R_INTR_STATUS       (0x04 / 4)
+#define R_INTR_STATUS_RESET (0x104)
 #define R_INTR_EN           (0x08 / 4)
 #define R_INTR_DIS          (0x0C / 4)
 #define R_INTR_MASK         (0x10 / 4)

@@ -102,6 +103,9 @@
 #define R_SLAVE_IDLE_COUNT  (0x24 / 4)
 #define R_TX_THRES          (0x28 / 4)
 #define R_RX_THRES          (0x2C / 4)
+#define R_GPIO              (0x30 / 4)
+#define R_LPBK_DLY_ADJ      (0x38 / 4)
+#define R_LPBK_DLY_ADJ_RESET (0x33)
 #define R_TXD1              (0x80 / 4)
 #define R_TXD2              (0x84 / 4)
 #define R_TXD3              (0x88 / 4)

@@ -137,11 +141,16 @@
 #define R_GQSPI_SELECT          (0x144 / 4)
     FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1)
 #define R_GQSPI_ISR         (0x104 / 4)
+#define R_GQSPI_ISR_RESET   (0xb84)
 #define R_GQSPI_IER         (0x108 / 4)
 #define R_GQSPI_IDR         (0x10c / 4)
 #define R_GQSPI_IMR         (0x110 / 4)
+#define R_GQSPI_IMR_RESET   (0xfbe)
 #define R_GQSPI_TX_THRESH   (0x128 / 4)
 #define R_GQSPI_RX_THRESH   (0x12c / 4)
+#define R_GQSPI_GPIO_THRESH (0x130 / 4)
+#define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4)
+#define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33)
 #define R_GQSPI_CNFG        (0x100 / 4)
     FIELD(GQSPI_CNFG, MODE_EN, 30, 2)
     FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1)

hw/ssi/xilinx_spips.c line 191

Quoted 8 lines
hw/ssi/xilinx_spips.c +2 -2
@@ -177,8 +186,16 @@
     FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1)
     FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1)
     FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8)
-#define R_GQSPI_MOD_ID        (0x168 / 4)
-#define R_GQSPI_MOD_ID_VALUE  0x010A0000
+#define R_GQSPI_MOD_ID        (0x1fc / 4)
+#define R_GQSPI_MOD_ID_RESET  (0x10a0000)

+

Quoted 11 lines
hw/ssi/xilinx_spips.c +7 -0
+#define R_QSPIDMA_DST_CTRL         (0x80c / 4)
+#define R_QSPIDMA_DST_CTRL_RESET   (0x803ffa00)
+#define R_QSPIDMA_DST_I_MASK       (0x820 / 4)
+#define R_QSPIDMA_DST_I_MASK_RESET (0xfe)
+#define R_QSPIDMA_DST_CTRL2        (0x824 / 4)
+#define R_QSPIDMA_DST_CTRL2_RESET  (0x081bfff8)
+
 /* size of TXRX FIFOs */
 #define RXFF_A          (128)
 #define TXFF_A          (128)

hw/ssi/xilinx_spips.c static void xlnx_zynqmp_qspips_reset(DeviceState *d) · line 373

Quoted 9 lines
hw/ssi/xilinx_spips.c +2 -3
@@ -351,11 +368,22 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d)
     fifo8_reset(&s->rx_fifo_g);
     fifo8_reset(&s->rx_fifo_g);
     fifo32_reset(&s->fifo_g);
-    s->regs[R_GQSPI_TX_THRESH] = 1;
-    s->regs[R_GQSPI_RX_THRESH] = 1;
-    s->regs[R_GQSPI_GFIFO_THRESH] = 1;
+    s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET;
+    s->regs[R_GPIO] = 1;

+ s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET;

hw/ssi/xilinx_spips.c static void xlnx_zynqmp_qspips_reset(DeviceState *d)

Quoted 3 lines
hw/ssi/xilinx_spips.c +1 -0
+    s->regs[R_GQSPI_GFIFO_THRESH] = 0x10;
     s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK;

Also, above row will be overriden below so maybe we should remove it?

hw/ssi/xilinx_spips.c static void xlnx_zynqmp_qspips_reset(DeviceState *d)

Quoted 3 lines
hw/ssi/xilinx_spips.c +1 -0
     s->regs[R_MOD_ID] = 0x01090101;
+    s->regs[R_GQSPI_ISR] = R_GQSPI_ISR_RESET;

To be noted, above row will also be overriden by xlnx_zynqmp_qspips_update_ixr below but maybe it is good to have for consistency (you can decide).

Best regards,
Francisco Iglesias

hw/ssi/xilinx_spips.c static void xlnx_zynqmp_qspips_reset(DeviceState *d) · line 381

Quoted 5 lines
hw/ssi/xilinx_spips.c +4 -0
+    s->regs[R_GQSPI_IMR] = R_GQSPI_IMR_RESET;
+    s->regs[R_GQSPI_TX_THRESH] = 1;
+    s->regs[R_GQSPI_RX_THRESH] = 1;
+    s->regs[R_GQSPI_GPIO_THRESH] = 1;

+ s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET;

Quoted 25 lines
hw/ssi/xilinx_spips.c +4 -0
+    s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET;
+    s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET;
+    s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET;
+    s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET;
     s->man_start_com_g = false;
     s->gqspi_irqline = 0;
     xlnx_zynqmp_qspips_update_ixr(s);
include/hw/ssi/xilinx_spips.h +1 -2
index 75fc94ce5d..d398a4e81c 100644
@@ -32,7 +32,7 @@
 typedef struct XilinxSPIPS XilinxSPIPS;
 
 #define XLNX_SPIPS_R_MAX        (0x100 / 4)
-#define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4)
+#define XLNX_ZYNQMP_SPIPS_R_MAX (0x830 / 4)
 
 /* Bite off 4k chunks at a time */
 #define LQSPI_CACHE_SIZE 1024
--

2.14.1

author
#6 lore raw

Re: [Qemu-devel] [PATCH-2.12 v1 2/3] xilinx_spis: Set all of the reset values

Quoted 89 lines · francisco iglesias

On 28 November 2017 at 23:31, Alistair Francis <[email protected]> wrote:

Dear Alistair,

There is a typo in the commit message:
s/xilinx_spis/xilinx_spips/

Quoted 79 lines

Following the ZynqMP register spec let's ensure that all reset values are set.

Signed-off-by Alistair Francis <[email protected]>

---

 hw/ssi/xilinx_spips.c         | 38 +++++++++++++++++++++++++++++++++-----
 include/hw/ssi/xilinx_spips.h |  2 +-
 2 files changed, 34 insertions(+), 6 deletions(-)
hw/ssi/xilinx_spips.c +19 -2
index 899db814ee..1a37f9c7f5 100644
@@ -66,6 +66,7 @@
 
 /* interrupt mechanism */
 #define R_INTR_STATUS       (0x04 / 4)
+#define R_INTR_STATUS_RESET (0x104)
 #define R_INTR_EN           (0x08 / 4)
 #define R_INTR_DIS          (0x0C / 4)
 #define R_INTR_MASK         (0x10 / 4)

@@ -102,6 +103,9 @@
 #define R_SLAVE_IDLE_COUNT  (0x24 / 4)
 #define R_TX_THRES          (0x28 / 4)
 #define R_RX_THRES          (0x2C / 4)
+#define R_GPIO              (0x30 / 4)
+#define R_LPBK_DLY_ADJ      (0x38 / 4)
+#define R_LPBK_DLY_ADJ_RESET (0x33)
 #define R_TXD1              (0x80 / 4)
 #define R_TXD2              (0x84 / 4)
 #define R_TXD3              (0x88 / 4)

@@ -137,11 +141,16 @@
 #define R_GQSPI_SELECT          (0x144 / 4)
     FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1)
 #define R_GQSPI_ISR         (0x104 / 4)
+#define R_GQSPI_ISR_RESET   (0xb84)
 #define R_GQSPI_IER         (0x108 / 4)
 #define R_GQSPI_IDR         (0x10c / 4)
 #define R_GQSPI_IMR         (0x110 / 4)
+#define R_GQSPI_IMR_RESET   (0xfbe)
 #define R_GQSPI_TX_THRESH   (0x128 / 4)
 #define R_GQSPI_RX_THRESH   (0x12c / 4)
+#define R_GQSPI_GPIO_THRESH (0x130 / 4)
+#define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4)
+#define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33)
 #define R_GQSPI_CNFG        (0x100 / 4)
     FIELD(GQSPI_CNFG, MODE_EN, 30, 2)
     FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1)

@@ -177,8 +186,16 @@
     FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1)
     FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1)
     FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8)
-#define R_GQSPI_MOD_ID        (0x168 / 4)
-#define R_GQSPI_MOD_ID_VALUE  0x010A0000
+#define R_GQSPI_MOD_ID        (0x1fc / 4)
+#define R_GQSPI_MOD_ID_RESET  (0x10a0000)
 
+
+#define R_QSPIDMA_DST_CTRL         (0x80c / 4)
+#define R_QSPIDMA_DST_CTRL_RESET   (0x803ffa00)
+#define R_QSPIDMA_DST_I_MASK       (0x820 / 4)
+#define R_QSPIDMA_DST_I_MASK_RESET (0xfe)
+#define R_QSPIDMA_DST_CTRL2        (0x824 / 4)
+#define R_QSPIDMA_DST_CTRL2_RESET  (0x081bfff8)
+
 /* size of TXRX FIFOs */
 #define RXFF_A          (128)

#define TXFF_A (128)

hw/ssi/xilinx_spips.c +2 -3
@@ -351,11 +368,22 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d)
     fifo8_reset(&s->rx_fifo_g);
     fifo8_reset(&s->rx_fifo_g);
     fifo32_reset(&s->fifo_g);
-    s->regs[R_GQSPI_TX_THRESH] = 1;
-    s->regs[R_GQSPI_RX_THRESH] = 1;
-    s->regs[R_GQSPI_GFIFO_THRESH] = 1;
+    s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET;
+    s->regs[R_GPIO] = 1;
Quoted 6 lines

hw/ssi/xilinx_spips.c static void xlnx_zynqmp_qspips_reset(DeviceState *d) · line 375

Quoted 3 lines
hw/ssi/xilinx_spips.c +2 -0
+    s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET;
+    s->regs[R_GQSPI_GFIFO_THRESH] = 0x10;
     s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK;

Also, above row will be overriden below so maybe we should remove it?

Yes, we should. I'll remove it.

Quoted 9 lines

hw/ssi/xilinx_spips.c static void xlnx_zynqmp_qspips_reset(DeviceState *d) · line 377

Quoted 4 lines
hw/ssi/xilinx_spips.c +1 -0
     s->regs[R_MOD_ID] = 0x01090101;
+    s->regs[R_GQSPI_ISR] = R_GQSPI_ISR_RESET;

To be noted, above row will also be overriden by xlnx_zynqmp_qspips_update_ixr below but maybe it is good to have for consistency (you can decide).

Ah, good point. I'll remove this one as well.

Alistair

Quoted 37 lines

Best regards,
Francisco Iglesias

Quoted 31 lines
hw/ssi/xilinx_spips.c +9 -0
+    s->regs[R_GQSPI_IMR] = R_GQSPI_IMR_RESET;
+    s->regs[R_GQSPI_TX_THRESH] = 1;
+    s->regs[R_GQSPI_RX_THRESH] = 1;
+    s->regs[R_GQSPI_GPIO_THRESH] = 1;
 
+    s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET;
+    s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET;
+    s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET;
+    s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET;
+    s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET;
     s->man_start_com_g = false;

     s->gqspi_irqline = 0;
     xlnx_zynqmp_qspips_update_ixr(s);
include/hw/ssi/xilinx_spips.h +1 -2
index 75fc94ce5d..d398a4e81c 100644
@@ -32,7 +32,7 @@
 typedef struct XilinxSPIPS XilinxSPIPS;
 
 #define XLNX_SPIPS_R_MAX        (0x100 / 4)
-#define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4)
+#define XLNX_ZYNQMP_SPIPS_R_MAX (0x830 / 4)
 
 /* Bite off 4k chunks at a time */
 #define LQSPI_CACHE_SIZE 1024
--

2.14.1

author
#7 lore raw

PATCH 3/3 xilinx_spips: Use memset instead of a for loop to zero registers

In reply to Alistair Francis

Use memset() instead of a for loop to zero all of the registers.

Signed-off-by Alistair Francis <[email protected]>

---

 hw/ssi/xilinx_spips.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)
hw/ssi/xilinx_spips.c +3 -8
index 1a37f9c7f5..82436e2f69 100644
@@ -330,10 +330,7 @@ static void xilinx_spips_reset(DeviceState *d)
 {
     XilinxSPIPS *s = XILINX_SPIPS(d);
 
-    int i;
-    for (i = 0; i < XLNX_SPIPS_R_MAX; i++) {
-        s->regs[i] = 0;
-    }
+    memset(s->regs, 0, sizeof(s->regs));
 
     fifo8_reset(&s->rx_fifo);
     fifo8_reset(&s->rx_fifo);

@@ -358,13 +355,11 @@ static void xilinx_spips_reset(DeviceState *d)
 static void xlnx_zynqmp_qspips_reset(DeviceState *d)
 {
     XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(d);
-    int i;
 
     xilinx_spips_reset(d);
 
-    for (i = 0; i < XLNX_ZYNQMP_SPIPS_R_MAX; i++) {
-        s->regs[i] = 0;
-    }
+    memset(s->regs, 0, sizeof(s->regs));
+
     fifo8_reset(&s->rx_fifo_g);
     fifo8_reset(&s->rx_fifo_g);
     fifo32_reset(&s->fifo_g);
Signature · 1 line
2.14.1
Reviewed-by on v1 3/3
#8 lore raw

Re: [Qemu-devel] [PATCH-2.12 v1 3/3] xilinx_spips: Use memset instead of a for loop to zero registers

Quoted 31 lines · Alistair Francis

Use memset() instead of a for loop to zero all of the registers.

Signed-off-by Alistair Francis <[email protected]>

---

  hw/ssi/xilinx_spips.c | 11 +++--------
  1 file changed, 3 insertions(+), 8 deletions(-)
hw/ssi/xilinx_spips.c +1 -5
index 1a37f9c7f5..82436e2f69 100644
@@ -330,10 +330,7 @@ static void xilinx_spips_reset(DeviceState *d)
  {
      XilinxSPIPS *s = XILINX_SPIPS(d);
 
-    int i;
-    for (i = 0; i < XLNX_SPIPS_R_MAX; i++) {
-        s->regs[i] = 0;
-    }
+    memset(s->regs, 0, sizeof(s->regs));
 
      fifo8_reset(&s->rx_fifo);
      fifo8_reset(&s->rx_fifo);

@@ -358,13 +355,11 @@ static void xilinx_spips_reset(DeviceState *d)
  static void xlnx_zynqmp_qspips_reset(DeviceState *d)
  {
      XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(d);
-    int i;

hw/ssi/xilinx_spips.c static void xilinx_spips_reset(DeviceState *d) · line 365

Quoted 10 lines
hw/ssi/xilinx_spips.c +2 -3
      xilinx_spips_reset(d);
 
-    for (i = 0; i < XLNX_ZYNQMP_SPIPS_R_MAX; i++) {
-        s->regs[i] = 0;
-    }
+    memset(s->regs, 0, sizeof(s->regs));
+
      fifo8_reset(&s->rx_fifo_g);
      fifo8_reset(&s->rx_fifo_g);
      fifo32_reset(&s->fifo_g);
Reviewed-by KONRAD Frederic <[email protected]>
Reviewed-by on v1 3/3
#9 lore raw

Re: [Qemu-devel] [PATCH-2.12 v1 3/3] xilinx_spips: Use memset instead of a for loop to zero registers

In reply to Alistair Francis
Quoted 4 lines · Alistair Francis

Use memset() instead of a for loop to zero all of the registers.

Signed-off-by Alistair Francis <[email protected]>
Reviewed-by Francisco Iglesias <[email protected]>
Quoted 42 lines

---

 hw/ssi/xilinx_spips.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)
hw/ssi/xilinx_spips.c +3 -9
index 1a37f9c7f5..82436e2f69 100644
@@ -330,10 +330,7 @@ static void xilinx_spips_reset(DeviceState *d)
 {
     XilinxSPIPS *s = XILINX_SPIPS(d);
 
-    int i;
-    for (i = 0; i < XLNX_SPIPS_R_MAX; i++) {
-        s->regs[i] = 0;
-    }
+    memset(s->regs, 0, sizeof(s->regs));
 
     fifo8_reset(&s->rx_fifo);
     fifo8_reset(&s->rx_fifo);

@@ -358,13 +355,11 @@ static void xilinx_spips_reset(DeviceState *d)
 static void xlnx_zynqmp_qspips_reset(DeviceState *d)
 {
     XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(d);
-    int i;
 
     xilinx_spips_reset(d);
 
-    for (i = 0; i < XLNX_ZYNQMP_SPIPS_R_MAX; i++) {
-        s->regs[i] = 0;
-    }
+    memset(s->regs, 0, sizeof(s->regs));
+
     fifo8_reset(&s->rx_fifo_g);
     fifo8_reset(&s->rx_fifo_g);
     fifo32_reset(&s->fifo_g);
--

2.14.1