target/mips: Amend R5900 support
cover target/mips: Amend R5900 support
This series amends the R5900 support with the following noncritical features:
- The vendor-specific Application-Specific Extension (ASE) ASE_MMI is renamed to ASE_TOSHIBA_MMI, because several vendors have multimedia instruction (MMI) sets and other extensions of various kinds. ASE vendor namespaces make it clear these are not generic architectural features and also avoid name clashes.
- The R5900 LQ and SQ instructions are now also covered by the Toshiba MMI ASE, as per the TX79 manual[1].
- The three-operand MADD and MADDU instructions specific to the R5900 and the Toshiba TX19, TX39 and TX79 cores are now supported and tested by the R5900 TCG test suite.
- The three-operand MADD1 and MADDU1 pipeline 1 instructions specific to the R5900 and the Toshiba TX79 core are now supported and tested by the R5900 TCG test suite.
- The membership field of struct mips_opcode is now uint64_t instead of unsigned long, that is too small in 32-bit builds.
- R5900 disassembly constants are defined.
- The R5900 instructions DIV1, DIVU1, MFLO, MTLO, MFHI, MTHI, MULT1 and MULTU1 are now disassembled. Unfortunately, the opcodes for MADD1 and MADDU1 clash with the opcodes for CLZ and CLO, resulting in incorrect disassembly. MADD1 and MADDU1 are therefore left undefined.
This series has been successfully built with the 16 different build configurations
{gcc,clang} x -m{32,64} x mips{,64}el-{linux-user,softmmu}in addition to successfully completing the R5900 test suite
cd tests/tcg/mips/mipsr5900 && make check
Reference:
[1] "Toshiba TX System RISC TX79 Core Architecture", Toshiba Corporation,
section B.3.2, p. B-4, <https://wiki.qemu.org/File:C790.pdf>.
Fredrik Noring (9):
target/mips: Rename ASE_MMI to ASE_TOSHIBA_MMI, with Toshiba namespace target/mips: R5900 LQ and SQ also belong to the Toshiba MMI ASE target/mips: Support R5900 three-operand MADD1 and MADDU1 tests/tcg/mips: Test R5900 three-operand MADD tests/tcg/mips: Test R5900 three-operand MADD1 tests/tcg/mips: Test R5900 three-operand MADDU tests/tcg/mips: Test R5900 three-operand MADDU1 disas/mips: Define R5900 disassembly constants
disas/mips: Disassemble R5900 DIV[U]1, M{F,T}{LO,HI}1 and MULT[U]1
Philippe Mathieu-Daudé (2):
target/mips: Support Toshiba specific three-operand MADD and MADDU disas/mips: Increase 'member of ISAs' flag holder size
disas/mips.c | 22 ++++++++- target/mips/mips-defs.h | 2 +- target/mips/translate.c | 77 ++++++++++++++++++++++++++---- target/mips/translate_init.inc.c | 2 +- tests/tcg/mips/mipsr5900/Makefile | 2 + tests/tcg/mips/mipsr5900/madd.c | 78 +++++++++++++++++++++++++++++++ tests/tcg/mips/mipsr5900/maddu.c | 70 +++++++++++++++++++++++++++ 7 files changed, 240 insertions(+), 13 deletions(-) create mode 100644 tests/tcg/mips/mipsr5900/madd.c create mode 100644 tests/tcg/mips/mipsr5900/maddu.c
Signature · 1 line
2.18.1
PATCH 1/11 target/mips: Rename ASE_MMI to ASE_TOSHIBA_MMI, with Toshiba namespace
Several vendors have multimedia instruction (MMI) sets and other extensions of various kinds. ASE vendor namespaces make it clear these are not generic architectural features and also avoid name clashes.
--- target/mips/mips-defs.h | 2 +- target/mips/translate.c | 3 ++- target/mips/translate_init.inc.c | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-)
target/mips/mips-defs.h +1 -1
@@ -68,7 +68,7 @@/* * bits 56-63: vendor-specific ASEs */ -#define ASE_MMI 0x0100000000000000ULL +#define ASE_TOSHIBA_MMI 0x0100000000000000ULL/* MIPS CPU defines. */ #define CPU_MIPS1 (ISA_MIPS1)
target/mips/translate.c +2 -1
@@ -26092,7 +26092,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)decode_opc_special (env, ctx);break ;case OPC_SPECIAL2 : -if ((ctx->insn_flags &INSN_R5900 ) && (ctx->insn_flags &ASE_MMI )) { +if ((ctx->insn_flags &INSN_R5900 ) && + (ctx->insn_flags &ASE_TOSHIBA_MMI )) {decode_tx79_mmi (env, ctx); }else {decode_opc_special2_legacy (env, ctx);
target/mips/translate_init.inc.c +1 -1
@@ -466,7 +466,7 @@ const mips_def_t mips_defs[] =#endif /* !CONFIG_USER_ONLY */ .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_R5900 | ASE_MMI, + .insn_flags = CPU_R5900 | ASE_TOSHIBA_MMI, .mmu_type = MMU_TYPE_R4000, }, {
Signature · 1 line
2.18.1
PATCH 2/11 target/mips: R5900 LQ and SQ also belong to the Toshiba MMI ASE
In reply to Fredrik Noring--- target/mips/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
target/mips/translate.c +4 -2
@@ -26100,7 +26100,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) }break ;case OPC_SPECIAL3 : -if (ctx->insn_flags &INSN_R5900 ) { +if ((ctx->insn_flags &INSN_R5900 ) && + (ctx->insn_flags &ASE_TOSHIBA_MMI )) {decode_tx79_sq (env, ctx);/* TX79_SQ */ }else {decode_opc_special3 (env, ctx);
@@ -26764,7 +26765,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) }break ;case OPC_MSA :/* OPC_MDMX */ -if (ctx->insn_flags &INSN_R5900 ) { +if ((ctx->insn_flags &INSN_R5900 ) && + (ctx->insn_flags &ASE_TOSHIBA_MMI )) {decode_tx79_lq (env, ctx);/* TX79_LQ */ }else {/* MDMX: Not implemented. */
Signature · 1 line
2.18.1
PATCH 3/11 target/mips: Support Toshiba specific three-operand MADD and MADDU
In reply to Fredrik NoringFrom: Philippe Mathieu-Daudé <[email protected]>
The three-operand MADD and MADDU are specific to the Toshiba TX19/TX39/TX79 cores.
The "32-Bit TX System RISC TX39 Family Architecture manual" is available at https://wiki.qemu.org/File:DSAE0022432.pdf
--- target/mips/translate.c | 58 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 53 insertions(+), 5 deletions(-)
target/mips/translate.c +53 -5
@@ -4801,8 +4801,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, }/* -* These MULT and MULTU instructions implemented in for example the -* Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core +* These MULT[U] and MADD[U] instructions implemented in for example +* the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core * architectures are special three-operand variants with the syntax * * MULT[U][1] rd, rs, rt
@@ -4811,6 +4811,14 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,* * (rd, LO, HI) <- rs * rt * +* and +* +* MADD[U] rd, rs, rt +* +* such that +* +* (rd, LO, HI) <- (LO, HI) + rs * rt +* * where the low-order 32-bits of the result is placed into both the * GPR rd and the special register LO. The high-order 32-bits of the * result is placed into the special register HI.
@@ -4867,8 +4875,48 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,tcg_temp_free_i32 (t3); }break ; +case TX79_MMI_MADD : + { +TCGv_i64 t2 =tcg_temp_new_i64 (); +TCGv_i64 t3 =tcg_temp_new_i64 (); + +tcg_gen_ext_tl_i64 (t2, t0); +tcg_gen_ext_tl_i64 (t3, t1); +tcg_gen_mul_i64 (t2, t2, t3); +tcg_gen_concat_tl_i64 (t3, cpu_LO[acc], cpu_HI[acc]); +tcg_gen_add_i64 (t2, t2, t3); +tcg_temp_free_i64 (t3); +gen_move_low32 (cpu_LO[acc], t2); +gen_move_high32 (cpu_HI[acc], t2); +if (rd) { +gen_move_low32 (cpu_gpr[rd], t2); + } +tcg_temp_free_i64 (t2); + } +break ; +case TX79_MMI_MADDU : + { +TCGv_i64 t2 =tcg_temp_new_i64 (); +TCGv_i64 t3 =tcg_temp_new_i64 (); + +tcg_gen_ext32u_tl (t0, t0); +tcg_gen_ext32u_tl (t1, t1); +tcg_gen_extu_tl_i64 (t2, t0); +tcg_gen_extu_tl_i64 (t3, t1); +tcg_gen_mul_i64 (t2, t2, t3); +tcg_gen_concat_tl_i64 (t3, cpu_LO[acc], cpu_HI[acc]); +tcg_gen_add_i64 (t2, t2, t3); +tcg_temp_free_i64 (t3); +gen_move_low32 (cpu_LO[acc], t2); +gen_move_high32 (cpu_HI[acc], t2); +if (rd) { +gen_move_low32 (cpu_gpr[rd], t2); + } +tcg_temp_free_i64 (t2); + } +break ;default : -MIPS_INVAL ("mul TXx9" ); +MIPS_INVAL ("mul/madd TXx9" );generate_exception_end (ctx,EXCP_RI ); goto out; }
@@ -24699,6 +24747,8 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)break ;case TX79_MMI_MULT1 :case TX79_MMI_MULTU1 : +case TX79_MMI_MADD : +case TX79_MMI_MADDU :gen_mul_txx9 (ctx, opc, rd, rs, rt);break ;case TX79_MMI_DIV1 :
@@ -24713,8 +24763,6 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)case TX79_MMI_MFHI1 :gen_HILO (ctx, opc,1 , rd);break ; -case TX79_MMI_MADD :/* TODO: TX79_MMI_MADD */ -case TX79_MMI_MADDU :/* TODO: TX79_MMI_MADDU */ case TX79_MMI_PLZCW :/* TODO: TX79_MMI_PLZCW */ case TX79_MMI_MADD1 :/* TODO: TX79_MMI_MADD1 */ case TX79_MMI_MADDU1 :/* TODO: TX79_MMI_MADDU1 */
Signature · 1 line
2.18.1
PATCH 4/11 target/mips: Support R5900 three-operand MADD1 and MADDU1
In reply to Fredrik Noring--- target/mips/translate.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)
target/mips/translate.c +9 -3
@@ -4813,7 +4813,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,* * and * -* MADD[U] rd, rs, rt +* MADD[U][1] rd, rs, rt * * such that *
@@ -4875,6 +4875,9 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,tcg_temp_free_i32 (t3); }break ; +case TX79_MMI_MADD1 : + acc =1 ; +/* Fall through */ case TX79_MMI_MADD : {TCGv_i64 t2 =tcg_temp_new_i64 ();
@@ -4894,6 +4897,9 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,tcg_temp_free_i64 (t2); }break ; +case TX79_MMI_MADDU1 : + acc =1 ; +/* Fall through */ case TX79_MMI_MADDU : {TCGv_i64 t2 =tcg_temp_new_i64 ();
@@ -24749,6 +24755,8 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)case TX79_MMI_MULTU1 :case TX79_MMI_MADD :case TX79_MMI_MADDU : +case TX79_MMI_MADD1 : +case TX79_MMI_MADDU1 :gen_mul_txx9 (ctx, opc, rd, rs, rt);break ;case TX79_MMI_DIV1 :
@@ -24764,8 +24772,6 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)gen_HILO (ctx, opc,1 , rd);break ;case TX79_MMI_PLZCW :/* TODO: TX79_MMI_PLZCW */ -case TX79_MMI_MADD1 :/* TODO: TX79_MMI_MADD1 */ -case TX79_MMI_MADDU1 :/* TODO: TX79_MMI_MADDU1 */ case TX79_MMI_PMFHL :/* TODO: TX79_MMI_PMFHL */ case TX79_MMI_PMTHL :/* TODO: TX79_MMI_PMTHL */ case TX79_MMI_PSLLH :/* TODO: TX79_MMI_PSLLH */
Signature · 1 line
2.18.1
PATCH 5/11 tests/tcg/mips: Test R5900 three-operand MADD
In reply to Fredrik Noring--- tests/tcg/mips/mipsr5900/Makefile | 1 + tests/tcg/mips/mipsr5900/madd.c | 45 +++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 tests/tcg/mips/mipsr5900/madd.c
tests/tcg/mips/mipsr5900/Makefile +1 -0
@@ -10,6 +10,7 @@ CFLAGS = -Wall -mabi=32 -march=r5900 -static TESTCASES = div1.tst TESTCASES += divu1.tst +TESTCASES += madd.tst TESTCASES += mflohi1.tst TESTCASES += mtlohi1.tst TESTCASES += mult.tst
tests/tcg/mips/mipsr5900/madd.c new file +45 -0
45 lines not on this page · raw message
Signature · 1 line
2.18.1
PATCH 6/11 tests/tcg/mips: Test R5900 three-operand MADD1
In reply to Fredrik Noring--- tests/tcg/mips/mipsr5900/madd.c | 43 +++++++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 5 deletions(-)
tests/tcg/mips/mipsr5900/madd.c +38 -5
@@ -1,5 +1,5 @@/* -* Test R5900-specific three-operand MADD. +* Test R5900-specific three-operand MADD and MADD1. */ #include <stdio.h>
@@ -29,12 +29,45 @@ int64_t madd(int64_t a, int32_t rs, int32_t rt)return r; } +int64_t madd1 (int64_t a,int32_t rs,int32_t rt) +{ +int32_t lo = a; +int32_t hi = a >>32 ; +int32_t rd; +int64_t r; + + __asm__ __volatile__ ( +" mtlo1 %5\n" +" mthi1 %6\n" +" madd1 %0, %3, %4\n" +" mflo1 %1\n" +" mfhi1 %2\n" + :"=r" (rd),"=r" (lo),"=r" (hi) + :"r" (rs),"r" (rt),"r" (lo),"r" (hi)); + r = ((int64_t )hi <<32 ) | (uint32_t )lo; + +assert (a + (int64_t )rs * rt == r); +assert (rd == lo); + +return r; +} + +static int64_t madd_variants (int64_t a,int32_t rs,int32_t rt) +{ +int64_t rd =madd (a, rs, rt); +int64_t rd1 =madd1 (a, rs, rt); + +assert (rd == rd1); + +return rd; +} +static void verify_madd (int64_t a,int32_t rs,int32_t rt,int64_t expected) { -assert (madd (a, rs, rt) == expected); -assert (madd (a, -rs, rt) == a + a - expected); -assert (madd (a, rs, -rt) == a + a - expected); -assert (madd (a, -rs, -rt) == expected); +assert (madd_variants (a, rs, rt) == expected); +assert (madd_variants (a, -rs, rt) == a + a - expected); +assert (madd_variants (a, rs, -rt) == a + a - expected); +assert (madd_variants (a, -rs, -rt) == expected); }int main ()
Signature · 1 line
2.18.1
PATCH 7/11 tests/tcg/mips: Test R5900 three-operand MADDU
In reply to Fredrik Noring--- tests/tcg/mips/mipsr5900/Makefile | 1 + tests/tcg/mips/mipsr5900/maddu.c | 37 +++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 tests/tcg/mips/mipsr5900/maddu.c
tests/tcg/mips/mipsr5900/Makefile +1 -0
@@ -11,6 +11,7 @@ CFLAGS = -Wall -mabi=32 -march=r5900 -static TESTCASES = div1.tst TESTCASES += divu1.tst TESTCASES += madd.tst +TESTCASES += maddu.tst TESTCASES += mflohi1.tst TESTCASES += mtlohi1.tst TESTCASES += mult.tst
tests/tcg/mips/mipsr5900/maddu.c new file +37 -0
@@ -0,0 +1,37 @@ +/* +* Test R5900-specific three-operand MADDU. +*/ + +#include <stdio.h> +#include <inttypes.h> +#include <assert.h> + +uint64_t maddu (uint64_t a,uint32_t rs,uint32_t rt) +{ +uint32_t lo = a; +uint32_t hi = a >>32 ; +uint32_t rd; +uint64_t r; + + __asm__ __volatile__ ( +" mtlo %5\n" +" mthi %6\n" +" maddu %0, %3, %4\n" +" mflo %1\n" +" mfhi %2\n" + :"=r" (rd),"=r" (lo),"=r" (hi) + :"r" (rs),"r" (rt),"r" (lo),"r" (hi)); + r = ((uint64_t )hi <<32 ) | (uint32_t )lo; + +assert (a + (uint64_t )rs * rt == r); +assert (rd == lo); + +return r; +} + +int main () +{ +assert (maddu (13 ,17 ,19 ) ==336 ); + +return 0 ; +}
Signature · 1 line
2.18.1
PATCH 8/11 tests/tcg/mips: Test R5900 three-operand MADDU1
In reply to Fredrik Noring--- tests/tcg/mips/mipsr5900/maddu.c | 37 ++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-)
tests/tcg/mips/mipsr5900/maddu.c +35 -2
@@ -1,5 +1,5 @@/* -* Test R5900-specific three-operand MADDU. +* Test R5900-specific three-operand MADDU and MADDU1. */ #include <stdio.h>
@@ -29,9 +29,42 @@ uint64_t maddu(uint64_t a, uint32_t rs, uint32_t rt)return r; } +uint64_t maddu1 (uint64_t a,uint32_t rs,uint32_t rt) +{ +uint32_t lo = a; +uint32_t hi = a >>32 ; +uint32_t rd; +uint64_t r; + + __asm__ __volatile__ ( +" mtlo1 %5\n" +" mthi1 %6\n" +" maddu1 %0, %3, %4\n" +" mflo1 %1\n" +" mfhi1 %2\n" + :"=r" (rd),"=r" (lo),"=r" (hi) + :"r" (rs),"r" (rt),"r" (lo),"r" (hi)); + r = ((uint64_t )hi <<32 ) | (uint32_t )lo; + +assert (a + (uint64_t )rs * rt == r); +assert (rd == lo); + +return r; +} + +static int64_t maddu_variants (int64_t a,int32_t rs,int32_t rt) +{ +int64_t rd =maddu (a, rs, rt); +int64_t rd1 =maddu1 (a, rs, rt); + +assert (rd == rd1); + +return rd; +} +int main () { -assert (maddu (13 ,17 ,19 ) ==336 ); +assert (maddu_variants (13 ,17 ,19 ) ==336 );return 0 ; }
Signature · 1 line
2.18.1
PATCH 9/11 disas/mips: Increase 'member of ISAs' flag holder size
In reply to Fredrik NoringFrom: Philippe Mathieu-Daudé <[email protected]>
Increase the size of 'membership' holder size to 64 bits. This is needed for future extensions since existing bits are almost all used. This change is related to commit f9c9cd63e3 "target/mips: Increase 'supported ISAs/ASEs' flag holder size".
--- disas/mips.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
disas/mips.c +1 -1
@@ -301,7 +301,7 @@ struct mips_opcodeunsigned long pinfo2;/* A collection of bits describing the instruction sets of which this instruction or macro is a member. */ -unsigned long membership; +uint64_t membership; };/* These are the characters which may appear in the args field of an
Signature · 1 line
2.18.1
PATCH 10/11 disas/mips: Define R5900 disassembly constants
In reply to Fredrik NoringAmend definition for MIPS ISAs in disassembler with R5900.
--- disas/mips.c | 8 ++++++++ 1 file changed, 8 insertions(+)
disas/mips.c +8 -0
@@ -611,6 +611,9 @@ struct mips_opcode/* ST Microelectronics Loongson 2F. */ #define INSN_LOONGSON_2F 0x80000000 +/* Sony/Toshiba R5900 */ +#define INSN_5900 0x100000000 +/* MIPS ISA defines, use instead of hardcoding ISA level. */ #define ISA_UNKNOWN 0/* Gas internal use. */
@@ -646,6 +649,7 @@ struct mips_opcode#define CPU_R5000 5000#define CPU_VR5400 5400#define CPU_VR5500 5500 +#define CPU_R5900 5900#define CPU_R6000 6000#define CPU_RM7000 7000#define CPU_R8000 8000
@@ -1193,6 +1197,7 @@ extern const int bfd_mips16_num_opcodes;#define N5 (INSN_5400 | INSN_5500)#define N54 INSN_5400#define N55 INSN_5500 +#define EE INSN_5900/* Emotion Engine */ #define G1 (T3 \ )
@@ -3861,6 +3866,7 @@ struct mips_arch_choice#define bfd_mach_mips5000 5000#define bfd_mach_mips5400 5400#define bfd_mach_mips5500 5500 +#define bfd_mach_mips5900 5900#define bfd_mach_mips6000 6000#define bfd_mach_mips7000 7000#define bfd_mach_mips8000 8000
@@ -3908,6 +3914,8 @@ static const struct mips_arch_choice mips_arch_choices[] = mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
Signature · 1 line
2.18.1
PATCH 11/11 disas/mips: Disassemble R5900 DIV[U]1, M{F, T}{LO, HI}1 and MULT[U]1
In reply to Fredrik NoringDisassemble the R5900 instructions DIV1, DIVU1, MFLO1, MTLO1, MFHI1, MTHI1, MULT1 and MULTU1.
--- disas/mips.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
disas/mips.c +12 -0
@@ -2323,6 +2323,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 }, {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 }, +{"div1", "z,s,t", 0x7000001a, 0xfc00ffff, RD_s | RD_t | WR_HILO, 0, EE }, +{"div1", "z,t", 0x7000001a, 0xffe0ffff, RD_s | RD_t | WR_HILO, 0, EE }, {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, {"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
@@ -2331,6 +2333,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 }, {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 }, +{"divu1", "z,s,t", 0x7000001b, 0xfc00ffff, RD_s | RD_t | WR_HILO, 0, EE }, +{"divu1", "z,t", 0x7000001b, 0xffe0ffff, RD_s | WR_HILO , 0, EE }, {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 }, {"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 }, {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */
@@ -2594,8 +2598,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 }, {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 }, +{"mfhi1", "d", 0x70000010, 0xffff07ff, WR_d | RD_HI, 0, EE}, {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 }, +{"mflo1", "d", 0x70000012, 0xffff07ff, WR_d | RD_LO, 0, EE}, {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT }, {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -2661,8 +2667,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 }, {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 }, +{"mthi1", "s", 0x70000011, 0xfc1fffff, RD_s | WR_HI, 0, EE }, {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 }, +{"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_s | WR_LO, 0, EE }, {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT }, {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
@@ -2728,10 +2736,14 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, {"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +{"mult1", "s,t", 0x70000018, 0xfc00ffff, RD_s | RD_t | WR_HILO | IS_M, 0, EE }, +{"mult1", "d,s,t", 0x70000018, 0xfc0007ff, WR_d | RD_s | RD_t | WR_HILO | IS_M, 0, EE }, {"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, {"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +{"multu1", "s,t", 0x70000019, 0xfc00ffff, RD_s | RD_t | WR_HILO | IS_M, 0, EE }, +{"multu1", "d,s,t", 0x70000019, 0xfc0007ff, WR_d | RD_s | RD_t | WR_HILO | IS_M, 0, EE }, {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */ {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */
Signature · 1 line
2.18.1
Re: [Qemu-devel] [PATCH 01/11] target/mips: Rename ASE_MMI to ASE_TOSHIBA_MMI, with Toshiba namespace
In reply to Fredrik NoringQuoted 6 lines
From: Fredrik Noring <[email protected]>
Subject: [PATCH 01/11] target/mips: RenameASE_MMItoASE_TOSHIBA_MMI, with Toshiba namespaceSeveral vendors have multimedia instruction (MMI) sets and other extensions of various kinds. ASE vendor namespaces make it clear these are not generic architectural features and also avoid name clashes.
ASE_XXX flags are not meant to identify a CPU or vendor. They are not wired to any configuration bit or CPU model. They are purely QEMU internal constructs, whose purpose was to make internal QEMU MIPS-specific code organization easier. In this case, ASE_MMI is an umbrella for all MMI-like ASEs, introduced with intent to make encapsulation of MMI-specific code better and easier. Differences between CPUs should be resolved by other means. Name 'ASE_MMI' is fine.
Thanks,
Aleksandar