Add RISC-V TCG backend support
v2 cover Add RISC-V TCG backend support
This patch set adds RISC-V backend support to QEMU. This is based on Michael Clark's original work with extra work on top.
This has been somewhat tested and can run other architecture softmmu code. It seems that any complex OS will eventually hang, but we can run the BIOS and OS startup code for a number of different operating systems.
I haven't tested linux user support at all yet. I think Michael had that working reliably though and hopefully my changes haven't broken it.
There are still some todos in the code (there are missing instructions and byte swapping) but these should assert instead of generating invalid code.
This branch can be found here:
https://github.com/alistair23/qemu/tree/mainline/alistair/tcg-backend-upstream.next
v2:
- define TCG_TARGET_HAS_MEMORY_BSWAP
- Fix new TCG MAINTAINERS entry
- Rebase ontop of Richard's patch_reloc() changes
v1:
- Fix long jump with slowpath load/stores
RFC v3:
- Update the MAINTAINERS file
- Enusre that RISC-V 32-bit works
- More changes based on Richard's feedback and contributions
RFC v2:
- A large number of changes based on Richard's feedback
Alistair Francis (23):
elf.h: Add the RISCV ELF magic numbers
linux-user: Add host dependency for RISC-V 32-bit
linux-user: Add host dependency for RISC-V 64-bit
exec: Add RISC-V GCC poison macro
riscv: Add the tcg-target header file
riscv: Add the tcg target registers
riscv: tcg-target: Add support for the constraints
riscv: tcg-target: Add the immediate encoders
riscv: tcg-target: Add the instruction emitters
riscv: tcg-target: Add the relocation functions
riscv: tcg-target: Add the mov and movi instruction
riscv: tcg-target: Add the extract instructions
riscv: tcg-target: Add the out load and store instructions
riscv: tcg-target: Add the add2 and sub2 instructions
riscv: tcg-target: Add branch and jump instructions
riscv: tcg-target: Add slowpath load and store instructions
riscv: tcg-target: Add direct load and store instructions
riscv: tcg-target: Add the out op decoder
riscv: tcg-target: Add the prologue generation and register the JIT
riscv: tcg-target: Add the target init code
tcg: Add RISC-V cpu signal handler
dias: Add RISC-V support
configure: Add support for building RISC-V host
MAINTAINERS | 12 +- accel/tcg/user-exec.c | 75 ++ configure | 12 +- disas.c | 10 +- include/elf.h | 55 + include/exec/poison.h | 1 + linux-user/host/riscv32/hostdep.h | 11 + linux-user/host/riscv64/hostdep.h | 11 + tcg/riscv/tcg-target.h | 177 +++ tcg/riscv/tcg-target.inc.c | 1946 +++++++++++++++++++++++++++++ 10 files changed, 2305 insertions(+), 5 deletions(-) create mode 100644 linux-user/host/riscv32/hostdep.h create mode 100644 linux-user/host/riscv64/hostdep.h create mode 100644 tcg/riscv/tcg-target.h create mode 100644 tcg/riscv/tcg-target.inc.c
Signature · 1 line
2.19.1
PATCH v2 1/23 elf.h: Add the RISCV ELF magic numbers
--- include/elf.h | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+)
include/elf.h +55 -0
@@ -1338,6 +1338,61 @@ typedef struct {#define R_IA64_DTPREL64LSB 0xb7/* @dtprel(sym + add), data8 LSB */ #define R_IA64_LTOFF_DTPREL22 0xba/* @ltoff(@dtprel(s+a)), imm22 */ +/* RISC-V relocations. */ +#define R_RISCV_NONE 0 +#define R_RISCV_32 1 +#define R_RISCV_64 2 +#define R_RISCV_RELATIVE 3 +#define R_RISCV_COPY 4 +#define R_RISCV_JUMP_SLOT 5 +#define R_RISCV_TLS_DTPMOD32 6 +#define R_RISCV_TLS_DTPMOD64 7 +#define R_RISCV_TLS_DTPREL32 8 +#define R_RISCV_TLS_DTPREL64 9 +#define R_RISCV_TLS_TPREL32 10 +#define R_RISCV_TLS_TPREL64 11 +#define R_RISCV_BRANCH 16 +#define R_RISCV_JAL 17 +#define R_RISCV_CALL 18 +#define R_RISCV_CALL_PLT 19 +#define R_RISCV_GOT_HI20 20 +#define R_RISCV_TLS_GOT_HI20 21 +#define R_RISCV_TLS_GD_HI20 22 +#define R_RISCV_PCREL_HI20 23 +#define R_RISCV_PCREL_LO12_I 24 +#define R_RISCV_PCREL_LO12_S 25 +#define R_RISCV_HI20 26 +#define R_RISCV_LO12_I 27 +#define R_RISCV_LO12_S 28 +#define R_RISCV_TPREL_HI20 29 +#define R_RISCV_TPREL_LO12_I 30 +#define R_RISCV_TPREL_LO12_S 31 +#define R_RISCV_TPREL_ADD 32 +#define R_RISCV_ADD8 33 +#define R_RISCV_ADD16 34 +#define R_RISCV_ADD32 35 +#define R_RISCV_ADD64 36 +#define R_RISCV_SUB8 37 +#define R_RISCV_SUB16 38 +#define R_RISCV_SUB32 39 +#define R_RISCV_SUB64 40 +#define R_RISCV_GNU_VTINHERIT 41 +#define R_RISCV_GNU_VTENTRY 42 +#define R_RISCV_ALIGN 43 +#define R_RISCV_RVC_BRANCH 44 +#define R_RISCV_RVC_JUMP 45 +#define R_RISCV_RVC_LUI 46 +#define R_RISCV_GPREL_I 47 +#define R_RISCV_GPREL_S 48 +#define R_RISCV_TPREL_I 49 +#define R_RISCV_TPREL_S 50 +#define R_RISCV_RELAX 51 +#define R_RISCV_SUB6 52 +#define R_RISCV_SET6 53 +#define R_RISCV_SET8 54 +#define R_RISCV_SET16 55 +#define R_RISCV_SET32 56 + typedef struct elf32_rel { Elf32_Addr r_offset; Elf32_Word r_info;
Signature · 1 line
2.19.1
PATCH v2 2/23 linux-user: Add host dependency for RISC-V 32-bit
In reply to Alistair Francis--- MAINTAINERS | 1 + linux-user/host/riscv32/hostdep.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 linux-user/host/riscv32/hostdep.h
MAINTAINERS +1 -0
@@ -266,6 +266,7 @@ S: Maintained F: target/riscv/ F: hw/riscv/ F: include/hw/riscv/ +F: linux-user/host/riscv32/ F: disas/riscv.c S390
linux-user/host/riscv32/hostdep.h new file +11 -0
@@ -0,0 +1,11 @@ +/* +* hostdep.h : things which are dependent on the host architecture +* +* This work is licensed under the terms of the GNU GPL, version 2 or later. +* See the COPYING file in the top-level directory. +*/ + +#ifndef RISCV32_HOSTDEP_H +#define RISCV32_HOSTDEP_H + +#endif
Signature · 1 line
2.19.1
PATCH v2 3/23 linux-user: Add host dependency for RISC-V 64-bit
In reply to Alistair Francis--- MAINTAINERS | 1 + linux-user/host/riscv64/hostdep.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 linux-user/host/riscv64/hostdep.h
MAINTAINERS +1 -0
@@ -267,6 +267,7 @@ F: target/riscv/ F: hw/riscv/ F: include/hw/riscv/ F: linux-user/host/riscv32/ +F: linux-user/host/riscv64/ F: disas/riscv.c S390
linux-user/host/riscv64/hostdep.h new file +11 -0
@@ -0,0 +1,11 @@ +/* +* hostdep.h : things which are dependent on the host architecture +* +* This work is licensed under the terms of the GNU GPL, version 2 or later. +* See the COPYING file in the top-level directory. +*/ + +#ifndef RISCV64_HOSTDEP_H +#define RISCV64_HOSTDEP_H + +#endif
Signature · 1 line
2.19.1
PATCH v2 4/23 exec: Add RISC-V GCC poison macro
In reply to Alistair Francis--- include/exec/poison.h | 1 + 1 file changed, 1 insertion(+)
include/exec/poison.h +1 -0
@@ -79,6 +79,7 @@#pragma GCC poison CONFIG_MOXIE_DIS#pragma GCC poison CONFIG_NIOS2_DIS#pragma GCC poison CONFIG_PPC_DIS +#pragma GCC poison CONFIG_RISCV_DIS#pragma GCC poison CONFIG_S390_DIS#pragma GCC poison CONFIG_SH4_DIS#pragma GCC poison CONFIG_SPARC_DIS
Signature · 1 line
2.19.1
PATCH v2 5/23 riscv: Add the tcg-target header file
In reply to Alistair Francis--- MAINTAINERS | 10 ++- tcg/riscv/tcg-target.h | 177 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 186 insertions(+), 1 deletion(-) create mode 100644 tcg/riscv/tcg-target.h
MAINTAINERS +9 -1
@@ -268,7 +268,6 @@ F: hw/riscv/ F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ -F: disas/riscv.c S390 M: Richard Henderson <[email protected]>
@@ -2166,6 +2165,15 @@ S: Odd Fixes F: tcg/ppc/ F: disas/ppc.c +RISC-V +M: Michael Clark <[email protected]> +M: Palmer Dabbelt <[email protected]> +M: Alistair Francis <[email protected]> +L: [email protected] +S: Maintained +F: tcg/riscv/ +F: disas/riscv.c + S390 target M: Richard Henderson <[email protected]> S: Maintained
tcg/riscv/tcg-target.h new file +177 -0
177 lines not on this page · raw message
Signature · 1 line
2.19.1
PATCH v2 6/23 riscv: Add the tcg target registers
In reply to Alistair Francis--- tcg/riscv/tcg-target.inc.c | 118 +++++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 tcg/riscv/tcg-target.inc.c
tcg/riscv/tcg-target.inc.c new file +118 -0
@@ -0,0 +1,118 @@ +/* +* Tiny Code Generator for QEMU +* +* Copyright (c) 2018 SiFive, Inc +* Copyright (c) 2008-2009 Arnaud Patard <[email protected]> +* Copyright (c) 2009 Aurelien Jarno <[email protected]> +* Copyright (c) 2008 Fabrice Bellard +* +* Based on i386/tcg-target.c and mips/tcg-target.c +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +*/ + +#include "tcg-pool.inc.c" + +#ifdef CONFIG_DEBUG_TCG +static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS ] = { +"zero" , +"ra" , +"sp" , +"gp" , +"tp" , +"t0" , +"t1" , +"t2" , +"s0" , +"s1" , +"a0" , +"a1" , +"a2" , +"a3" , +"a4" , +"a5" , +"a6" , +"a7" , +"s2" , +"s3" , +"s4" , +"s5" , +"s6" , +"s7" , +"s8" , +"s9" , +"s10" , +"s11" , +"t3" , +"t4" , +"t5" , +"t6" +}; +#endif + +static const int tcg_target_reg_alloc_order[] = { +/* Call saved registers */ +/* TCG_REG_S0 reservered for TCG_AREG0 */ +TCG_REG_S1 , +TCG_REG_S2 , +TCG_REG_S3 , +TCG_REG_S4 , +TCG_REG_S5 , +TCG_REG_S6 , +TCG_REG_S7 , +TCG_REG_S8 , +TCG_REG_S9 , +TCG_REG_S10 , +TCG_REG_S11 , + +/* Call clobbered registers */ +TCG_REG_T0 , +TCG_REG_T1 , +TCG_REG_T2 , +TCG_REG_T3 , +TCG_REG_T4 , +TCG_REG_T5 , +TCG_REG_T6 , + +/* Argument registers */ +TCG_REG_A0 , +TCG_REG_A1 , +TCG_REG_A2 , +TCG_REG_A3 , +TCG_REG_A4 , +TCG_REG_A5 , +TCG_REG_A6 , +TCG_REG_A7 , +}; + +static const int tcg_target_call_iarg_regs[] = { +TCG_REG_A0 , +TCG_REG_A1 , +TCG_REG_A2 , +TCG_REG_A3 , +TCG_REG_A4 , +TCG_REG_A5 , +TCG_REG_A6 , +TCG_REG_A7 , +}; + +static const int tcg_target_call_oarg_regs[] = { +TCG_REG_A0 , +TCG_REG_A1 , +};
Signature · 1 line
2.19.1
PATCH v2 7/23 riscv: tcg-target: Add support for the constraints
In reply to Alistair Francis--- tcg/riscv/tcg-target.inc.c | 168 +++++++++++++++++++++++++++++++++++++ 1 file changed, 168 insertions(+)
tcg/riscv/tcg-target.inc.c +168 -0
@@ -116,3 +116,171 @@ static const int tcg_target_call_oarg_regs[] = {TCG_REG_A0 , TCG_REG_A1, }; + +#define TCG_CT_CONST_ZERO 0x100 +#define TCG_CT_CONST_S12 0x200 +#define TCG_CT_CONST_N12 0x400 +#define TCG_CT_CONST_M12 0x800 + +static inline tcg_target_long sextreg (tcg_target_long val,int pos,int len) +{ +if (TCG_TARGET_REG_BITS ==32 ) { +return sextract32 (val, pos, len); + }else { +return sextract64 (val, pos, len); + } +} + +/* parse target specific constraints */ +static const char *target_parse_constraint (TCGArgConstraint *ct, +const char *ct_str,TCGType type) +{ +switch (*ct_str++) { +case 'r' : + ct->ct |=TCG_CT_REG ; + ct->u.regs =0xffffffff ; +break ; +case 'L' : +/* qemu_ld/qemu_st constraint */ + ct->ct |=TCG_CT_REG ; + ct->u.regs =0xffffffff ; +/* qemu_ld/qemu_st uses TCG_REG_TMP0 */ +#if defined(CONFIG_SOFTMMU ) +tcg_regset_reset_reg (ct->u.regs, tcg_target_call_iarg_regs[0 ]); +tcg_regset_reset_reg (ct->u.regs, tcg_target_call_iarg_regs[1 ]); +tcg_regset_reset_reg (ct->u.regs, tcg_target_call_iarg_regs[2 ]); +tcg_regset_reset_reg (ct->u.regs, tcg_target_call_iarg_regs[3 ]); +tcg_regset_reset_reg (ct->u.regs, tcg_target_call_iarg_regs[4 ]); +#endif +break ; +case 'I' : + ct->ct |=TCG_CT_CONST_S12 ; +break ; +case 'N' : + ct->ct |=TCG_CT_CONST_N12 ; +break ; +case 'M' : + ct->ct |=TCG_CT_CONST_M12 ; +break ; +case 'Z' : +/* we can use a zero immediate as a zero register argument. */ + ct->ct |=TCG_CT_CONST_ZERO ; +break ; +default : +return NULL ; + } +return ct_str; +} + +/* test if a constant matches the constraint */ +static int tcg_target_const_match (tcg_target_long val,TCGType type, +const TCGArgConstraint *arg_ct) +{ +int ct = arg_ct->ct; +if (ct &TCG_CT_CONST ) { +return 1 ; + } +if ((ct &TCG_CT_CONST_ZERO ) && val ==0 ) { +return 1 ; + } +if ((ct &TCG_CT_CONST_S12 ) && val ==sextreg (val,0 ,12 )) { +return 1 ; + } +if ((ct &TCG_CT_CONST_N12 ) && -val ==sextreg (-val,0 ,12 )) { +return 1 ; + } +if ((ct &TCG_CT_CONST_M12 ) && val >=-0xfff && val <=0xfff ) { +return 1 ; + } +return 0 ; +} + +/* +* RISC-V Base ISA opcodes (IM) +*/ + +typedef enum { +OPC_ADD =0x33 , +OPC_ADDI =0x13 , +OPC_AND =0x7033 , +OPC_ANDI =0x7013 , +OPC_AUIPC =0x17 , +OPC_BEQ =0x63 , +OPC_BGE =0x5063 , +OPC_BGEU =0x7063 , +OPC_BLT =0x4063 , +OPC_BLTU =0x6063 , +OPC_BNE =0x1063 , +OPC_DIV =0x2004033 , +OPC_DIVU =0x2005033 , +OPC_JAL =0x6f , +OPC_JALR =0x67 , +OPC_LB =0x3 , +OPC_LBU =0x4003 , +OPC_LD =0x3003 , +OPC_LH =0x1003 , +OPC_LHU =0x5003 , +OPC_LUI =0x37 , +OPC_LW =0x2003 , +OPC_LWU =0x6003 , +OPC_MUL =0x2000033 , +OPC_MULH =0x2001033 , +OPC_MULHSU =0x2002033 , +OPC_MULHU =0x2003033 , +OPC_OR =0x6033 , +OPC_ORI =0x6013 , +OPC_REM =0x2006033 , +OPC_REMU =0x2007033 , +OPC_SB =0x23 , +OPC_SD =0x3023 , +OPC_SH =0x1023 , +OPC_SLL =0x1033 , +OPC_SLLI =0x1013 , +OPC_SLT =0x2033 , +OPC_SLTI =0x2013 , +OPC_SLTIU =0x3013 , +OPC_SLTU =0x3033 , +OPC_SRA =0x40005033 , +OPC_SRAI =0x40005013 , +OPC_SRL =0x5033 , +OPC_SRLI =0x5013 , +OPC_SUB =0x40000033 , +OPC_SW =0x2023 , +OPC_XOR =0x4033 , +OPC_XORI =0x4013 , + +#if TCG_TARGET_REG_BITS ==64 +OPC_ADDIW =0x1b , +OPC_ADDW =0x3b , +OPC_DIVUW =0x200503b , +OPC_DIVW =0x200403b , +OPC_MULW =0x200003b , +OPC_REMUW =0x200703b , +OPC_REMW =0x200603b , +OPC_SLLIW =0x101b , +OPC_SLLW =0x103b , +OPC_SRAIW =0x4000501b , +OPC_SRAW =0x4000503b , +OPC_SRLIW =0x501b , +OPC_SRLW =0x503b , +OPC_SUBW =0x4000003b , +#else +/* Simplify code throughout by defining aliases for RV32. */ +OPC_ADDIW =OPC_ADDI , +OPC_ADDW =OPC_ADD , +OPC_DIVUW =OPC_DIVU , +OPC_DIVW =OPC_DIV , +OPC_MULW =OPC_MUL , +OPC_REMUW =OPC_REMU , +OPC_REMW =OPC_REM , +OPC_SLLIW =OPC_SLLI , +OPC_SLLW =OPC_SLL , +OPC_SRAIW =OPC_SRAI , +OPC_SRAW =OPC_SRA , +OPC_SRLIW =OPC_SRLI , +OPC_SRLW =OPC_SRL , +OPC_SUBW =OPC_SUB , +#endif + +OPC_FENCE =0x0000000f , +}RISCVInsn ;
Signature · 1 line
2.19.1
PATCH v2 8/23 riscv: tcg-target: Add the immediate encoders
In reply to Alistair Francis--- tcg/riscv/tcg-target.inc.c | 90 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+)
tcg/riscv/tcg-target.inc.c +90 -0
@@ -284,3 +284,93 @@ typedef enum {OPC_FENCE =0x0000000f , } RISCVInsn; + +/* +* RISC-V immediate and instruction encoders (excludes 16-bit RVC) +*/ + +/* Type-R */ + +static int32_t encode_r (RISCVInsn opc,TCGReg rd,TCGReg rs1,TCGReg rs2) +{ +return opc | (rd &0x1f ) <<7 | (rs1 &0x1f ) <<15 | (rs2 &0x1f ) <<20 ; +} + +/* Type-I */ + +static int32_t encode_imm12 (uint32_t imm) +{ +return (imm &0xfff ) <<20 ; +} + +static int32_t encode_i (RISCVInsn opc,TCGReg rd,TCGReg rs1,uint32_t imm) +{ +return opc | (rd &0x1f ) <<7 | (rs1 &0x1f ) <<15 |encode_imm12 (imm); +} + +/* Type-S */ + +static int32_t encode_simm12 (uint32_t imm) +{ +int32_t ret =0 ; + + ret |= (imm &0xFE0 ) <<20 ; + ret |= (imm &0x1F ) <<7 ; + +return ret; +} + +static int32_t encode_s (RISCVInsn opc,TCGReg rs1,TCGReg rs2,uint32_t imm) +{ +return opc | (rs1 &0x1f ) <<15 | (rs2 &0x1f ) <<20 |encode_simm12 (imm); +} + +/* Type-SB */ + +static int32_t encode_sbimm12 (uint32_t imm) +{ +int32_t ret =0 ; + + ret |= (imm &0x1000 ) <<19 ; + ret |= (imm &0x7e0 ) <<20 ; + ret |= (imm &0x1e ) <<7 ; + ret |= (imm &0x800 ) >>4 ; + +return ret; +} + +static int32_t encode_sb (RISCVInsn opc,TCGReg rs1,TCGReg rs2,uint32_t imm) +{ +return opc | (rs1 &0x1f ) <<15 | (rs2 &0x1f ) <<20 |encode_sbimm12 (imm); +} + +/* Type-U */ + +static int32_t encode_uimm20 (uint32_t imm) +{ +return imm &0xfffff000 ; +} + +static int32_t encode_u (RISCVInsn opc,TCGReg rd,uint32_t imm) +{ +return opc | (rd &0x1f ) <<7 |encode_uimm20 (imm); +} + +/* Type-UJ */ + +static int32_t encode_ujimm20 (uint32_t imm) +{ +int32_t ret =0 ; + + ret |= (imm &0x0007fe ) << (21 -1 ); + ret |= (imm &0x000800 ) << (20 -11 ); + ret |= (imm &0x0ff000 ) << (12 -12 ); + ret |= (imm &0x100000 ) << (31 -20 ); + +return ret; +} + +static int32_t encode_uj (RISCVInsn opc,TCGReg rd,uint32_t imm) +{ +return opc | (rd &0x1f ) <<7 |encode_ujimm20 (imm); +}
Signature · 1 line
2.19.1
PATCH v2 9/23 riscv: tcg-target: Add the instruction emitters
In reply to Alistair Francis--- tcg/riscv/tcg-target.inc.c | 48 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+)
tcg/riscv/tcg-target.inc.c +48 -0
@@ -374,3 +374,51 @@ static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm) {return opc | (rd &0x1f ) <<7 |encode_ujimm20 (imm); } + +/* +* RISC-V instruction emitters +*/ + +static void tcg_out_opc_reg (TCGContext *s,RISCVInsn opc, +TCGReg rd,TCGReg rs1,TCGReg rs2) +{ +tcg_out32 (s,encode_r (opc, rd, rs1, rs2)); +} + +static void tcg_out_opc_imm (TCGContext *s,RISCVInsn opc, +TCGReg rd,TCGReg rs1,TCGArg imm) +{ +tcg_out32 (s,encode_i (opc, rd, rs1, imm)); +} + +static void tcg_out_opc_store (TCGContext *s,RISCVInsn opc, +TCGReg rs1,TCGReg rs2,uint32_t imm) +{ +tcg_out32 (s,encode_s (opc, rs1, rs2, imm)); +} + +static void tcg_out_opc_branch (TCGContext *s,RISCVInsn opc, +TCGReg rs1,TCGReg rs2,uint32_t imm) +{ +tcg_out32 (s,encode_sb (opc, rs1, rs2, imm)); +} + +static void tcg_out_opc_upper (TCGContext *s,RISCVInsn opc, +TCGReg rd,uint32_t imm) +{ +tcg_out32 (s,encode_u (opc, rd, imm)); +} + +static void tcg_out_opc_jump (TCGContext *s,RISCVInsn opc, +TCGReg rd,uint32_t imm) +{ +tcg_out32 (s,encode_uj (opc, rd, imm)); +} + +static void tcg_out_nop_fill (tcg_insn_unit *p,int count) +{ +int i; +for (i =0 ; i < count; ++i) { + p[i] =encode_i (OPC_ADDI ,TCG_REG_ZERO ,TCG_REG_ZERO ,0 ); + } +}
Signature · 1 line
2.19.1
PATCH v2 10/23 riscv: tcg-target: Add the relocation functions
In reply to Alistair Francis--- tcg/riscv/tcg-target.inc.c | 88 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+)
tcg/riscv/tcg-target.inc.c +88 -0
@@ -422,3 +422,91 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count) p[i] =encode_i (OPC_ADDI ,TCG_REG_ZERO ,TCG_REG_ZERO ,0 ); } } + +/* +* Relocations +*/ + +static bool reloc_sbimm12 (tcg_insn_unit *code_ptr,tcg_insn_unit *target) +{ +intptr_t offset = (intptr_t )target - (intptr_t )code_ptr; + +if (offset ==sextreg (offset,1 ,12 ) <<1 ) { + code_ptr[0 ] |=encode_sbimm12 (offset); +return true; + } + +return false; +} + +static bool reloc_jimm20 (tcg_insn_unit *code_ptr,tcg_insn_unit *target) +{ +intptr_t offset = (intptr_t )target - (intptr_t )code_ptr; + +if (offset ==sextreg (offset,1 ,20 ) <<1 ) { + code_ptr[0 ] |=encode_ujimm20 (offset); +return true; + } + +return false; +} + +static bool reloc_call (tcg_insn_unit *code_ptr,tcg_insn_unit *target) +{ +intptr_t offset = (intptr_t )target - (intptr_t )code_ptr; +int32_t lo =sextreg (offset,0 ,12 ); +int32_t hi = offset - lo; + +if (offset == hi + lo) { + code_ptr[0 ] |=encode_uimm20 (hi); + code_ptr[1 ] |=encode_imm12 (lo); +return true; + } + +return false; +} + +static bool patch_reloc (tcg_insn_unit *code_ptr,int type, +intptr_t value,intptr_t addend) +{ +uint32_t insn = *code_ptr; +intptr_t diff; +bool short_jmp; + +tcg_debug_assert (addend ==0 ); + +switch (type) { +case R_RISCV_BRANCH : + diff = value - (uintptr_t )code_ptr; + short_jmp = diff ==sextreg (diff,0 ,12 ); +if (short_jmp) { +return reloc_sbimm12 (code_ptr, (tcg_insn_unit *)value); + }else { +/* Invert the condition */ + insn = insn ^ (1 <<12 ); +/* Clear the offset */ + insn &=0x01fff07f ; +/* Set the offset to the PC + 8 */ + insn |=encode_sbimm12 (8 ); + +/* Move forward */ + code_ptr[0 ] = insn; + +/* Overwrite the NOP with jal x0,value */ + diff = value - (uintptr_t )(code_ptr +1 ); + insn =encode_uj (OPC_JAL ,TCG_REG_ZERO , diff); + code_ptr[1 ] = insn; + +return true; + } +break ; +case R_RISCV_JAL : +return reloc_jimm20 (code_ptr, (tcg_insn_unit *)value); +break ; +case R_RISCV_CALL : +return reloc_call (code_ptr, (tcg_insn_unit *)value); +break ; +default : +tcg_abort (); + } +}
Signature · 1 line
2.19.1
PATCH v2 11/23 riscv: tcg-target: Add the mov and movi instruction
In reply to Alistair Francis--- tcg/riscv/tcg-target.inc.c | 86 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+)
tcg/riscv/tcg-target.inc.c +86 -0
@@ -510,3 +510,89 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,tcg_abort (); } } + +/* +* TCG intrinsics +*/ + +static void tcg_out_mov (TCGContext *s,TCGType type,TCGReg ret,TCGReg arg) +{ +if (ret == arg) { +return ; + } +switch (type) { +case TCG_TYPE_I32 : +case TCG_TYPE_I64 : +tcg_out_opc_imm (s,OPC_ADDI , ret, arg,0 ); +break ; +default : +g_assert_not_reached (); + } +} + +static void tcg_out_movi (TCGContext *s,TCGType type,TCGReg rd, +tcg_target_long val) +{ +tcg_target_long lo, hi, tmp; +int shift, ret; + +if (TCG_TARGET_REG_BITS ==64 && type ==TCG_TYPE_I32 ) { + val = (int32_t )val; + } + + lo =sextreg (val,0 ,12 ); +if (val == lo) { +tcg_out_opc_imm (s,OPC_ADDI , rd,TCG_REG_ZERO , lo); +return ; + } + + hi = val - lo; +if (TCG_TARGET_REG_BITS ==32 || val == (int32_t )val) { +tcg_out_opc_upper (s,OPC_LUI , rd, hi); +if (lo !=0 ) { +tcg_out_opc_imm (s,OPC_ADDIW , rd, rd, lo); + } +return ; + } + +/* We can only be here if TCG_TARGET_REG_BITS != 32 */ + tmp =tcg_pcrel_diff (s, (void *)val); +if (tmp == (int32_t )tmp) { +tcg_out_opc_upper (s,OPC_AUIPC , rd,0 ); +tcg_out_opc_imm (s,OPC_ADDI , rd, rd,0 ); + ret =reloc_call (s->code_ptr -2 , (tcg_insn_unit *)val); +tcg_debug_assert (ret == true); +return ; + } + +/* Look for a single 20-bit section. */ + shift =ctz64 (val); + tmp = val >> shift; +if (tmp ==sextreg (tmp,0 ,20 )) { +tcg_out_opc_upper (s,OPC_LUI , rd, tmp <<12 ); +if (shift >12 ) { +tcg_out_opc_imm (s,OPC_SLLI , rd, rd, shift -12 ); + }else { +tcg_out_opc_imm (s,OPC_SRAI , rd, rd,12 - shift); + } +return ; + } + +/* Look for a few high zero bits, with lots of bits set in the middle. */ + shift =clz64 (val); + tmp = val << shift; +if (tmp ==sextreg (tmp,12 ,20 ) <<12 ) { +tcg_out_opc_upper (s,OPC_LUI , rd, tmp); +tcg_out_opc_imm (s,OPC_SRLI , rd, rd, shift); +return ; + }else if (tmp ==sextreg (tmp,0 ,12 )) { +tcg_out_opc_imm (s,OPC_ADDI , rd,TCG_REG_ZERO , tmp); +tcg_out_opc_imm (s,OPC_SRLI , rd, rd, shift); +return ; + } + +/* Drop into the constant pool. */ +new_pool_label (s, val,R_RISCV_CALL , s->code_ptr,0 ); +tcg_out_opc_upper (s,OPC_AUIPC , rd,0 ); +tcg_out_opc_imm (s,OPC_LD , rd, rd,0 ); +}
Signature · 1 line
2.19.1
PATCH v2 12/23 riscv: tcg-target: Add the extract instructions
In reply to Alistair Francis--- tcg/riscv/tcg-target.inc.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)
tcg/riscv/tcg-target.inc.c +34 -0
@@ -596,3 +596,37 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,tcg_out_opc_upper (s,OPC_AUIPC , rd,0 );tcg_out_opc_imm (s,OPC_LD , rd, rd,0 ); } + +static void tcg_out_ext8u (TCGContext *s,TCGReg ret,TCGReg arg) +{ +tcg_out_opc_imm (s,OPC_ANDI , ret, arg,0xff ); +} + +static void tcg_out_ext16u (TCGContext *s,TCGReg ret,TCGReg arg) +{ +tcg_out_opc_imm (s,OPC_SLLIW , ret, arg,16 ); +tcg_out_opc_imm (s,OPC_SRLIW , ret, ret,16 ); +} + +static void tcg_out_ext32u (TCGContext *s,TCGReg ret,TCGReg arg) +{ +tcg_out_opc_imm (s,OPC_SLLI , ret, arg,32 ); +tcg_out_opc_imm (s,OPC_SRLI , ret, ret,32 ); +} + +static void tcg_out_ext8s (TCGContext *s,TCGReg ret,TCGReg arg) +{ +tcg_out_opc_imm (s,OPC_SLLIW , ret, arg,24 ); +tcg_out_opc_imm (s,OPC_SRAIW , ret, ret,24 ); +} + +static void tcg_out_ext16s (TCGContext *s,TCGReg ret,TCGReg arg) +{ +tcg_out_opc_imm (s,OPC_SLLIW , ret, arg,16 ); +tcg_out_opc_imm (s,OPC_SRAIW , ret, ret,16 ); +} + +static void tcg_out_ext32s (TCGContext *s,TCGReg ret,TCGReg arg) +{ +tcg_out_opc_imm (s,OPC_ADDIW , ret, arg,0 ); +}
Signature · 1 line
2.19.1
PATCH v2 13/23 riscv: tcg-target: Add the out load and store instructions
In reply to Alistair Francis--- tcg/riscv/tcg-target.inc.c | 65 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+)
tcg/riscv/tcg-target.inc.c +65 -0
@@ -630,3 +630,68 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) {tcg_out_opc_imm (s,OPC_ADDIW , ret, arg,0 ); } + +static void tcg_out_ldst (TCGContext *s,RISCVInsn opc,TCGReg data, +TCGReg addr,intptr_t offset) +{ +intptr_t imm12 =sextreg (offset,0 ,12 ); + +if (offset != imm12) { +intptr_t diff = offset - (uintptr_t )s->code_ptr; + +if (addr ==TCG_REG_ZERO && diff == (int32_t )diff) { + imm12 =sextreg (diff,0 ,12 ); +tcg_out_opc_upper (s,OPC_AUIPC ,TCG_REG_TMP2 , diff - imm12); + }else { +tcg_out_movi (s,TCG_TYPE_PTR ,TCG_REG_TMP2 , offset - imm12); +if (addr !=TCG_REG_ZERO ) { +tcg_out_opc_reg (s,OPC_ADD ,TCG_REG_TMP2 ,TCG_REG_TMP2 , addr); + } + } + addr =TCG_REG_TMP2 ; + } + +switch (opc) { +case OPC_SB : +case OPC_SH : +case OPC_SW : +case OPC_SD : +tcg_out_opc_store (s, opc, addr, data, imm12); +break ; +case OPC_LB : +case OPC_LBU : +case OPC_LH : +case OPC_LHU : +case OPC_LW : +case OPC_LWU : +case OPC_LD : +tcg_out_opc_imm (s, opc, data, addr, imm12); +break ; +default : +g_assert_not_reached (); + } +} + +static void tcg_out_ld (TCGContext *s,TCGType type,TCGReg arg, +TCGReg arg1,intptr_t arg2) +{ +bool is32bit = (TCG_TARGET_REG_BITS ==32 || type ==TCG_TYPE_I32 ); +tcg_out_ldst (s, is32bit ?OPC_LW :OPC_LD , arg, arg1, arg2); +} + +static void tcg_out_st (TCGContext *s,TCGType type,TCGReg arg, +TCGReg arg1,intptr_t arg2) +{ +bool is32bit = (TCG_TARGET_REG_BITS ==32 || type ==TCG_TYPE_I32 ); +tcg_out_ldst (s, is32bit ?OPC_SW :OPC_SD , arg, arg1, arg2); +} + +static bool tcg_out_sti (TCGContext *s,TCGType type,TCGArg val, +TCGReg base,intptr_t ofs) +{ +if (val ==0 ) { +tcg_out_st (s, type,TCG_REG_ZERO , base, ofs); +return true; + } +return false; +}
Signature · 1 line
2.19.1
PATCH v2 14/23 riscv: tcg-target: Add the add2 and sub2 instructions
In reply to Alistair Francis--- tcg/riscv/tcg-target.inc.c | 55 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+)
tcg/riscv/tcg-target.inc.c +55 -0
@@ -695,3 +695,58 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, }return false; } + +static void tcg_out_addsub2 (TCGContext *s, +TCGReg rl,TCGReg rh, +TCGReg al,TCGReg ah, +TCGArg bl,TCGArg bh, +bool cbl,bool cbh,bool is_sub,bool is32bit) +{ +const RISCVInsn opc_add = is32bit ?OPC_ADDW :OPC_ADD ; +const RISCVInsn opc_addi = is32bit ?OPC_ADDIW :OPC_ADDI ; +const RISCVInsn opc_sub = is32bit ?OPC_SUBW :OPC_SUB ; +TCGReg th =TCG_REG_TMP1 ; + +/* If we have a negative constant such that negating it would +make the high part zero, we can (usually) eliminate one insn. */ +if (cbl && cbh && bh ==-1 && bl !=0 ) { + bl = -bl; + bh =0 ; + is_sub = !is_sub; + } + +/* By operating on the high part first, we get to use the final +carry operation to move back from the temporary. */ +if (!cbh) { +tcg_out_opc_reg (s, (is_sub ? opc_sub : opc_add), th, ah, bh); + }else if (bh !=0 || ah == rl) { +tcg_out_opc_imm (s, opc_addi, th, ah, (is_sub ? -bh : bh)); + }else { + th = ah; + } + +/* Note that tcg optimization should eliminate the bl == 0 case. */ +if (is_sub) { +if (cbl) { +tcg_out_opc_imm (s,OPC_SLTIU ,TCG_REG_TMP0 , al, bl); +tcg_out_opc_imm (s, opc_addi, rl, al, -bl); + }else { +tcg_out_opc_reg (s,OPC_SLTU ,TCG_REG_TMP0 , al, bl); +tcg_out_opc_reg (s, opc_sub, rl, al, bl); + } +tcg_out_opc_reg (s, opc_sub, rh, th,TCG_REG_TMP0 ); + }else { +if (cbl) { +tcg_out_opc_imm (s, opc_addi, rl, al, bl); +tcg_out_opc_imm (s,OPC_SLTIU ,TCG_REG_TMP0 , rl, bl); + }else if (rl == al && rl == bl) { +tcg_out_opc_imm (s,OPC_SLTI ,TCG_REG_TMP0 , al,0 ); +tcg_out_opc_reg (s, opc_addi, rl, al, bl); + }else { +tcg_out_opc_reg (s, opc_add, rl, al, bl); +tcg_out_opc_reg (s,OPC_SLTU ,TCG_REG_TMP0 , + rl, (rl == bl ? al : bl)); + } +tcg_out_opc_reg (s, opc_add, rh, th,TCG_REG_TMP0 ); + } +}
Signature · 1 line
2.19.1
PATCH v2 15/23 riscv: tcg-target: Add branch and jump instructions
In reply to Alistair Francis--- tcg/riscv/tcg-target.inc.c | 145 +++++++++++++++++++++++++++++++++++++ 1 file changed, 145 insertions(+)
tcg/riscv/tcg-target.inc.c +145 -0
@@ -750,3 +750,148 @@ static void tcg_out_addsub2(TCGContext *s,tcg_out_opc_reg (s, opc_add, rh, th,TCG_REG_TMP0 ); } } + +static const struct { +RISCVInsn op; +bool swap; +} tcg_brcond_to_riscv[] = { + [TCG_COND_EQ ] = {OPC_BEQ , false }, + [TCG_COND_NE ] = {OPC_BNE , false }, + [TCG_COND_LT ] = {OPC_BLT , false }, + [TCG_COND_GE ] = {OPC_BGE , false }, + [TCG_COND_LE ] = {OPC_BGE , true }, + [TCG_COND_GT ] = {OPC_BLT , true }, + [TCG_COND_LTU ] = {OPC_BLTU , false }, + [TCG_COND_GEU ] = {OPC_BGEU , false }, + [TCG_COND_LEU ] = {OPC_BGEU , true }, + [TCG_COND_GTU ] = {OPC_BLTU , true } +}; + +static void tcg_out_brcond (TCGContext *s,TCGCond cond,TCGReg arg1, +TCGReg arg2,TCGLabel *l) +{ +RISCVInsn op = tcg_brcond_to_riscv[cond].op; + +tcg_debug_assert (op !=0 ); + +if (tcg_brcond_to_riscv[cond].swap) { +TCGReg t = arg1; + arg1 = arg2; + arg2 = t; + } + +if (l->has_value) { +intptr_t diff =tcg_pcrel_diff (s, l->u.value_ptr); +if (diff ==sextreg (diff,0 ,12 )) { +tcg_out_opc_branch (s, op, arg1, arg2, diff); + }else { +/* Invert the conditional branch. */ +tcg_out_opc_branch (s, op ^ (1 <<12 ), arg1, arg2,8 ); +tcg_out_opc_jump (s,OPC_JAL ,TCG_REG_ZERO , diff -4 ); + } + }else { +tcg_out_reloc (s, s->code_ptr,R_RISCV_BRANCH , l,0 ); +tcg_out_opc_branch (s, op, arg1, arg2,0 ); +/* NOP to allow patching later */ +tcg_out_opc_imm (s,OPC_ADDI ,TCG_REG_ZERO ,TCG_REG_ZERO ,0 ); + } +} + +static void tcg_out_setcond (TCGContext *s,TCGCond cond,TCGReg ret, +TCGReg arg1,TCGReg arg2) +{ +switch (cond) { +case TCG_COND_EQ : +tcg_out_opc_reg (s,OPC_SUB , ret, arg1, arg2); +tcg_out_opc_imm (s,OPC_SLTIU , ret, ret,1 ); +break ; +case TCG_COND_NE : +tcg_out_opc_reg (s,OPC_SUB , ret, arg1, arg2); +tcg_out_opc_reg (s,OPC_SLTU , ret,TCG_REG_ZERO , ret); +break ; +case TCG_COND_LT : +tcg_out_opc_reg (s,OPC_SLT , ret, arg1, arg2); +break ; +case TCG_COND_GE : +tcg_out_opc_reg (s,OPC_SLT , ret, arg1, arg2); +tcg_out_opc_imm (s,OPC_XORI , ret, ret,1 ); +break ; +case TCG_COND_LE : +tcg_out_opc_reg (s,OPC_SLT , ret, arg2, arg1); +tcg_out_opc_imm (s,OPC_XORI , ret, ret,1 ); +break ; +case TCG_COND_GT : +tcg_out_opc_reg (s,OPC_SLT , ret, arg2, arg1); +break ; +case TCG_COND_LTU : +tcg_out_opc_reg (s,OPC_SLTU , ret, arg1, arg2); +break ; +case TCG_COND_GEU : +tcg_out_opc_reg (s,OPC_SLTU , ret, arg1, arg2); +tcg_out_opc_imm (s,OPC_XORI , ret, ret,1 ); +break ; +case TCG_COND_LEU : +tcg_out_opc_reg (s,OPC_SLTU , ret, arg2, arg1); +tcg_out_opc_imm (s,OPC_XORI , ret, ret,1 ); +break ; +case TCG_COND_GTU : +tcg_out_opc_reg (s,OPC_SLTU , ret, arg2, arg1); +break ; +default : +g_assert_not_reached (); +break ; + } +} + +static void tcg_out_brcond2 (TCGContext *s,TCGCond cond,TCGReg al,TCGReg ah, +TCGReg bl,TCGReg bh,TCGLabel *l) +{ +/* todo */ +g_assert_not_reached (); +} + +static void tcg_out_setcond2 (TCGContext *s,TCGCond cond,TCGReg ret, +TCGReg al,TCGReg ah,TCGReg bl,TCGReg bh) +{ +/* todo */ +g_assert_not_reached (); +} + +static inline void tcg_out_goto (TCGContext *s,tcg_insn_unit *target) +{ +ptrdiff_t offset =tcg_pcrel_diff (s, target); +tcg_debug_assert (offset ==sextreg (offset,1 ,20 ) <<1 ); +tcg_out_opc_jump (s,OPC_JAL ,TCG_REG_ZERO , offset); +} + +static void tcg_out_call_int (TCGContext *s,tcg_insn_unit *arg,bool tail) +{ +TCGReg link = tail ?TCG_REG_ZERO :TCG_REG_RA ; +ptrdiff_t offset =tcg_pcrel_diff (s, arg); +int ret; + +if (offset ==sextreg (offset,1 ,20 ) <<1 ) { +/* short jump: -2097150 to 2097152 */ +tcg_out_opc_jump (s,OPC_JAL , link, offset); + }else if (TCG_TARGET_REG_BITS ==32 || + offset ==sextreg (offset,1 ,31 ) <<1 ) { +/* long jump: -2147483646 to 2147483648 */ +tcg_out_opc_upper (s,OPC_AUIPC ,TCG_REG_TMP0 ,0 ); +tcg_out_opc_imm (s,OPC_JALR , link,TCG_REG_TMP0 ,0 ); + ret =reloc_call (s->code_ptr -2 , arg);\ +tcg_debug_assert (ret == true); + }else if (TCG_TARGET_REG_BITS ==64 ) { +/* far jump: 64-bit */ +tcg_target_long imm =sextreg ((tcg_target_long )arg,0 ,12 ); +tcg_target_long base = (tcg_target_long )arg - imm; +tcg_out_movi (s,TCG_TYPE_PTR ,TCG_REG_TMP0 , base); +tcg_out_opc_imm (s,OPC_JALR , link,TCG_REG_TMP0 , imm); + }else { +g_assert_not_reached (); + } +} + +static void tcg_out_call (TCGContext *s,tcg_insn_unit *arg) +{ +tcg_out_call_int (s, arg, false); +}
Signature · 1 line
2.19.1
PATCH v2 16/23 riscv: tcg-target: Add slowpath load and store instructions
In reply to Alistair Francis--- tcg/riscv/tcg-target.inc.c | 256 +++++++++++++++++++++++++++++++++++++ 1 file changed, 256 insertions(+)
tcg/riscv/tcg-target.inc.c +256 -0
@@ -895,3 +895,259 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) {tcg_out_call_int (s, arg, false); } + +static void tcg_out_mb (TCGContext *s,TCGArg a0) +{ +tcg_insn_unit insn =OPC_FENCE ; + +if (a0 &TCG_MO_LD_LD ) { + insn |=0x02200000 ; + } +if (a0 &TCG_MO_ST_LD ) { + insn |=0x01200000 ; + } +if (a0 &TCG_MO_LD_ST ) { + insn |=0x02100000 ; + } +if (a0 &TCG_MO_ST_ST ) { + insn |=0x02200000 ; + } +tcg_out32 (s, insn); +} + +/* +* Load/store and TLB +*/ + +#if defined(CONFIG_SOFTMMU ) +#include "tcg-ldst.inc.c" + +/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, +* TCGMemOpIdx oi, uintptr_t ra) +*/ +static void *const qemu_ld_helpers[16 ] = { + [MO_UB ] = helper_ret_ldub_mmu, + [MO_SB ] = helper_ret_ldsb_mmu, + [MO_LEUW ] = helper_le_lduw_mmu, + [MO_LESW ] = helper_le_ldsw_mmu, + [MO_LEUL ] = helper_le_ldul_mmu, +#if TCG_TARGET_REG_BITS == 64 + [MO_LESL ] = helper_le_ldsl_mmu, +#endif + [MO_LEQ ] = helper_le_ldq_mmu, + [MO_BEUW ] = helper_be_lduw_mmu, + [MO_BESW ] = helper_be_ldsw_mmu, + [MO_BEUL ] = helper_be_ldul_mmu, +#if TCG_TARGET_REG_BITS == 64 + [MO_BESL ] = helper_be_ldsl_mmu, +#endif + [MO_BEQ ] = helper_be_ldq_mmu, +}; + +/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, +* uintxx_t val, TCGMemOpIdx oi, +* uintptr_t ra) +*/ +static void *const qemu_st_helpers[16 ] = { + [MO_UB ] = helper_ret_stb_mmu, + [MO_LEUW ] = helper_le_stw_mmu, + [MO_LEUL ] = helper_le_stl_mmu, + [MO_LEQ ] = helper_le_stq_mmu, + [MO_BEUW ] = helper_be_stw_mmu, + [MO_BEUL ] = helper_be_stl_mmu, + [MO_BEQ ] = helper_be_stq_mmu, +}; + +static void tcg_out_tlb_load (TCGContext *s,TCGReg addrl, +TCGReg addrh,TCGMemOpIdx oi, +tcg_insn_unit **label_ptr,bool is_load) +{ +TCGMemOp opc =get_memop (oi); +unsigned s_bits = opc &MO_SIZE ; +unsigned a_bits =get_alignment_bits (opc); +target_ulong mask; +int mem_index =get_mmuidx (oi); +int cmp_off + = (is_load + ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) + : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write)); + int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend); +RISCVInsn load_cmp_op = (TARGET_LONG_BITS ==64 ?OPC_LD : +TCG_TARGET_REG_BITS ==64 ?OPC_LWU :OPC_LW ); +RISCVInsn load_add_op =TCG_TARGET_REG_BITS ==64 ?OPC_LD :OPC_LW ; +TCGReg base =TCG_AREG0 ; + +/* We don't support oversize guests */ +if (TCG_TARGET_REG_BITS <TARGET_LONG_BITS ) { +g_assert_not_reached (); + } + +/* We don't support unaligned accesses. */ +if (a_bits < s_bits) { + a_bits = s_bits; + } + mask = (target_ulong )TARGET_PAGE_MASK | ((1 << a_bits) -1 ); + + +/* Compensate for very large offsets. */ +if (add_off >=0x1000 ) { +int adj; + base =TCG_REG_TMP2 ; +if (cmp_off <=2 *0xfff ) { + adj =0xfff ; +tcg_out_opc_imm (s,OPC_ADDI , base,TCG_AREG0 , adj); + }else { + adj = cmp_off -sextreg (cmp_off,0 ,12 ); +tcg_debug_assert (add_off - adj >=-0x1000 + && add_off - adj <0x1000 ); + +tcg_out_opc_upper (s,OPC_LUI , base, adj); +tcg_out_opc_reg (s,OPC_ADD , base, base,TCG_AREG0 ); + } + add_off -= adj; + cmp_off -= adj; + } + +/* Extract the page index. */ +if (CPU_TLB_BITS +CPU_TLB_ENTRY_BITS <12 ) { +tcg_out_opc_imm (s,OPC_SRLI ,TCG_REG_TMP0 , addrl, +TARGET_PAGE_BITS -CPU_TLB_ENTRY_BITS ); +tcg_out_opc_imm (s,OPC_ANDI ,TCG_REG_TMP0 ,TCG_REG_TMP0 , +MAKE_64BIT_MASK (CPU_TLB_ENTRY_BITS ,CPU_TLB_BITS )); + }else if (TARGET_PAGE_BITS >=12 ) { +tcg_out_opc_upper (s,OPC_LUI ,TCG_REG_TMP0 , +MAKE_64BIT_MASK (TARGET_PAGE_BITS ,CPU_TLB_BITS )); +tcg_out_opc_reg (s,OPC_AND ,TCG_REG_TMP0 ,TCG_REG_TMP0 , addrl); +tcg_out_opc_imm (s,OPC_SRLI ,TCG_REG_TMP0 ,TCG_REG_TMP0 , +CPU_TLB_BITS -CPU_TLB_ENTRY_BITS ); + }else { +tcg_out_opc_imm (s,OPC_SRLI ,TCG_REG_TMP0 , addrl,TARGET_PAGE_BITS ); +tcg_out_opc_imm (s,OPC_ANDI ,TCG_REG_TMP0 ,TCG_REG_TMP0 , +MAKE_64BIT_MASK (0 ,CPU_TLB_BITS )); +tcg_out_opc_imm (s,OPC_SLLI ,TCG_REG_TMP0 ,TCG_REG_TMP0 , +CPU_TLB_ENTRY_BITS ); + } + +/* Add that to the base address to index the tlb. */ +tcg_out_opc_reg (s,OPC_ADD ,TCG_REG_TMP2 , base,TCG_REG_TMP0 ); + base =TCG_REG_TMP2 ; + +/* Load the tlb comparator and the addend. */ +tcg_out_ldst (s, load_cmp_op,TCG_REG_TMP0 , base, cmp_off); +tcg_out_ldst (s, load_add_op,TCG_REG_TMP2 , base, add_off); + +/* Clear the non-page, non-alignment bits from the address. */ +if (mask ==sextreg (mask,0 ,12 )) { +tcg_out_opc_imm (s,OPC_ANDI ,TCG_REG_TMP1 , addrl, mask); + }else { +tcg_out_movi (s,TCG_TYPE_REG ,TCG_REG_TMP1 , mask); +tcg_out_opc_reg (s,OPC_AND ,TCG_REG_TMP1 ,TCG_REG_TMP1 , addrl); + } + +/* Compare masked address with the TLB entry. */ + label_ptr[0 ] = s->code_ptr; +tcg_out_opc_branch (s,OPC_BNE ,TCG_REG_TMP0 ,TCG_REG_TMP1 ,0 ); +/* NOP to allow patching later */ +tcg_out_opc_imm (s,OPC_ADDI ,TCG_REG_ZERO ,TCG_REG_ZERO ,0 ); +/* TODO: Move this out of line +* see: +* https://lists.nongnu.org/archive/html/qemu-devel/2018-11/msg02234.html +*/ + +/* TLB Hit - translate address using addend. */ +if (TCG_TARGET_REG_BITS >TARGET_LONG_BITS ) { +tcg_out_ext32u (s,TCG_REG_TMP0 , addrl); + addrl =TCG_REG_TMP0 ; + } +tcg_out_opc_reg (s,OPC_ADD ,TCG_REG_TMP0 ,TCG_REG_TMP2 , addrl); +} + +static void add_qemu_ldst_label (TCGContext *s,int is_ld,TCGMemOpIdx oi, +TCGType ext, +TCGReg datalo,TCGReg datahi, +TCGReg addrlo,TCGReg addrhi, +void *raddr,tcg_insn_unit **label_ptr) +{ +TCGLabelQemuLdst *label =new_ldst_label (s); + + label->is_ld = is_ld; + label->oi = oi; + label->type = ext; + label->datalo_reg = datalo; + label->datahi_reg = datahi; + label->addrlo_reg = addrlo; + label->addrhi_reg = addrhi; + label->raddr = raddr; + label->label_ptr[0 ] = label_ptr[0 ]; +} + +static void tcg_out_qemu_ld_slow_path (TCGContext *s,TCGLabelQemuLdst *l) +{ +TCGMemOpIdx oi = l->oi; +TCGMemOp opc =get_memop (oi); +TCGReg a0 = tcg_target_call_iarg_regs[0 ]; +TCGReg a1 = tcg_target_call_iarg_regs[1 ]; +TCGReg a2 = tcg_target_call_iarg_regs[2 ]; +TCGReg a3 = tcg_target_call_iarg_regs[3 ]; + +/* We don't support oversize guests */ +if (TCG_TARGET_REG_BITS <TARGET_LONG_BITS ) { +g_assert_not_reached (); + } + +/* resolve label address */ +patch_reloc (l->label_ptr[0 ],R_RISCV_BRANCH , (intptr_t ) s->code_ptr,0 ); + +/* call load helper */ +tcg_out_mov (s,TCG_TYPE_PTR , a0,TCG_AREG0 ); +tcg_out_mov (s,TCG_TYPE_PTR , a1, l->addrlo_reg); +tcg_out_movi (s,TCG_TYPE_PTR , a2, oi); +tcg_out_movi (s,TCG_TYPE_PTR , a3, (tcg_target_long )l->raddr); + +tcg_out_call (s, qemu_ld_helpers[opc & (MO_BSWAP |MO_SSIZE )]); +tcg_out_mov (s, (opc &MO_SIZE ) ==MO_64 , l->datalo_reg, a0); + +tcg_out_goto (s, l->raddr); +} + +static void tcg_out_qemu_st_slow_path (TCGContext *s,TCGLabelQemuLdst *l) +{ +TCGMemOpIdx oi = l->oi; +TCGMemOp opc =get_memop (oi); +TCGMemOp s_bits = opc &MO_SIZE ; +TCGReg a0 = tcg_target_call_iarg_regs[0 ]; +TCGReg a1 = tcg_target_call_iarg_regs[1 ]; +TCGReg a2 = tcg_target_call_iarg_regs[2 ]; +TCGReg a3 = tcg_target_call_iarg_regs[3 ]; +TCGReg a4 = tcg_target_call_iarg_regs[4 ]; + +/* We don't support oversize guests */ +if (TCG_TARGET_REG_BITS <TARGET_LONG_BITS ) { +g_assert_not_reached (); + } + +/* resolve label address */ +patch_reloc (l->label_ptr[0 ],R_RISCV_BRANCH , (intptr_t ) s->code_ptr,0 ); + +/* call store helper */ +tcg_out_mov (s,TCG_TYPE_PTR , a0,TCG_AREG0 ); +tcg_out_mov (s,TCG_TYPE_PTR , a1, l->addrlo_reg); +tcg_out_mov (s,TCG_TYPE_PTR , a2, l->datalo_reg); +switch (s_bits) { +case MO_8 : +tcg_out_ext8u (s, a2, a2); +break ; +case MO_16 : +tcg_out_ext16u (s, a2, a2); +break ; +default : +break ; + } +tcg_out_movi (s,TCG_TYPE_PTR , a3, oi); +tcg_out_movi (s,TCG_TYPE_PTR , a4, (tcg_target_long )l->raddr); + +tcg_out_call (s, qemu_st_helpers[opc & (MO_BSWAP |MO_SSIZE )]); + +tcg_out_goto (s, l->raddr); +} +#endif /* CONFIG_SOFTMMU */
Signature · 1 line
2.19.1
PATCH v2 17/23 riscv: tcg-target: Add direct load and store instructions
In reply to Alistair Francis--- tcg/riscv/tcg-target.inc.c | 158 +++++++++++++++++++++++++++++++++++++ 1 file changed, 158 insertions(+)
tcg/riscv/tcg-target.inc.c +158 -0
@@ -1151,3 +1151,161 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)tcg_out_goto (s, l->raddr); }#endif /* CONFIG_SOFTMMU */ + +static void tcg_out_qemu_ld_direct (TCGContext *s,TCGReg lo,TCGReg hi, +TCGReg base,TCGMemOp opc,bool is_64) +{ +const TCGMemOp bswap = opc &MO_BSWAP ; + +/* We don't yet handle byteswapping, assert */ +g_assert (!bswap); + +switch (opc & (MO_SSIZE )) { +case MO_UB : +tcg_out_opc_imm (s,OPC_LBU , lo, base,0 ); +break ; +case MO_SB : +tcg_out_opc_imm (s,OPC_LB , lo, base,0 ); +break ; +case MO_UW : +tcg_out_opc_imm (s,OPC_LHU , lo, base,0 ); +break ; +case MO_SW : +tcg_out_opc_imm (s,OPC_LH , lo, base,0 ); +break ; +case MO_UL : +if (TCG_TARGET_REG_BITS ==64 && is_64) { +tcg_out_opc_imm (s,OPC_LWU , lo, base,0 ); +break ; + } +/* FALLTHRU */ +case MO_SL : +tcg_out_opc_imm (s,OPC_LW , lo, base,0 ); +break ; +case MO_Q : +/* Prefer to load from offset 0 first, but allow for overlap. */ +if (TCG_TARGET_REG_BITS ==64 ) { +tcg_out_opc_imm (s,OPC_LD , lo, base,0 ); + }else if (lo != base) { +tcg_out_opc_imm (s,OPC_LW , lo, base,0 ); +tcg_out_opc_imm (s,OPC_LW , hi, base,4 ); + }else { +tcg_out_opc_imm (s,OPC_LW , hi, base,4 ); +tcg_out_opc_imm (s,OPC_LW , lo, base,0 ); + } +break ; +default : +g_assert_not_reached (); + } +} + +static void tcg_out_qemu_ld (TCGContext *s,const TCGArg *args,bool is_64) +{ + TCGReg addr_regl, addr_regh __attribute__((unused)); +TCGReg data_regl, data_regh; +TCGMemOpIdx oi; +TCGMemOp opc; +#if defined(CONFIG_SOFTMMU ) +tcg_insn_unit *label_ptr[1 ]; +#endif +TCGReg base =TCG_REG_TMP0 ; + + data_regl = *args++; + data_regh = (TCG_TARGET_REG_BITS ==32 && is_64 ? *args++ :0 ); + addr_regl = *args++; + addr_regh = (TCG_TARGET_REG_BITS <TARGET_LONG_BITS ? *args++ :0 ); + oi = *args++; + opc =get_memop (oi); + +#if defined(CONFIG_SOFTMMU ) +tcg_out_tlb_load (s, addr_regl, addr_regh, oi, label_ptr,1 ); +tcg_out_qemu_ld_direct (s, data_regl, data_regh, base, opc, is_64); +add_qemu_ldst_label (s,1 , oi, + (is_64 ?TCG_TYPE_I64 :TCG_TYPE_I32 ), + data_regl, data_regh, addr_regl, addr_regh, + s->code_ptr, label_ptr); +#else +if (TCG_TARGET_REG_BITS >TARGET_LONG_BITS ) { +tcg_out_ext32u (s, base, addr_regl); + addr_regl = base; + } + +if (guest_base ==0 ) { +tcg_out_opc_reg (s,OPC_ADD , base, addr_regl,TCG_REG_ZERO ); + }else { +tcg_out_opc_reg (s,OPC_ADD , base,TCG_GUEST_BASE_REG , addr_regl); + } +tcg_out_qemu_ld_direct (s, data_regl, data_regh, base, opc, is_64); +#endif +} + +static void tcg_out_qemu_st_direct (TCGContext *s,TCGReg lo,TCGReg hi, +TCGReg base,TCGMemOp opc) +{ +const TCGMemOp bswap = opc &MO_BSWAP ; + +/* We don't yet handle byteswapping, assert */ +g_assert (!bswap); + +switch (opc & (MO_SSIZE )) { +case MO_8 : +tcg_out_opc_store (s,OPC_SB , base, lo,0 ); +break ; +case MO_16 : +tcg_out_opc_store (s,OPC_SH , base, lo,0 ); +break ; +case MO_32 : +tcg_out_opc_store (s,OPC_SW , base, lo,0 ); +break ; +case MO_64 : +if (TCG_TARGET_REG_BITS ==64 ) { +tcg_out_opc_store (s,OPC_SD , base, lo,0 ); + }else { +tcg_out_opc_store (s,OPC_SW , base, lo,0 ); +tcg_out_opc_store (s,OPC_SW , base, hi,4 ); + } +break ; +default : +g_assert_not_reached (); + } +} + +static void tcg_out_qemu_st (TCGContext *s,const TCGArg *args,bool is_64) +{ + TCGReg addr_regl, addr_regh __attribute__((unused)); +TCGReg data_regl, data_regh; +TCGMemOpIdx oi; +TCGMemOp opc; +#if defined(CONFIG_SOFTMMU ) +tcg_insn_unit *label_ptr[1 ]; +#endif +TCGReg base =TCG_REG_TMP0 ; + + data_regl = *args++; + data_regh = (TCG_TARGET_REG_BITS ==32 && is_64 ? *args++ :0 ); + addr_regl = *args++; + addr_regh = (TCG_TARGET_REG_BITS <TARGET_LONG_BITS ? *args++ :0 ); + oi = *args++; + opc =get_memop (oi); + +#if defined(CONFIG_SOFTMMU ) +tcg_out_tlb_load (s, addr_regl, addr_regh, oi, label_ptr,0 ); +tcg_out_qemu_st_direct (s, data_regl, data_regh, base, opc); +add_qemu_ldst_label (s,0 , oi, + (is_64 ?TCG_TYPE_I64 :TCG_TYPE_I32 ), + data_regl, data_regh, addr_regl, addr_regh, + s->code_ptr, label_ptr); +#else +if (TCG_TARGET_REG_BITS >TARGET_LONG_BITS ) { +tcg_out_ext32u (s, base, addr_regl); + addr_regl = base; + } + +if (guest_base ==0 ) { +tcg_out_opc_reg (s,OPC_ADD , base, addr_regl,TCG_REG_ZERO ); + }else { +tcg_out_opc_reg (s,OPC_ADD , base,TCG_GUEST_BASE_REG , addr_regl); + } +tcg_out_qemu_st_direct (s, data_regl, data_regh, base, opc); +#endif +}
Signature · 1 line
2.19.1
PATCH v2 18/23 riscv: tcg-target: Add the out op decoder
In reply to Alistair Francis--- tcg/riscv/tcg-target.inc.c | 493 +++++++++++++++++++++++++++++++++++++ 1 file changed, 493 insertions(+)
tcg/riscv/tcg-target.inc.c +493 -0
@@ -1309,3 +1309,496 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)tcg_out_qemu_st_direct (s, data_regl, data_regh, base, opc);#endif } + +static tcg_insn_unit *tb_ret_addr; + +static void tcg_out_op (TCGContext *s,TCGOpcode opc, +const TCGArg *args,const int *const_args) +{ +TCGArg a0 = args[0 ]; +TCGArg a1 = args[1 ]; +TCGArg a2 = args[2 ]; +int c2 = const_args[2 ]; + +switch (opc) { +case INDEX_op_exit_tb: +/* Reuse the zeroing that exists for goto_ptr. */ +if (a0 ==0 ) { +tcg_out_call_int (s, s->code_gen_epilogue, true); + }else { +tcg_out_movi (s,TCG_TYPE_PTR ,TCG_REG_A0 , a0); +tcg_out_call_int (s, tb_ret_addr, true); + } +break ; + +case INDEX_op_goto_tb: +assert (s->tb_jmp_insn_offset ==0 ); +/* indirect jump method */ +tcg_out_ld (s,TCG_TYPE_PTR ,TCG_REG_TMP0 ,TCG_REG_ZERO , + (uintptr_t )(s->tb_jmp_target_addr + a0)); +tcg_out_opc_imm (s,OPC_JALR ,TCG_REG_ZERO ,TCG_REG_TMP0 ,0 ); +set_jmp_reset_offset (s, a0); +break ; + +case INDEX_op_goto_ptr: +tcg_out_opc_imm (s,OPC_JALR ,TCG_REG_ZERO , a0,0 ); +break ; + +case INDEX_op_br: +tcg_out_reloc (s, s->code_ptr,R_RISCV_JAL ,arg_label (a0),0 ); +tcg_out_opc_jump (s,OPC_JAL ,TCG_REG_ZERO ,0 ); +break ; + +case INDEX_op_ld8u_i32: +case INDEX_op_ld8u_i64: +tcg_out_ldst (s,OPC_LBU , a0, a1, a2); +break ; +case INDEX_op_ld8s_i32: +case INDEX_op_ld8s_i64: +tcg_out_ldst (s,OPC_LB , a0, a1, a2); +break ; +case INDEX_op_ld16u_i32: +case INDEX_op_ld16u_i64: +tcg_out_ldst (s,OPC_LHU , a0, a1, a2); +break ; +case INDEX_op_ld16s_i32: +case INDEX_op_ld16s_i64: +tcg_out_ldst (s,OPC_LH , a0, a1, a2); +break ; +case INDEX_op_ld32u_i64: +tcg_out_ldst (s,OPC_LWU , a0, a1, a2); +break ; +case INDEX_op_ld_i32: +case INDEX_op_ld32s_i64: +tcg_out_ldst (s,OPC_LW , a0, a1, a2); +break ; +case INDEX_op_ld_i64: +tcg_out_ldst (s,OPC_LD , a0, a1, a2); +break ; + +case INDEX_op_st8_i32: +case INDEX_op_st8_i64: +tcg_out_ldst (s,OPC_SB , a0, a1, a2); +break ; +case INDEX_op_st16_i32: +case INDEX_op_st16_i64: +tcg_out_ldst (s,OPC_SH , a0, a1, a2); +break ; +case INDEX_op_st_i32: +case INDEX_op_st32_i64: +tcg_out_ldst (s,OPC_SW , a0, a1, a2); +break ; +case INDEX_op_st_i64: +tcg_out_ldst (s,OPC_SD , a0, a1, a2); +break ; + +case INDEX_op_add_i32: +if (c2) { +tcg_out_opc_imm (s,OPC_ADDIW , a0, a1, a2); + }else { +tcg_out_opc_reg (s,OPC_ADDW , a0, a1, a2); + } +break ; +case INDEX_op_add_i64: +if (c2) { +tcg_out_opc_imm (s,OPC_ADDI , a0, a1, a2); + }else { +tcg_out_opc_reg (s,OPC_ADD , a0, a1, a2); + } +break ; + +case INDEX_op_sub_i32: +if (c2) { +tcg_out_opc_imm (s,OPC_ADDIW , a0, a1, -a2); + }else { +tcg_out_opc_reg (s,OPC_SUBW , a0, a1, a2); + } +break ; +case INDEX_op_sub_i64: +if (c2) { +tcg_out_opc_imm (s,OPC_ADDI , a0, a1, -a2); + }else { +tcg_out_opc_reg (s,OPC_SUB , a0, a1, a2); + } +break ; + +case INDEX_op_and_i32: +case INDEX_op_and_i64: +if (c2) { +tcg_out_opc_imm (s,OPC_ANDI , a0, a1, a2); + }else { +tcg_out_opc_reg (s,OPC_AND , a0, a1, a2); + } +break ; + +case INDEX_op_or_i32: +case INDEX_op_or_i64: +if (c2) { +tcg_out_opc_imm (s,OPC_ORI , a0, a1, a2); + }else { +tcg_out_opc_reg (s,OPC_OR , a0, a1, a2); + } +break ; + +case INDEX_op_xor_i32: +case INDEX_op_xor_i64: +if (c2) { +tcg_out_opc_imm (s,OPC_XORI , a0, a1, a2); + }else { +tcg_out_opc_reg (s,OPC_XOR , a0, a1, a2); + } +break ; + +case INDEX_op_not_i32: +case INDEX_op_not_i64: +tcg_out_opc_imm (s,OPC_XORI , a0, a1,-1 ); +break ; + +case INDEX_op_neg_i32: +tcg_out_opc_reg (s,OPC_SUBW , a0,TCG_REG_ZERO , a1); +break ; +case INDEX_op_neg_i64: +tcg_out_opc_reg (s,OPC_SUB , a0,TCG_REG_ZERO , a1); +break ; + +case INDEX_op_mul_i32: +tcg_out_opc_reg (s,OPC_MULW , a0, a1, a2); +break ; +case INDEX_op_mul_i64: +tcg_out_opc_reg (s,OPC_MUL , a0, a1, a2); +break ; + +case INDEX_op_div_i32: +tcg_out_opc_reg (s,OPC_DIVW , a0, a1, a2); +break ; +case INDEX_op_div_i64: +tcg_out_opc_reg (s,OPC_DIV , a0, a1, a2); +break ; + +case INDEX_op_divu_i32: +tcg_out_opc_reg (s,OPC_DIVUW , a0, a1, a2); +break ; +case INDEX_op_divu_i64: +tcg_out_opc_reg (s,OPC_DIVU , a0, a1, a2); +break ; + +case INDEX_op_rem_i32: +tcg_out_opc_reg (s,OPC_REMW , a0, a1, a2); +break ; +case INDEX_op_rem_i64: +tcg_out_opc_reg (s,OPC_REM , a0, a1, a2); +break ; + +case INDEX_op_remu_i32: +tcg_out_opc_reg (s,OPC_REMUW , a0, a1, a2); +break ; +case INDEX_op_remu_i64: +tcg_out_opc_reg (s,OPC_REMU , a0, a1, a2); +break ; + +case INDEX_op_shl_i32: +if (c2) { +tcg_out_opc_imm (s,OPC_SLLIW , a0, a1, a2); + }else { +tcg_out_opc_reg (s,OPC_SLLW , a0, a1, a2); + } +break ; +case INDEX_op_shl_i64: +if (c2) { +tcg_out_opc_imm (s,OPC_SLLI , a0, a1, a2); + }else { +tcg_out_opc_reg (s,OPC_SLL , a0, a1, a2); + } +break ; + +case INDEX_op_shr_i32: +if (c2) { +tcg_out_opc_imm (s,OPC_SRLIW , a0, a1, a2); + }else { +tcg_out_opc_reg (s,OPC_SRLW , a0, a1, a2); + } +break ; +case INDEX_op_shr_i64: +if (c2) { +tcg_out_opc_imm (s,OPC_SRLI , a0, a1, a2); + }else { +tcg_out_opc_reg (s,OPC_SRL , a0, a1, a2); + } +break ; + +case INDEX_op_sar_i32: +if (c2) { +tcg_out_opc_imm (s,OPC_SRAIW , a0, a1, a2); + }else { +tcg_out_opc_reg (s,OPC_SRAW , a0, a1, a2); + } +break ; +case INDEX_op_sar_i64: +if (c2) { +tcg_out_opc_imm (s,OPC_SRAI , a0, a1, a2); + }else { +tcg_out_opc_reg (s,OPC_SRA , a0, a1, a2); + } +break ; + +case INDEX_op_add2_i32: +tcg_out_addsub2 (s, a0, a1, a2, args[3 ], args[4 ], args[5 ], + const_args[4 ], const_args[5 ], false, true); +break ; +case INDEX_op_add2_i64: +tcg_out_addsub2 (s, a0, a1, a2, args[3 ], args[4 ], args[5 ], + const_args[4 ], const_args[5 ], false, false); +break ; +case INDEX_op_sub2_i32: +tcg_out_addsub2 (s, a0, a1, a2, args[3 ], args[4 ], args[5 ], + const_args[4 ], const_args[5 ], true, true); +break ; +case INDEX_op_sub2_i64: +tcg_out_addsub2 (s, a0, a1, a2, args[3 ], args[4 ], args[5 ], + const_args[4 ], const_args[5 ], true, false); +break ; + +case INDEX_op_brcond_i32: +case INDEX_op_brcond_i64: +tcg_out_brcond (s, a2, a0, a1,arg_label (args[3 ])); +break ; +case INDEX_op_brcond2_i32: +tcg_out_brcond2 (s, args[4 ], a0, a1, a2, args[3 ],arg_label (args[5 ])); +break ; + +case INDEX_op_setcond_i32: +case INDEX_op_setcond_i64: +tcg_out_setcond (s, args[3 ], a0, a1, a2); +break ; +case INDEX_op_setcond2_i32: +tcg_out_setcond2 (s, args[5 ], a0, a1, a2, args[3 ], args[4 ]); +break ; + +case INDEX_op_qemu_ld_i32: +tcg_out_qemu_ld (s, args, false); +break ; +case INDEX_op_qemu_ld_i64: +tcg_out_qemu_ld (s, args, true); +break ; +case INDEX_op_qemu_st_i32: +tcg_out_qemu_st (s, args, false); +break ; +case INDEX_op_qemu_st_i64: +tcg_out_qemu_st (s, args, true); +break ; + +case INDEX_op_ext8u_i32: +case INDEX_op_ext8u_i64: +tcg_out_ext8u (s, a0, a1); +break ; + +case INDEX_op_ext16u_i32: +case INDEX_op_ext16u_i64: +tcg_out_ext16u (s, a0, a1); +break ; + +case INDEX_op_ext32u_i64: +case INDEX_op_extu_i32_i64: +tcg_out_ext32u (s, a0, a1); +break ; + +case INDEX_op_ext8s_i32: +case INDEX_op_ext8s_i64: +tcg_out_ext8s (s, a0, a1); +break ; + +case INDEX_op_ext16s_i32: +case INDEX_op_ext16s_i64: +tcg_out_ext16s (s, a0, a1); +break ; + +case INDEX_op_ext32s_i64: +case INDEX_op_extrl_i64_i32: +case INDEX_op_extrh_i64_i32: +case INDEX_op_ext_i32_i64: +tcg_out_ext32s (s, a0, a1); +break ; + +case INDEX_op_mulsh_i32: +case INDEX_op_mulsh_i64: +tcg_out_opc_reg (s,OPC_MULH , a0, a1, a2); +break ; + +case INDEX_op_muluh_i32: +case INDEX_op_muluh_i64: +tcg_out_opc_reg (s,OPC_MULHU , a0, a1, a2); +break ; + +case INDEX_op_mb: +tcg_out_mb (s, a0); +break ; + +case INDEX_op_mov_i32:/* Always emitted via tcg_out_mov. */ +case INDEX_op_mov_i64: +case INDEX_op_movi_i32:/* Always emitted via tcg_out_movi. */ +case INDEX_op_movi_i64: +case INDEX_op_call:/* Always emitted via tcg_out_call. */ +default : +g_assert_not_reached (); + } +} + +static const TCGTargetOpDef *tcg_target_op_def (TCGOpcode op) +{ +static const TCGTargetOpDef r + = { .args_ct_str = {"r" } }; +static const TCGTargetOpDef r_r + = { .args_ct_str = {"r" ,"r" } }; +static const TCGTargetOpDef rZ_r + = { .args_ct_str = {"rZ" ,"r" } }; +static const TCGTargetOpDef rZ_rZ + = { .args_ct_str = {"rZ" ,"rZ" } }; +static const TCGTargetOpDef rZ_rZ_rZ_rZ + = { .args_ct_str = {"rZ" ,"rZ" ,"rZ" ,"rZ" } }; +static const TCGTargetOpDef r_r_ri + = { .args_ct_str = {"r" ,"r" ,"ri" } }; +static const TCGTargetOpDef r_r_rI + = { .args_ct_str = {"r" ,"r" ,"rI" } }; +static const TCGTargetOpDef r_rZ_rN + = { .args_ct_str = {"r" ,"rZ" ,"rN" } }; +static const TCGTargetOpDef r_rZ_rZ + = { .args_ct_str = {"r" ,"rZ" ,"rZ" } }; +static const TCGTargetOpDef r_rZ_rZ_rZ_rZ + = { .args_ct_str = {"r" ,"rZ" ,"rZ" ,"rZ" ,"rZ" } }; +static const TCGTargetOpDef r_L + = { .args_ct_str = {"r" ,"L" } }; +static const TCGTargetOpDef r_r_L + = { .args_ct_str = {"r" ,"r" ,"L" } }; +static const TCGTargetOpDef r_L_L + = { .args_ct_str = {"r" ,"L" ,"L" } }; +static const TCGTargetOpDef r_r_L_L + = { .args_ct_str = {"r" ,"r" ,"L" ,"L" } }; +static const TCGTargetOpDef LZ_L + = { .args_ct_str = {"LZ" ,"L" } }; +static const TCGTargetOpDef LZ_L_L + = { .args_ct_str = {"LZ" ,"L" ,"L" } }; +static const TCGTargetOpDef LZ_LZ_L + = { .args_ct_str = {"LZ" ,"LZ" ,"L" } }; +static const TCGTargetOpDef LZ_LZ_L_L + = { .args_ct_str = {"LZ" ,"LZ" ,"L" ,"L" } }; +static const TCGTargetOpDef r_r_rZ_rZ_rM_rM + = { .args_ct_str = {"r" ,"r" ,"rZ" ,"rZ" ,"rM" ,"rM" } }; + +switch (op) { +case INDEX_op_goto_ptr: +return &r; + +case INDEX_op_ld8u_i32: +case INDEX_op_ld8s_i32: +case INDEX_op_ld16u_i32: +case INDEX_op_ld16s_i32: +case INDEX_op_ld_i32: +case INDEX_op_not_i32: +case INDEX_op_neg_i32: +case INDEX_op_ld8u_i64: +case INDEX_op_ld8s_i64: +case INDEX_op_ld16u_i64: +case INDEX_op_ld16s_i64: +case INDEX_op_ld32s_i64: +case INDEX_op_ld32u_i64: +case INDEX_op_ld_i64: +case INDEX_op_not_i64: +case INDEX_op_neg_i64: +case INDEX_op_ext8u_i32: +case INDEX_op_ext8u_i64: +case INDEX_op_ext16u_i32: +case INDEX_op_ext16u_i64: +case INDEX_op_ext32u_i64: +case INDEX_op_extu_i32_i64: +case INDEX_op_ext8s_i32: +case INDEX_op_ext8s_i64: +case INDEX_op_ext16s_i32: +case INDEX_op_ext16s_i64: +case INDEX_op_ext32s_i64: +case INDEX_op_extrl_i64_i32: +case INDEX_op_extrh_i64_i32: +case INDEX_op_ext_i32_i64: +return &r_r; + +case INDEX_op_st8_i32: +case INDEX_op_st16_i32: +case INDEX_op_st_i32: +case INDEX_op_st8_i64: +case INDEX_op_st16_i64: +case INDEX_op_st32_i64: +case INDEX_op_st_i64: +return &rZ_r; + +case INDEX_op_add_i32: +case INDEX_op_and_i32: +case INDEX_op_or_i32: +case INDEX_op_xor_i32: +case INDEX_op_add_i64: +case INDEX_op_and_i64: +case INDEX_op_or_i64: +case INDEX_op_xor_i64: +return &r_r_rI; + +case INDEX_op_sub_i32: +case INDEX_op_sub_i64: +return &r_rZ_rN; + +case INDEX_op_mul_i32: +case INDEX_op_mulsh_i32: +case INDEX_op_muluh_i32: +case INDEX_op_div_i32: +case INDEX_op_divu_i32: +case INDEX_op_rem_i32: +case INDEX_op_remu_i32: +case INDEX_op_setcond_i32: +case INDEX_op_mul_i64: +case INDEX_op_mulsh_i64: +case INDEX_op_muluh_i64: +case INDEX_op_div_i64: +case INDEX_op_divu_i64: +case INDEX_op_rem_i64: +case INDEX_op_remu_i64: +case INDEX_op_setcond_i64: +return &r_rZ_rZ; + +case INDEX_op_shl_i32: +case INDEX_op_shr_i32: +case INDEX_op_sar_i32: +case INDEX_op_shl_i64: +case INDEX_op_shr_i64: +case INDEX_op_sar_i64: +return &r_r_ri; + +case INDEX_op_brcond_i32: +case INDEX_op_brcond_i64: +return &rZ_rZ; + +case INDEX_op_add2_i32: +case INDEX_op_add2_i64: +case INDEX_op_sub2_i32: +case INDEX_op_sub2_i64: +return &r_r_rZ_rZ_rM_rM; + +case INDEX_op_brcond2_i32: +return &rZ_rZ_rZ_rZ; + +case INDEX_op_setcond2_i32: +return &r_rZ_rZ_rZ_rZ; + +case INDEX_op_qemu_ld_i32: +return TARGET_LONG_BITS <=TCG_TARGET_REG_BITS ? &r_L : &r_L_L; +case INDEX_op_qemu_st_i32: +return TARGET_LONG_BITS <=TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L ; +case INDEX_op_qemu_ld_i64: +return TCG_TARGET_REG_BITS ==64 ? &r_L + :TARGET_LONG_BITS <=TCG_TARGET_REG_BITS ? &r_r_L + : &r_r_L_L; +case INDEX_op_qemu_st_i64: +return TCG_TARGET_REG_BITS ==64 ? &LZ_L + :TARGET_LONG_BITS <=TCG_TARGET_REG_BITS ? &LZ_LZ_L + : &LZ_LZ_L_L ; + +default : +return NULL ; + } +}
Signature · 1 line
2.19.1
Re: [Qemu-devel] [PATCH v2 18/23] riscv: tcg-target: Add the out op decoder
Review
Quoted 6 lines · Alistair Francis
(quoted diff) +6
-0+ case INDEX_op_ext32s_i64: + case INDEX_op_extrl_i64_i32: + case INDEX_op_extrh_i64_i32: + case INDEX_op_ext_i32_i64: + tcg_out_ext32s(s, a0, a1); + break;
This is the last bug that's easy to identify. It shows up quickly in a linux-user smoke test [1]. Obviously extrl (extract low) and extrh (extract high) should not be implemented identically.
Fixed thus.
With this, most of the tests pass, when run in a qemu-riscv chroot. The ones that don't primarily never get started. E.g. the alpha test fails to map ld.so, for reasons that I have not examined, since it's not a tcg problem.
r~
[1] https://archive.li/o/1YduE/wiki.qemu.org/download/linux-user-test-0.3.tar.gz
--- tcg/riscv/tcg-target.inc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
tcg/riscv/tcg-target.inc.c +4 -1
@@ -1614,11 +1614,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,case INDEX_op_ext32s_i64:case INDEX_op_extrl_i64_i32: -case INDEX_op_extrh_i64_i32:case INDEX_op_ext_i32_i64:tcg_out_ext32s (s, a0, a1);break ; +case INDEX_op_extrh_i64_i32: +tcg_out_opc_imm (s,OPC_SRAI , a0, a1,32 ); +break ; +case INDEX_op_mulsh_i32:case INDEX_op_mulsh_i64:tcg_out_opc_reg (s,OPC_MULH , a0, a1, a2);
---
PATCH v2 19/23 riscv: tcg-target: Add the prologue generation and register the JIT
In reply to Alistair Francis--- tcg/riscv/tcg-target.inc.c | 111 +++++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+)
tcg/riscv/tcg-target.inc.c +111 -0
@@ -1802,3 +1802,114 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)return NULL ; } } + +static const int tcg_target_callee_save_regs[] = { +TCG_REG_S0 ,/* used for the global env (TCG_AREG0) */ +TCG_REG_S1 , +TCG_REG_S2 , +TCG_REG_S3 , +TCG_REG_S4 , +TCG_REG_S5 , +TCG_REG_S6 , +TCG_REG_S7 , +TCG_REG_S8 , +TCG_REG_S9 , +TCG_REG_S10 , +TCG_REG_S11 , +TCG_REG_RA ,/* should be last for ABI compliance */ +}; + +/* Stack frame parameters. */ +#define REG_SIZE (TCG_TARGET_REG_BITS / 8) +#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) +#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) +#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ + + TCG_TARGET_STACK_ALIGN - 1) \ + & -TCG_TARGET_STACK_ALIGN) +#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) + +/* We're expecting to be able to use an immediate for frame allocation. */ +QEMU_BUILD_BUG_ON (FRAME_SIZE >0x7ff ); + +/* Generate global QEMU prologue and epilogue code */ +static void tcg_target_qemu_prologue (TCGContext *s) +{ +int i; + +tcg_set_frame (s,TCG_REG_SP ,TCG_STATIC_CALL_ARGS_SIZE ,TEMP_SIZE ); + +/* TB prologue */ +tcg_out_opc_imm (s,OPC_ADDI ,TCG_REG_SP ,TCG_REG_SP , -FRAME_SIZE ); +for (i =0 ; i <ARRAY_SIZE (tcg_target_callee_save_regs); i++) { +tcg_out_st (s,TCG_TYPE_REG , tcg_target_callee_save_regs[i], +TCG_REG_SP ,SAVE_OFS + i *REG_SIZE ); + } + +#if !defined(CONFIG_SOFTMMU ) +tcg_out_movi (s,TCG_TYPE_PTR ,TCG_GUEST_BASE_REG , guest_base); +tcg_regset_set_reg (s->reserved_regs,TCG_GUEST_BASE_REG ); +#endif + +/* Call generated code */ +tcg_out_mov (s,TCG_TYPE_PTR ,TCG_AREG0 , tcg_target_call_iarg_regs[0 ]); +tcg_out_opc_imm (s,OPC_JALR ,TCG_REG_ZERO , tcg_target_call_iarg_regs[1 ],0 ); + +/* Return path for goto_ptr. Set return value to 0 */ + s->code_gen_epilogue = s->code_ptr; +tcg_out_mov (s,TCG_TYPE_REG ,TCG_REG_A0 ,TCG_REG_ZERO ); + +/* TB epilogue */ + tb_ret_addr = s->code_ptr; +for (i =0 ; i <ARRAY_SIZE (tcg_target_callee_save_regs); i++) { +tcg_out_ld (s,TCG_TYPE_REG , tcg_target_callee_save_regs[i], +TCG_REG_SP ,SAVE_OFS + i *REG_SIZE ); + } + +tcg_out_opc_imm (s,OPC_ADDI ,TCG_REG_SP ,TCG_REG_SP ,FRAME_SIZE ); +tcg_out_opc_imm (s,OPC_JALR ,TCG_REG_ZERO ,TCG_REG_RA ,0 ); +} + +typedef struct { +DebugFrameHeader h; +uint8_t fde_def_cfa[4 ]; +uint8_t fde_reg_ofs[ARRAY_SIZE (tcg_target_callee_save_regs) *2 ]; +}DebugFrame ; + +#define ELF_HOST_MACHINE EM_RISCV + +static const DebugFrame debug_frame = { + .h.cie.len =sizeof (DebugFrameCIE) -4 ,/* length after .len member */ + .h.cie.id =-1 , + .h.cie.version =1 , + .h.cie.code_align =1 , + .h.cie.data_align = -(TCG_TARGET_REG_BITS /8 ) &0x7f ,/* sleb128 */ + .h.cie.return_column =TCG_REG_RA , + +/* Total FDE size does not include the "len" member. */ + .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), + + .fde_def_cfa = { +12 ,TCG_REG_SP ,/* DW_CFA_def_cfa sp, ... */ + (FRAME_SIZE &0x7f ) |0x80 ,/* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >>7 ) + }, + .fde_reg_ofs = { +0x80 +9 ,12 ,/* DW_CFA_offset, s1, -96 */ +0x80 +18 ,11 ,/* DW_CFA_offset, s2, -88 */ +0x80 +19 ,10 ,/* DW_CFA_offset, s3, -80 */ +0x80 +20 ,9 ,/* DW_CFA_offset, s4, -72 */ +0x80 +21 ,8 ,/* DW_CFA_offset, s5, -64 */ +0x80 +22 ,7 ,/* DW_CFA_offset, s6, -56 */ +0x80 +23 ,6 ,/* DW_CFA_offset, s7, -48 */ +0x80 +24 ,5 ,/* DW_CFA_offset, s8, -40 */ +0x80 +25 ,4 ,/* DW_CFA_offset, s9, -32 */ +0x80 +26 ,3 ,/* DW_CFA_offset, s10, -24 */ +0x80 +27 ,2 ,/* DW_CFA_offset, s11, -16 */ +0x80 +1 ,1 ,/* DW_CFA_offset, ra, -8 */ + } +}; + +void tcg_register_jit (void *buf,size_t buf_size) +{ +tcg_register_jit_int (buf, buf_size, &debug_frame,sizeof (debug_frame)); +}
Signature · 1 line
2.19.1
PATCH v2 20/23 riscv: tcg-target: Add the target init code
In reply to Alistair Francis--- tcg/riscv/tcg-target.inc.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)
tcg/riscv/tcg-target.inc.c +31 -0
@@ -1869,6 +1869,37 @@ static void tcg_target_qemu_prologue(TCGContext *s)tcg_out_opc_imm (s,OPC_JALR ,TCG_REG_ZERO ,TCG_REG_RA ,0 ); } +static void tcg_target_init (TCGContext *s) +{ + tcg_target_available_regs[TCG_TYPE_I32 ] =0xffffffff ; +if (TCG_TARGET_REG_BITS ==64 ) { + tcg_target_available_regs[TCG_TYPE_I64 ] =0xffffffff ; + } + + tcg_target_call_clobber_regs =-1u ; +tcg_regset_reset_reg (tcg_target_call_clobber_regs,TCG_REG_S0 ); +tcg_regset_reset_reg (tcg_target_call_clobber_regs,TCG_REG_S1 ); +tcg_regset_reset_reg (tcg_target_call_clobber_regs,TCG_REG_S2 ); +tcg_regset_reset_reg (tcg_target_call_clobber_regs,TCG_REG_S3 ); +tcg_regset_reset_reg (tcg_target_call_clobber_regs,TCG_REG_S4 ); +tcg_regset_reset_reg (tcg_target_call_clobber_regs,TCG_REG_S5 ); +tcg_regset_reset_reg (tcg_target_call_clobber_regs,TCG_REG_S6 ); +tcg_regset_reset_reg (tcg_target_call_clobber_regs,TCG_REG_S7 ); +tcg_regset_reset_reg (tcg_target_call_clobber_regs,TCG_REG_S8 ); +tcg_regset_reset_reg (tcg_target_call_clobber_regs,TCG_REG_S9 ); +tcg_regset_reset_reg (tcg_target_call_clobber_regs,TCG_REG_S10 ); +tcg_regset_reset_reg (tcg_target_call_clobber_regs,TCG_REG_S11 ); + + s->reserved_regs =0 ; +tcg_regset_set_reg (s->reserved_regs,TCG_REG_ZERO ); +tcg_regset_set_reg (s->reserved_regs,TCG_REG_TMP0 ); +tcg_regset_set_reg (s->reserved_regs,TCG_REG_TMP1 ); +tcg_regset_set_reg (s->reserved_regs,TCG_REG_TMP2 ); +tcg_regset_set_reg (s->reserved_regs,TCG_REG_SP ); +tcg_regset_set_reg (s->reserved_regs,TCG_REG_GP ); +tcg_regset_set_reg (s->reserved_regs,TCG_REG_TP ); +} + typedef struct { DebugFrameHeader h; uint8_t fde_def_cfa[4];
Signature · 1 line
2.19.1
PATCH v2 21/23 tcg: Add RISC-V cpu signal handler
In reply to Alistair Francis--- accel/tcg/user-exec.c | 75 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+)
accel/tcg/user-exec.c +75 -0
@@ -571,6 +571,81 @@ int cpu_signal_handler(int host_signum, void *pinfo,return handle_cpu_signal (pc, info, is_write, &uc->uc_sigmask); } +#elif defined(__riscv) + +int cpu_signal_handler (int host_signum,void *pinfo, +void *puc) +{ +siginfo_t *info = pinfo; +ucontext_t *uc = puc; +greg_t pc = uc->uc_mcontext.__gregs[REG_PC ]; +uint32_t insn = *(uint32_t *)pc; +int is_write =0 ; + +/* Detect store by reading the instruction at the program +counter. Note: we currently only generate 32-bit +instructions so we thus only detect 32-bit stores */ +switch (((insn >>0 ) &0b11 )) { +case 3 : +switch (((insn >>2 ) &0b11111 )) { +case 8 : +switch (((insn >>12 ) &0b111 )) { +case 0 :/* sb */ +case 1 :/* sh */ +case 2 :/* sw */ +case 3 :/* sd */ +case 4 :/* sq */ + is_write =1 ; +break ; +default : +break ; + } +break ; +case 9 : +switch (((insn >>12 ) &0b111 )) { +case 2 :/* fsw */ +case 3 :/* fsd */ +case 4 :/* fsq */ + is_write =1 ; +break ; +default : +break ; + } +break ; +default : +break ; + } + } + +/* Check for compressed instructions */ +switch (((insn >>13 ) &0b111 )) { +case 7 : +switch (insn &0b11 ) { +case 0 :/*c.sd */ +case 2 :/* c.sdsp */ + is_write =1 ; +break ; +default : +break ; + } +break ; +case 6 : +switch (insn &0b11 ) { +case 0 :/* c.sw */ +case 3 :/* c.swsp */ + is_write =1 ; +break ; +default : +break ; + } +break ; +default : +break ; + } + +return handle_cpu_signal (pc, info, is_write, &uc->uc_sigmask); +} +#else #error host CPU specific signal handler needed
Signature · 1 line
2.19.1
PATCH v2 22/23 dias: Add RISC-V support
In reply to Alistair Francis--- disas.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
disas.c +8 -2
@@ -522,8 +522,14 @@ void disas(FILE *out, void *code, unsigned long size)# ifdef _ARCH_PPC64 s.info.cap_mode =CS_MODE_64 ;# endif -#elif defined(__riscv__) - print_insn = print_insn_riscv; +#elif defined(__riscv) && defined(CONFIG_RISCV_DIS ) +#if defined(_ILP32) || (__riscv_xlen ==32 ) + print_insn = print_insn_riscv32; +#elif defined(_LP64) + print_insn = print_insn_riscv64; +#else +#error unsupported RISC-V ABI +#endif #elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS ) print_insn = print_insn_arm_a64; s.info.cap_arch =CS_ARCH_ARM64 ;
Signature · 1 line
2.19.1
PATCH v2 23/23 configure: Add support for building RISC-V host
In reply to Alistair Francis--- configure | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)
configure +10 -2
@@ -710,6 +710,12 @@ elif check_define __s390__ ; then else cpu="s390" fi +elif check_define __riscv ; then + if check_define _LP64 ; then + cpu="riscv64" + else + cpu="riscv32" + fi elif check_define __arm__ ; then cpu="arm" elif check_define __aarch64__ ; then
@@ -722,7 +728,7 @@ ARCH= # Normalise host CPU name and set ARCH. # Note that this case should only have supported host CPUs, not guests. case "$cpu" in - ppc|ppc64|s390|s390x|sparc64|x32) + ppc|ppc64|s390|s390x|sparc64|x32|riscv32|riscv64) cpu="$cpu" supported_cpu="yes" eval "cross_cc_${cpu}=\$host_cc"
@@ -6937,6 +6943,8 @@ elif test "$ARCH" = "x86_64" -o "$ARCH" = "x32" ; then QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/i386 $QEMU_INCLUDES" elif test "$ARCH" = "ppc64" ; then QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/ppc $QEMU_INCLUDES" +elif test "$ARCH" = "riscv32" -o "$ARCH" = "riscv64" ; then + QEMU_INCLUDES="-I\$(SRC_PATH)/tcg/riscv $QEMU_INCLUDES" else QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/\$(ARCH) $QEMU_INCLUDES" fi
@@ -7433,7 +7441,7 @@ for i in $ARCH $TARGET_BASE_ARCH ; do ppc*) disas_config "PPC" ;; - riscv) + riscv*) disas_config "RISCV" ;; s390*)
Signature · 1 line
2.19.1
Richard Henderson
AppliedQuoted 8 lines · Alistair Francis
This patch set adds RISC-V backend support to QEMU. This is based on Michael Clark's original work with extra work on top.
This has been somewhat tested and can run other architecture softmmu code. It seems that any complex OS will eventually hang, but we can run the BIOS and OS startup code for a number of different operating systems.
Quoted 6 lines
I haven't tested linux user support at all yet. I think Michael had that working reliably though and hopefully my changes haven't broken it.
There are still some todos in the code (there are missing instructions and byte swapping) but these should assert instead of generating invalid code.
Queued to tcg-next, with the extrh fix.
Some of those todos are no longer todos, since e.g. bswap is now optional. Those asserts should never fire (as a good assert should do, I suppose).
The missing instructions are only for riscv32, which afaik is just now making its way to glibc. So a chroot complete enough to build qemu is a ways away. I'm ok with leaving that incomplete for now.
r~
Quoted 10 lines · Richard Henderson
Quoted 8 lines · Alistair Francis
This patch set adds RISC-V backend support to QEMU. This is based on Michael Clark's original work with extra work on top.
This has been somewhat tested and can run other architecture softmmu code. It seems that any complex OS will eventually hang, but we can run the BIOS and OS startup code for a number of different operating systems.
Quoted 8 lines
Quoted 6 lines
I haven't tested linux user support at all yet. I think Michael had that working reliably though and hopefully my changes haven't broken it.
There are still some todos in the code (there are missing instructions and byte swapping) but these should assert instead of generating invalid code.
Queued to tcg-next, with the extrh fix.
Thanks Richard!
Quoted 10 lines
Some of those todos are no longer todos, since e.g. bswap is now optional. Those asserts should never fire (as a good assert should do, I suppose).
The missing instructions are only for riscv32, which afaik is just now making its way to glibc. So a chroot complete enough to build qemu is a ways away. I'm ok with leaving that incomplete for now.
r~
Quoted 15 lines · On Thu, 20 Dec 2018 09:20:05 PST (-0800), [email protected] wrote:
Quoted 13 lines · Richard Henderson
Quoted 11 lines · Alistair Francis
This patch set adds RISC-V backend support to QEMU. This is based on Michael Clark's original work with extra work on top.
This has been somewhat tested and can run other architecture softmmu code. It seems that any complex OS will eventually hang, but we can run the BIOS and OS startup code for a number of different operating systems.
I haven't tested linux user support at all yet. I think Michael had that working reliably though and hopefully my changes haven't broken it.
Quoted 7 lines
Quoted 5 lines
Quoted 3 lines
There are still some todos in the code (there are missing instructions and byte swapping) but these should assert instead of generating invalid code.
Queued to tcg-next, with the extrh fix.
Thanks Richard!
Sounds good to me. I'm still attempting to collect the RISC-V patches to get a PR out, a few things came up but I should have time now. This was the biggest patch set, so it should be a lot easier now.
Thanks for picking this up!
Quoted 6 lines
Quoted 6 lines
Some of those todos are no longer todos, since e.g. bswap is now optional. Those asserts should never fire (as a good assert should do, I suppose).
The missing instructions are only for riscv32, which afaik is just now making its way to glibc. So a chroot complete enough to build qemu is a ways away. I'm ok with leaving that incomplete for now.
We've decided to delay the rv32i glibc port until after the next glibc release, which is targeted for the beginning of February. glibc should freeze at the end of the year, at which point we're going to do a rv32i glibc prerelease and try to build a proper userspace with the theory being that we'll shake out ABI bugs that way.
Quoted 38 lines · Palmer Dabbelt
Quoted 15 lines · On Thu, 20 Dec 2018 09:20:05 PST (-0800), [email protected] wrote:
Quoted 13 lines · Richard Henderson
Quoted 11 lines · Alistair Francis
This patch set adds RISC-V backend support to QEMU. This is based on Michael Clark's original work with extra work on top.
This has been somewhat tested and can run other architecture softmmu code. It seems that any complex OS will eventually hang, but we can run the BIOS and OS startup code for a number of different operating systems.
I haven't tested linux user support at all yet. I think Michael had that working reliably though and hopefully my changes haven't broken it.
Quoted 7 lines
Quoted 5 lines
Quoted 3 lines
There are still some todos in the code (there are missing instructions and byte swapping) but these should assert instead of generating invalid code.
Queued to tcg-next, with the extrh fix.
Thanks Richard!
Sounds good to me. I'm still attempting to collect the RISC-V patches to get a PR out, a few things came up but I should have time now. This was the biggest patch set, so it should be a lot easier now.
Thanks for picking this up!
Quoted 6 lines
Quoted 6 lines
Some of those todos are no longer todos, since e.g. bswap is now optional. Those asserts should never fire (as a good assert should do, I suppose).
The missing instructions are only for riscv32, which afaik is just now making its way to glibc. So a chroot complete enough to build qemu is a ways away. I'm ok with leaving that incomplete for now.
Quoted 5 lines
We've decided to delay the rv32i glibc port until after the next glibc release, which is targeted for the beginning of February. glibc should freeze at the end of the year, at which point we're going to do a rv32i glibc prerelease and try to build a proper userspace with the theory being that we'll shake out ABI bugs that way.
Yocto/OE has full support for building 32-bit userspaces with the latest 32-bit glibc patchset so that is probably a good place to start testing. It even runs QEMU!
Alistair
Quoted 45 lines · On Thu, 20 Dec 2018 11:04:41 PST (-0800), [email protected] wrote:
Quoted 38 lines · Palmer Dabbelt
Quoted 15 lines · On Thu, 20 Dec 2018 09:20:05 PST (-0800), [email protected] wrote:
Quoted 13 lines · Richard Henderson
Quoted 11 lines · Alistair Francis
This patch set adds RISC-V backend support to QEMU. This is based on Michael Clark's original work with extra work on top.
This has been somewhat tested and can run other architecture softmmu code. It seems that any complex OS will eventually hang, but we can run the BIOS and OS startup code for a number of different operating systems.
I haven't tested linux user support at all yet. I think Michael had that working reliably though and hopefully my changes haven't broken it.
Quoted 7 lines
Quoted 5 lines
Quoted 3 lines
There are still some todos in the code (there are missing instructions and byte swapping) but these should assert instead of generating invalid code.
Queued to tcg-next, with the extrh fix.
Thanks Richard!
Sounds good to me. I'm still attempting to collect the RISC-V patches to get a PR out, a few things came up but I should have time now. This was the biggest patch set, so it should be a lot easier now.
Thanks for picking this up!
Quoted 6 lines
Quoted 6 lines
Some of those todos are no longer todos, since e.g. bswap is now optional. Those asserts should never fire (as a good assert should do, I suppose).
The missing instructions are only for riscv32, which afaik is just now making its way to glibc. So a chroot complete enough to build qemu is a ways away. I'm ok with leaving that incomplete for now.
Quoted 5 lines
We've decided to delay the rv32i glibc port until after the next glibc release, which is targeted for the beginning of February. glibc should freeze at the end of the year, at which point we're going to do a rv32i glibc prerelease and try to build a proper userspace with the theory being that we'll shake out ABI bugs that way.
Quoted 3 lines
Yocto/OE has full support for building 32-bit userspaces with the latest 32-bit glibc patchset so that is probably a good place to start testing. It even runs QEMU!
That's my plan. The issue is less on the distro side and more on the "go through the whole rv32i glibc ABI to make sure it's sane" side.
Patchew URL: https://patchew.org/QEMU/[email protected]/
Patchew URL: https://patchew.org/QEMU/[email protected]/
Hi,
This series seems to have some coding style problems. See output below for more information:
Message-id: [email protected]
Type: series
Subject: [Qemu-devel] [PATCH v2 00/23] Add RISC-V TCG backend support
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
commits="$(git log --format=%H --reverse $BASE..)" for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
2236221 configure: Add support for building RISC-V host
e990378 dias: Add RISC-V support
713b47c tcg: Add RISC-V cpu signal handler
8ec51ee riscv: tcg-target: Add the target init code
3feff31 riscv: tcg-target: Add the prologue generation and register the JIT 702fdc0 riscv: tcg-target: Add the out op decoder
ed66ad3 riscv: tcg-target: Add direct load and store instructions fd97412 riscv: tcg-target: Add slowpath load and store instructions 5e6bb90 riscv: tcg-target: Add branch and jump instructions a066182 riscv: tcg-target: Add the add2 and sub2 instructions 8192923 riscv: tcg-target: Add the out load and store instructions 65e8bfc riscv: tcg-target: Add the extract instructions
37fba48 riscv: tcg-target: Add the mov and movi instruction e015e10 riscv: tcg-target: Add the relocation functions
67927da riscv: tcg-target: Add the instruction emitters
def52f9 riscv: tcg-target: Add the immediate encoders
db3a876 riscv: tcg-target: Add support for the constraints 472711b riscv: Add the tcg target registers
cb5271e riscv: Add the tcg-target header file
c053c44 exec: Add RISC-V GCC poison macro
a4660da linux-user: Add host dependency for RISC-V 64-bit cec4a16 linux-user: Add host dependency for RISC-V 32-bit 52105f5 elf.h: Add the RISCV ELF magic numbers
=== OUTPUT BEGIN ===
Checking PATCH 1/23: elf.h: Add the RISCV ELF magic numbers... Checking PATCH 2/23: linux-user: Add host dependency for RISC-V 32-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #24:
new file mode 100644
total: 0 errors, 1 warnings, 18 lines checked
Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS.
Checking PATCH 3/23: linux-user: Add host dependency for RISC-V 64-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #24:
new file mode 100644
total: 0 errors, 1 warnings, 18 lines checked
Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS.
Checking PATCH 4/23: exec: Add RISC-V GCC poison macro... Checking PATCH 5/23: riscv: Add the tcg-target header file...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #40:
new file mode 100644
WARNING: architecture specific defines should be avoided #72: FILE: tcg/riscv/tcg-target.h:28:
+#if __riscv_xlen == 32
total: 0 errors, 2 warnings, 199 lines checked
Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS.
Checking PATCH 6/23: riscv: Add the tcg target registers...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #12:
new file mode 100644
total: 0 errors, 1 warnings, 118 lines checked
Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 7/23: riscv: tcg-target: Add support for the constraints... Checking PATCH 8/23: riscv: tcg-target: Add the immediate encoders... Checking PATCH 9/23: riscv: tcg-target: Add the instruction emitters... Checking PATCH 10/23: riscv: tcg-target: Add the relocation functions... Checking PATCH 11/23: riscv: tcg-target: Add the mov and movi instruction... Checking PATCH 12/23: riscv: tcg-target: Add the extract instructions... Checking PATCH 13/23: riscv: tcg-target: Add the out load and store instructions... Checking PATCH 14/23: riscv: tcg-target: Add the add2 and sub2 instructions...
WARNING: Block comments use a leading /* on a separate line
#30: FILE: tcg/riscv/tcg-target.inc.c:710:
+ /* If we have a negative constant such that negating it would
WARNING: Block comments use * on subsequent lines
#31: FILE: tcg/riscv/tcg-target.inc.c:711:
+ /* If we have a negative constant such that negating it would
+ make the high part zero, we can (usually) eliminate one insn. */
WARNING: Block comments use a trailing */ on a separate line #31: FILE: tcg/riscv/tcg-target.inc.c:711:
+ make the high part zero, we can (usually) eliminate one insn. */
WARNING: Block comments use a leading /* on a separate line #38: FILE: tcg/riscv/tcg-target.inc.c:718:
+ /* By operating on the high part first, we get to use the final
WARNING: Block comments use * on subsequent lines
#39: FILE: tcg/riscv/tcg-target.inc.c:719:
+ /* By operating on the high part first, we get to use the final
+ carry operation to move back from the temporary. */
WARNING: Block comments use a trailing */ on a separate line #39: FILE: tcg/riscv/tcg-target.inc.c:719:
+ carry operation to move back from the temporary. */
total: 0 errors, 6 warnings, 58 lines checked
Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 15/23: riscv: tcg-target: Add branch and jump instructions... Checking PATCH 16/23: riscv: tcg-target: Add slowpath load and store instructions...
WARNING: Block comments use a leading /* on a separate line
#46: FILE: tcg/riscv/tcg-target.inc.c:925:
+/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
WARNING: Block comments use a leading /* on a separate line #68: FILE: tcg/riscv/tcg-target.inc.c:947:
+/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
WARNING: Block comments use a leading /* on a separate line #173: FILE: tcg/riscv/tcg-target.inc.c:1052:
+ /* TODO: Move this out of line
total: 0 errors, 3 warnings, 259 lines checked
Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 17/23: riscv: tcg-target: Add direct load and store instructions...
ERROR: spaces required around that '*' (ctx:WxV)
#74: FILE: tcg/riscv/tcg-target.inc.c:1209:
+ tcg_insn_unit *label_ptr[1];
^ERROR: spaces required around that '*' (ctx:WxV)
#145: FILE: tcg/riscv/tcg-target.inc.c:1280:
+ tcg_insn_unit *label_ptr[1];
^total: 2 errors, 0 warnings, 161 lines checked
Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS.
Checking PATCH 18/23: riscv: tcg-target: Add the out op decoder...
Checking PATCH 19/23: riscv: tcg-target: Add the prologue generation and register the JIT... Checking PATCH 20/23: riscv: tcg-target: Add the target init code...
Checking PATCH 21/23: tcg: Add RISC-V cpu signal handler...
WARNING: Block comments use a leading /* on a separate line
#29: FILE: accel/tcg/user-exec.c:585:
+ /* Detect store by reading the instruction at the program
WARNING: Block comments use * on subsequent lines
#30: FILE: accel/tcg/user-exec.c:586:
+ /* Detect store by reading the instruction at the program
+ counter. Note: we currently only generate 32-bit
WARNING: Block comments use a trailing */ on a separate line #31: FILE: accel/tcg/user-exec.c:587:
+ instructions so we thus only detect 32-bit stores */
total: 0 errors, 3 warnings, 81 lines checked
Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS.
Checking PATCH 22/23: dias: Add RISC-V support...
WARNING: architecture specific defines should be avoided #22: FILE: disas.c:526:
+#if defined(_ILP32) || (__riscv_xlen == 32)
total: 0 errors, 1 warnings, 16 lines checked
Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS.
Checking PATCH 23/23: configure: Add support for building RISC-V host... === OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/[email protected]/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to [email protected]