Add coresight support for SDM845 and MSM8996
Subsystems (5)
v4 cover Add coresight support for SDM845 and MSM8996
This patch series adds support for coresight on SDM845 and MSM8996.
* Patch 1 adds device tree nodes for SDM845 coresight components.
* Patch 2 adds device tree nodes for MSM8996 coresight components.
* Patch 3 enables support for ETMv4.2 and enables SDM845 to make use of same driver(etm4x).
* Patch 4 is a trivial removal of duplicate header file.
Patch 1 and 3 depends on below AOSS QMP patches by Bjorn:
https://patchwork.kernel.org/patch/10749469/
https://patchwork.kernel.org/patch/10749481/
https://patchwork.kernel.org/patch/10749479/
https://patchwork.kernel.org/patch/10749475/
This patch series has been tested on SDM845 MTP and MSM8996 based Dragonboard 820c.
v4:
* Mask out the minor version as suggested by Mathieu.
* Add the dependent patch description in patch 1.
v3:
* Added arm,scatter-gather property as suggested by Suzuki.
v2:
* Added coresight support for msm8996 based on Vivek's patch. Cleaned up and added coresight cpu debug nodes for msm8996.
* Merged coresight dtsi file into sdm845.dtsi as suggested by Bjorn
* Addressed Mathieu's feedback about masking the minor version in etm4_arch_supported() and added a comment for reason to bypass the AMBA bus discovery method.
Sai Prakash Ranjan (3):
arm64: dts: qcom: sdm845: Add Coresight support
coresight: etm4x: Add support to enable ETMv4.2
arm64: dts: qcom: sdm845: Remove the duplicate header inclusion
Vivek Gautam (1):
arm64: dts: qcom: msm8996: Add Coresight support
arch/arm64/boot/dts/qcom/msm8996.dtsi | 448 +++++++++++++++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 449 +++++++++++++++++- drivers/hwtracing/coresight/coresight-etm4x.c | 3 +- 3 files changed, 898 insertions(+), 2 deletions(-)
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v4 1/4 arm64: dts: qcom: sdm845: Add Coresight support
Add coresight components found on Qualcomm SDM845 SoC.
---
Depends on AOSS QMP side channel patches and AMBA bus pclk change by Bjorn Andersson [1][2].
Also depends on patch ("arm64: dts: qcom: sdm845: Increase address and size cells for soc") [3].
[1] https://lore.kernel.org/lkml/[email protected]/
[2] https://lore.kernel.org/lkml/[email protected]/
[3] https://lore.kernel.org/lkml/[email protected]/
--- arch/arm64/boot/dts/qcom/sdm845.dtsi | 448 +++++++++++++++++++++++++++ 1 file changed, 448 insertions(+)
arch/arm64/boot/dts/qcom/sdm845.dtsi +448 -0
@@ -1348,6 +1348,454 @@ }; }; + stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x06002000 0 0x1000>, + <0 0x16280000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = + <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x06041000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@6043000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x06043000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + funnel2_out: endpoint { + remote-endpoint = + <&merge_funnel_in2>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + funnel2_in5: endpoint { + remote-endpoint = + <&apss_merge_funnel_out>; + }; + }; + }; + }; + + funnel@6045000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x06045000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@2 { + reg = <2>; + merge_funnel_in2: endpoint { + remote-endpoint = + <&funnel2_out>; + }; + }; + }; + }; + + replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06046000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf@6047000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06047000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + etf_in: endpoint { + remote-endpoint = + <&merge_funnel_out>; + }; + }; + }; + }; + + etr@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06048000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = + <&replicator_out>; + }; + }; + }; + }; + + /* + * On QCOM SDM845, we bypass the normal AMBA bus discovery + * method by forcing the peripheral ID because of the wrong + * value read from ETM PID registers. + */ + + etm@7040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0 0x07040000 0 0x1000>; + + cpu = <&CPU0>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0 0x07140000 0 0x1000>; + + cpu = <&CPU1>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0 0x07240000 0 0x1000>; + + cpu = <&CPU2>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0 0x07340000 0 0x1000>; + + cpu = <&CPU3>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel_in3>; + }; + }; + }; + }; + + etm@7440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0 0x07440000 0 0x1000>; + + cpu = <&CPU4>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&apss_funnel_in4>; + }; + }; + }; + }; + + etm@7540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0 0x07540000 0 0x1000>; + + cpu = <&CPU5>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&apss_funnel_in5>; + }; + }; + }; + }; + + etm@7640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0 0x07640000 0 0x1000>; + + cpu = <&CPU6>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&apss_funnel_in6>; + }; + }; + }; + }; + + etm@7740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0 0x07740000 0 0x1000>; + + cpu = <&CPU7>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&apss_funnel_in7>; + }; + }; + }; + }; + + funnel@7800000 { /* APSS Funnel */ + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x07800000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel_in0: endpoint { + remote-endpoint = + <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel_in1: endpoint { + remote-endpoint = + <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel_in2: endpoint { + remote-endpoint = + <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel_in3: endpoint { + remote-endpoint = + <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel_in4: endpoint { + remote-endpoint = + <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel_in5: endpoint { + remote-endpoint = + <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel_in6: endpoint { + remote-endpoint = + <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel_in7: endpoint { + remote-endpoint = + <&etm7_out>; + }; + }; + }; + }; + + funnel@7810000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x07810000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = + <&funnel2_in5>; + }; + }; + }; + + in-ports { + port { + apss_merge_funnel_in: endpoint { + remote-endpoint = + <&apss_funnel_out>; + }; + }; + }; + }; + usb_1_hsphy: phy@88e2000 { compatible = "qcom,sdm845-qusb2-phy"; reg = <0x88e2000 0x400>;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v4 2/4 arm64: dts: qcom: msm8996: Add Coresight support
In reply to Sai Prakash RanjanFrom: Vivek Gautam <[email protected]>
Enable coresight support by adding device nodes for the available source, sinks and channel blocks on msm8996.
This also adds coresight cpu debug nodes.
--- arch/arm64/boot/dts/qcom/msm8996.dtsi | 448 ++++++++++++++++++++++++++ 1 file changed, 448 insertions(+)
arch/arm64/boot/dts/qcom/msm8996.dtsi +448 -0
@@ -429,6 +429,454 @@ reg = <0x300000 0x90000>; }; + stm@3002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x3002000 0x1000>, + <0x8280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = + <&funnel0_in>; + }; + }; + }; + }; + + tpiu@3020000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x3020000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + tpiu_in: endpoint { + remote-endpoint = + <&replicator_out1>; + }; + }; + }; + }; + + funnel@3021000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x3021000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + funnel0_in: endpoint { + remote-endpoint = + <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&merge_funnel_in0>; + }; + }; + }; + }; + + funnel@3022000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x3022000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + funnel1_in: endpoint { + remote-endpoint = + <&apss_merge_funnel_out>; + }; + }; + }; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = + <&merge_funnel_in1>; + }; + }; + }; + }; + + funnel@3025000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x3025000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = + <&funnel1_out>; + }; + }; + }; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = + <&etf_in>; + }; + }; + }; + }; + + replicator@3026000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x3026000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = + <&etf_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = + <&etr_in>; + }; + }; + + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = + <&tpiu_in>; + }; + }; + }; + }; + + etf@3027000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x3027000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = + <&merge_funnel_out>; + }; + }; + }; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + }; + + etr@3028000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x3028000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = + <&replicator_out0>; + }; + }; + }; + }; + + /* + * On msm8996, we bypass the normal AMBA bus discovery + * method by forcing the peripheral ID because of the wrong + * value read from PID registers. + */ + + debug@3810000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + arm,primecell-periphid = <0x000bbd03>; + reg = <0x3810000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU0>; + }; + + etm@3840000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x3840000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU0>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel0_in0>; + }; + }; + }; + }; + + debug@3910000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + arm,primecell-periphid = <0x000bbd03>; + reg = <0x3910000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + }; + + etm@3940000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x3940000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU1>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel0_in1>; + }; + }; + }; + }; + + funnel@39b0000 { /* APSS Funnel 0 */ + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x39b0000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel0_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel0_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + }; + + out-ports { + port { + apss_funnel0_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in0>; + }; + }; + }; + }; + + debug@3a10000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + arm,primecell-periphid = <0x000bbd03>; + reg = <0x3a10000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU2>; + }; + + etm@3a40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x3a40000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU2>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel1_in0>; + }; + }; + }; + }; + + debug@3b10000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + arm,primecell-periphid = <0x000bbd03>; + reg = <0x3b10000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + }; + + etm@3b40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x3b40000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU3>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel1_in1>; + }; + }; + }; + }; + + funnel@3bb0000 { /* APSS Funnel 1 */ + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x3bb0000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel1_in0: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel1_in1: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + + out-ports { + port { + apss_funnel1_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in1>; + }; + }; + }; + }; + + funnel@3bc0000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x3bc0000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_merge_funnel_in0: endpoint { + remote-endpoint = + <&apss_funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_merge_funnel_in1: endpoint { + remote-endpoint = + <&apss_funnel1_out>; + }; + }; + }; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = + <&funnel1_in>; + }; + }; + }; + }; + kryocc: clock-controller@6400000 { compatible = "qcom,apcc-msm8996"; reg = <0x6400000 0x90000>;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v4 3/4 coresight: etm4x: Add support to enable ETMv4.2
In reply to Sai Prakash RanjanSDM845 has ETMv4.2 and can use the existing etm4x driver. But the current etm driver checks only for ETMv4.0 and errors out for other etm4x versions. This patch adds this missing support to enable SoC's with ETMv4x to use same driver by checking only the ETM architecture major version number.
Without this change, we get below error during etm probe:
/ # dmesg | grep etm
[ 6.660093] coresight-etm4x: probe of 7040000.etm failed with error -22 [ 6.666902] coresight-etm4x: probe of 7140000.etm failed with error -22 [ 6.673708] coresight-etm4x: probe of 7240000.etm failed with error -22 [ 6.680511] coresight-etm4x: probe of 7340000.etm failed with error -22 [ 6.687313] coresight-etm4x: probe of 7440000.etm failed with error -22 [ 6.694113] coresight-etm4x: probe of 7540000.etm failed with error -22 [ 6.700914] coresight-etm4x: probe of 7640000.etm failed with error -22 [ 6.707717] coresight-etm4x: probe of 7740000.etm failed with error -22
With this change, etm probe is successful:
/ # dmesg | grep coresight
[ 6.659198] coresight-etm4x 7040000.etm: CPU0: ETM v4.2 initialized [ 6.665848] coresight-etm4x 7140000.etm: CPU1: ETM v4.2 initialized [ 6.672493] coresight-etm4x 7240000.etm: CPU2: ETM v4.2 initialized [ 6.679129] coresight-etm4x 7340000.etm: CPU3: ETM v4.2 initialized [ 6.685770] coresight-etm4x 7440000.etm: CPU4: ETM v4.2 initialized [ 6.692403] coresight-etm4x 7540000.etm: CPU5: ETM v4.2 initialized [ 6.699024] coresight-etm4x 7640000.etm: CPU6: ETM v4.2 initialized [ 6.705646] coresight-etm4x 7740000.etm: CPU7: ETM v4.2 initialized
--- drivers/hwtracing/coresight/coresight-etm4x.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/hwtracing/coresight/coresight-etm4x.c +2 -1
@@ -55,7 +55,8 @@ static void etm4_os_unlock(struct etmv4_drvdata *drvdata)static bool etm4_arch_supported (u8 arch) { -switch (arch) { +/* Mask out the minor version number */ +switch (arch &0xf0 ) {case ETM_ARCH_V4 :break ;default :
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v4 4/4 arm64: dts: qcom: sdm845: Remove the duplicate header inclusion
In reply to Sai Prakash RanjanRemove the duplicate inclusion of qcom,gcc-sdm845.h mistakenly introduced by commit 6e17f8140521 ("arm64:
dts: sdm845: add prng-ee node").
--- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 - 1 file changed, 1 deletion(-)
arch/arm64/boot/dts/qcom/sdm845.dtsi +0 -1
@@ -12,7 +12,6 @@ #include <dt-bindings/phy/phy-qcom-qusb2.h> #include <dt-bindings/reset/qcom,sdm845-aoss.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> -#include <dt-bindings/clock/qcom,gcc-sdm845.h> / { interrupt-parent = <&intc>;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Suzuki K Poulose
maintainerRe: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
In reply to Sai Prakash RanjanHi Sai,
Quoted 4 lines · Sai Prakash Ranjan
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>
Sorry, but I hadn't noticed the PID override strings below. Please find the question.
Quoted 9 lines
---
Depends on AOSS QMP side channel patches and AMBA bus pclk change by Bjorn Andersson [1][2].
Also depends on patch ("arm64: dts: qcom: sdm845: Increase address and size cells for soc") [3].[1] https://lore.kernel.org/lkml/[email protected]/
[2] https://lore.kernel.org/lkml/[email protected]/
[3] https://lore.kernel.org/lkml/[email protected]/
[...]
};
Quoted 13 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi +13
-0+ + etr@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06048000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = + <&replicator_out>;
arch/arm64/boot/dts/qcom/sdm845.dtsi line 1535
Quoted 10 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi +10
-0+ }; + }; + }; + }; + + /* + * On QCOM SDM845, we bypass the normal AMBA bus discovery + * method by forcing the peripheral ID because of the wrong + * value read from ETM PID registers. + */
What is the value read back from the ETM PIDx registers ? Do they provide inconsistent or incompatible value w.r.t the ETM/Coresight architecture ? If it is an unsupported CPU with proper values, you must add them to the table in etm4x driver.
arch/arm64/boot/dts/qcom/sdm845.dtsi line 1543
Quoted 6 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi +6
-0+ etm@7040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d> > + reg = <0 0x07040000 0 0x1000>; + + cpu = <&CPU0>; +
You seem to be specifying the PID of A53 ETM all over, while at least one of your cores is ETMv4.2 (from the other patch) and A53 is not ETMv4.2. As above, it would be good to add the PID to the table.
Suzuki
Re: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
Hi Suzuki,
Thanks for looking into this. Please find my response inline.
Quoted 11 lines · Suzuki K Poulose
Hi Sai,
Quoted 4 lines · Sai Prakash Ranjan
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>Sorry, but I hadn't noticed the PID override strings below. Please find the question.
[..]
Quoted 11 lines
Quoted 5 lines
+ /*
+ * On QCOM SDM845, we bypass the normal AMBA bus discovery + * method by forcing the peripheral ID because of the wrong + * value read from ETM PID registers.
+ */What is the value read back from the ETM PIDx registers ? Do they provide inconsistent or incompatible value w.r.t the ETM/Coresight architecture ? If it is an unsupported CPU with proper values, you must add them to the table in etm4x driver.
The values read from ETM PIDx registers are actually inconsistent and is different for some ETMs.
Below are the PIDs read for SDM845:
[ 5.996448] resname=etm@7040000 pid=001bb803 [ 6.052891] resname=etm@7140000 pid=001bb803
<snip> .. (Same pid=001bb803 for etm@7240000 to etm@7540000 but differs for other 2 cpus as shown below)
[ 6.266687] resname=etm@7640000 pid=001bb802 [ 6.329171] resname=etm@7740000 pid=001bb802
This is the case for MSM8996 also as shown below where PID value is not correct and has to be hardcoded.
For MSM8996:
resname=etm@3b40000 pid=102f0205
Quoted 12 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi line 1543
Quoted 7 lines
+ etm@7040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d> > + reg = <00x0704000000x1000>;arch/arm64/boot/dts/qcom/sdm845.dtsi +3
-0+ + cpu = <&CPU0>; +You seem to be specifying the PID of A53 ETM all over, while at least one of your cores is ETMv4.2 (from the other patch) and A53 is not ETMv4.2. As above, it would be good to add the PID to the table.
As explained in above comment, PID values read are not correct. Please let me know if I am not clear.
Thanks,
Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Suzuki K Poulose
maintainerRe: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
Hi Sai,
Quoted 24 lines · Sai Prakash Ranjan
Hi Suzuki,
Thanks for looking into this. Please find my response inline.
Quoted 11 lines · Suzuki K Poulose
Hi Sai,
Quoted 4 lines · Sai Prakash Ranjan
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>Sorry, but I hadn't noticed the PID override strings below. Please find the question.
[..]
Quoted 6 lines
Quoted 5 lines
+ /*
+ * On QCOM SDM845, we bypass the normal AMBA bus discovery + * method by forcing the peripheral ID because of the wrong + * value read from ETM PID registers.
+ */
Quoted 8 lines
Quoted 5 lines
What is the value read back from the ETM PIDx registers ? Do they provide inconsistent or incompatible value w.r.t the ETM/Coresight architecture ? If it is an unsupported CPU with proper values, you must add them to the table in etm4x driver.
The values read from ETM PIDx registers are actually inconsistent and is different for some ETMs.
By inconsistent, I meant the registers provides values which are not the same on two different CPUs of the *same type*. And it is expected that two different CPU/ETM implementations will have different PIDs.
Quoted 6 lines
Below are the PIDs read for SDM845:
[ 5.996448] resname=etm@7040000 pid=001bb803
[ 6.052891] resname=etm@7140000 pid=001bb803
Quoted 8 lines
<snip> .. (Same pid=001bb803 for etm@7240000 to etm@7540000 but differs for other 2 cpus as shown below)
[ 6.266687] resname=etm@7640000 pid=001bb802
[ 6.329171] resname=etm@7740000 pid=001bb802This is the case for MSM8996 also as shown below where PID value is not correct and has to be hardcoded.
They differ because they are two different types of CPU cores (and thus different ETM PIDs). What does the Register descriptions say for the Cores ?
To me it looks like there are two different types of Qualcomm Cores with their respective ETMs which are missing in the ETM4x driver and we are trying to "make the ETM" work by faking it as something else, which is not nice. I would rather prefer to add the appropriate masks and the expected value for these two different ETM implementations and be done with it, instead of faking it in all the DTs where these cores appear.
Quoted 4 lines
For MSM8996:
resname=etm@3b40000 pid=102f0205
I don't know what CPUs the MSM8996 have. If they don't have A53, you must add the actual PIDs to the table once and for all.
Quoted 14 lines
Quoted 13 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi line 1543
Quoted 8 lines
+ etm@7040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d> > + reg = <00x0704000000x1000>;arch/arm64/boot/dts/qcom/sdm845.dtsi +3
-0+ + cpu = <&CPU0>; +You seem to be specifying the PID of A53 ETM all over, while at least one of your cores is ETMv4.2 (from the other patch) and A53 is not ETMv4.2. As above, it would be good to add the PID to the table.
Quoted 1 line
As explained in above comment, PID values read are not correct. Please let me know if I am not clear.
There is no measure for "correctness" here. If the ETM exposes different PID than what you expect from the TRM, then we could think of overriding it. Otherwise please add the PIDs to the table.
Cheers
Suzuki
Re: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
Hi Suzuki,
Quoted 5 lines · Suzuki K Poulose
By inconsistent, I meant the registers provides values which are not the same on two different CPUs of the *same type*. And it is expected that two different CPU/ETM implementations will have different PIDs.
SDM845 has 4 Kryo 385 Gold (ARM A75) + 4 Kryo 385 Silver (ARM A55), so the PID values should be same for 4 ETMs atleast. But here one pid value(001bb803) is same for 6 ETMs and other one for 2 ETMs(001bb802) which seems odd and hence the doubt if these pids are even valid ones.
Quoted 18 lines
Quoted 6 lines
Below are the PIDs read for SDM845:
[ 5.996448] resname=etm@7040000 pid=001bb803
[ 6.052891] resname=etm@7140000 pid=001bb803Quoted 8 lines
<snip> .. (Same pid=001bb803 for etm@7240000 to etm@7540000 but differs for other 2 cpus as shown below)
[ 6.266687] resname=etm@7640000 pid=001bb802
[ 6.329171] resname=etm@7740000 pid=001bb802This is the case for MSM8996 also as shown below where PID value is not correct and has to be hardcoded.
They differ because they are two different types of CPU cores (and thus different ETM PIDs). What does the Register descriptions say for the Cores ?
Quoted 8 lines
To me it looks like there are two different types of Qualcomm Cores with their respective ETMs which are missing in the ETM4x driver and we are trying to "make the ETM" work by faking it as something else, which is not nice. I would rather prefer to add the appropriate masks and the expected value for these two different ETM implementations and be done with it, instead of faking it in all the DTs where these cores appear.
ETM4x driver does not have entries for A55 and A75. Could you please let me know the PIDs for these CPUs so that we can compare?
Quoted 8 lines
Quoted 4 lines
For MSM8996:
resname=etm@3b40000 pid=102f0205
I don't know what CPUs the MSM8996 have. If they don't have A53, you must add the actual PIDs to the table once and for all.
But again, this PID is some invalid value. And does not correspond to any of the ARM CPU cores and would be MSM8996 specific. MSM8996 has 2+2 Kryo cores which are not ARM derivative as SDM845 if I am right.
Quoted 14 lines
Quoted 14 lines
Quoted 13 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi line 1543
Quoted 8 lines
+ etm@7040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d> > + reg = <00x0704000000x1000>;arch/arm64/boot/dts/qcom/sdm845.dtsi +3
-0+ + cpu = <&CPU0>; +You seem to be specifying the PID of A53 ETM all over, while at least one of your cores is ETMv4.2 (from the other patch) and A53 is not ETMv4.2. As above, it would be good to add the PID to the table.
Quoted 6 lines
Quoted 1 line
As explained in above comment, PID values read are not correct. Please let me know if I am not clear.
There is no measure for "correctness" here. If the ETM exposes different PID than what you expect from the TRM, then we could think of overriding it. Otherwise please add the PIDs to the table.
This is exactly the case, ETM PID registers are exposing some invalid value and hence we override in DT.
Thanks,
Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Suzuki K Poulose
maintainerRe: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
Hi Sai,
Quoted 9 lines · Sai Prakash Ranjan
Hi Suzuki,
Quoted 5 lines · Suzuki K Poulose
By inconsistent, I meant the registers provides values which are not the same on two different CPUs of the *same type*. And it is expected that two different CPU/ETM implementations will have different PIDs.
Quoted 5 lines
SDM845 has 4 Kryo 385 Gold (ARM A75) + 4 Kryo 385 Silver (ARM A55), so the PID values should be same for 4 ETMs atleast. But here one pid value(001bb803) is same for 6 ETMs and other one for 2 ETMs(001bb802) which seems odd and hence the doubt if these pids are even valid ones.
Have you checked other SoCs with A55 for the ETM PID ? The drivers usually only care about PID0[7-0], PID1[7-0], PID2[3-0] and ignores the other fields that may change over revisions of the core. So, in your case the ETM ID could be treated as 0xbb802 and 0xbb803.
Quoted 9 lines
Quoted 9 lines
Quoted 9 lines
Below are the PIDs read for SDM845:
[ 5.996448] resname=etm@7040000 pid=001bb803
[ 6.052891] resname=etm@7140000 pid=001bb803<snip> .. (Same pid=001bb803 for etm@7240000 to etm@7540000 but differs for other 2 cpus as shown below)
So thats 4 CPUs with 0x1bb803.
Quoted 21 lines
Quoted 12 lines
Quoted 8 lines
[ 6.266687] resname=etm@7640000 pid=001bb802
[ 6.329171] resname=etm@7740000 pid=001bb802This is the case for MSM8996 also as shown below where PID value is not correct and has to be hardcoded.
They differ because they are two different types of CPU cores (and thus different ETM PIDs). What does the Register descriptions say for the Cores ?
Quoted 8 lines
To me it looks like there are two different types of Qualcomm Cores with their respective ETMs which are missing in the ETM4x driver and we are trying to "make the ETM" work by faking it as something else, which is not nice. I would rather prefer to add the appropriate masks and the expected value for these two different ETM implementations and be done with it, instead of faking it in all the DTs where these cores appear.
Quoted 2 lines
ETM4x driver does not have entries for A55 and A75. Could you please let me know the PIDs for these CPUs so that we can compare?
FWIW, here is the PID list:
A75: 0xB_BD_0A
A55: 0xB_BD_05
Btw, I am not sure if the ETM has been changed/tuned for the Cores in SDM845. Please could you get this clarified internally within your organisation ?
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines
For MSM8996:
resname=etm@3b40000 pid=102f0205
Quoted 8 lines
Quoted 3 lines
I don't know what CPUs the MSM8996 have. If they don't have A53, you must add the actual PIDs to the table once and for all.
But again, this PID is some invalid value. And does not correspond to any of the ARM CPU cores and would be MSM8996 specific. MSM8996 has 2+2 Kryo cores which are not ARM derivative as SDM845 if I am right.
As long as the JEP106 coding standard is followed and is indicated in
the appropriate fields (PIDR2[3]), we should be fine. In the case above:
PID of the ETM is 0xf0205, implies JEP106 code[6:0] of the designer is 0x70 and ETM part number is : 0x205, which makes sense to me.
Quoted 17 lines
Quoted 17 lines
Quoted 16 lines
Quoted 14 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi line 1543
Quoted 9 lines
+ etm@7040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d> > + reg = <00x0704000000x1000>;arch/arm64/boot/dts/qcom/sdm845.dtsi +3
-0+ + cpu = <&CPU0>; +You seem to be specifying the PID of A53 ETM all over, while at least one of your cores is ETMv4.2 (from the other patch) and A53 is not ETMv4.2. As above, it would be good to add the PID to the table.
As explained in above comment, PID values read are not correct. Please let me know if I am not clear.
Quoted 7 lines
Quoted 4 lines
There is no measure for "correctness" here. If the ETM exposes different PID than what you expect from the TRM, then we could think of overriding it. Otherwise please add the PIDs to the table.
This is exactly the case, ETM PID registers are exposing some invalid value and hence we override in DT.
It would be good to have this clarified. I will check with the internal teams here for any details.
Thanks
Suzuki
Re: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
Hi Suzuki,
Quoted 5 lines · Suzuki K Poulose
Hi Sai,
Quoted 2 lines · Sai Prakash Ranjan
Hi Suzuki,
[..]
Quoted 7 lines
Quoted 6 lines
SDM845 has 4 Kryo 385 Gold (ARM A75) + 4 Kryo 385 Silver (ARM A55), so the PID values should be same for 4 ETMs atleast. But here one pid value(001bb803) is same for 6 ETMs and other one for 2 ETMs(001bb802) which seems odd and hence the doubt if these pids are even valid ones.
Quoted 5 lines
Have you checked other SoCs with A55 for the ETM PID ? The drivers usually only care about PID0[7-0], PID1[7-0], PID2[3-0] and ignores the other fields that may change over revisions of the core. So, in your case the ETM ID could be treated as
0xbb802and0xbb803.
Very sorry to have mislead you here. I checked again today on SDM845 and as you said 4 ETMs based on A75 has 0xbb803 and other 4 ETMs based on A55 has 0Xbb803. I wrongly mentioned it as 6 and 2.
[ 6.688809] resname=etm@7040000 pid = 0x1bb803 [ 6.694957] [ 6.694957] resname=etm@7140000 pid = 0x1bb803 [ 6.701135] [ 6.701135] resname=etm@7240000 pid = 0x1bb803 [ 6.707256] [ 6.707256] resname=etm@7340000 pid = 0x1bb803 [ 6.713454] [ 6.713454] resname=etm@7440000 pid = 0x1bb802 [ 6.719621] [ 6.719621] resname=etm@7540000 pid = 0x1bb802 [ 6.725814] [ 6.725814] resname=etm@7640000 pid = 0x1bb802 [ 6.731971] [ 6.731971] resname=etm@7740000 pid = 0x1bb802
So is it ok to add these to table as below in etm4x driver with the following comment since these do not exactly match A75 and A55 PIDs which you provided? Or any other way you prefer?
@@ -1079,6 +1079,10 @@ static const struct amba_id etm4_ids[] = {
ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */
ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */
ETM4x_AMBA_ID(0x000bb9da), /* Cortex-A35 */
+ ETM4x_AMBA_ID(0x000f0211), /* Qualcomm Kryo */
+ ETM4x_AMBA_ID(0x000f0205), /* Qualcomm Kryo */
+ ETM4x_AMBA_ID(0x000bb803), /* Qualcomm Kryo 385 Cortex-A75 */
+ ETM4x_AMBA_ID(0x000bb802), /* Qualcomm Kryo 385 Cortex-A55 */
{},};
For msm8996, cpu debug module pid returned is same as ETM
which is causing the probe failure for cpu debug coresight module
as shown in below logs.
For this case, I tried adding these ids to cpu debug driver, but it
splits some errors (coresight-cpu-debug: probe of 3840000.etm failed with error -16) since the ids are same. Can we override for this case or there is something else we can do here?
[ 5.480629] resname=debug@3810000 pid = 0x102f0211 [ 5.480920] OF: graph: no port node found in /soc/debug@3810000 [ 5.513214] coresight-etm4x: probe of 3810000.debug failed with error -22 [ 5.524362] [ 5.524362] resname=debug@3910000 pid = 0x102f0211 [ 5.524888] OF: graph: no port node found in /soc/debug@3910000 [ 5.537586] coresight-etm4x: probe of 3910000.debug failed with error -22 [ 5.541481] [ 5.549643] resname=debug@3a10000 pid = 0x102f0205 [ 5.580990] OF: graph: no port node found in /soc/debug@3a10000 [ 5.586817] coresight-etm4x: probe of 3a10000.debug failed with error -22 [ 5.592082] [ 5.592629] resname=debug@3b10000 pid = 0x102f0205 [ 5.604922] OF: graph: no port node found in /soc/debug@3b10000 [ 5.611234] coresight-etm4x: probe of 3b10000.debug failed with error -22
Thanks,
Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
Quoted 27 lines · Sai Prakash Ranjan
Hi Suzuki,
Quoted 5 lines · Suzuki K Poulose
Hi Sai,
Quoted 2 lines · Sai Prakash Ranjan
Hi Suzuki,
[..]
Quoted 7 lines
Quoted 6 lines
SDM845 has 4 Kryo 385 Gold (ARM A75) + 4 Kryo 385 Silver (ARM A55), so the PID values should be same for 4 ETMs atleast. But here one pid value(001bb803) is same for 6 ETMs and other one for 2 ETMs(001bb802) which seems odd and hence the doubt if these pids are even valid ones.
Quoted 5 lines
Have you checked other SoCs with A55 for the ETM PID ? The drivers usually only care about PID0[7-0], PID1[7-0], PID2[3-0] and ignores the other fields that may change over revisions of the core. So, in your case the ETM ID could be treated as
0xbb802and0xbb803.Very sorry to have mislead you here. I checked again today on SDM845 and as you said 4 ETMs based on A75 has
0xbb803and other 4 ETMs based on A55 has0Xbb803. I wrongly mentioned it as 6 and 2.
Quoted 16 lines
[ 6.688809] resname=etm@7040000 pid = 0x1bb803 [ 6.694957] [ 6.694957] resname=etm@7140000 pid = 0x1bb803 [ 6.701135] [ 6.701135] resname=etm@7240000 pid = 0x1bb803 [ 6.707256] [ 6.707256] resname=etm@7340000 pid = 0x1bb803 [ 6.713454] [ 6.713454] resname=etm@7440000 pid = 0x1bb802 [ 6.719621] [ 6.719621] resname=etm@7540000 pid = 0x1bb802 [ 6.725814] [ 6.725814] resname=etm@7640000 pid = 0x1bb802 [ 6.731971] [ 6.731971] resname=etm@7740000 pid = 0x1bb802
Ok, so that makes sense.
Quoted 3 lines
So is it ok to add these to table as below in etm4x driver with the following comment since these do not exactly match A75 and A55 PIDs which you provided? Or any other way you prefer?
That depends on whether the ETMs have been modified at all, something Suzuki has asked to be clarified. If ETMs have been modified then we need to understand how they differ from the driver's implementation. If the implementations are the same:
Review static const struct amba_id etm4_ids[] = { · line 1083
Quoted 7 lines
(quoted diff) +2
-0@@ -1079,6 +1079,10 @@ static const struct amba_id etm4_ids[] = { ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */ ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */ ETM4x_AMBA_ID(0x000bb9da), /* Cortex-A35 */ + ETM4x_AMBA_ID(0x000f0211), /* Qualcomm Kryo */ + ETM4x_AMBA_ID(0x000f0205), /* Qualcomm Kryo */
What version of the Kryo CPU? And the above will need to be in a separate patch with the modifications to address the problem you mentionned below.
Quoted 4 lines
(quoted diff) +1
-0+ ETM4x_AMBA_ID(0x000bb803), /* Qualcomm Kryo 385Cortex-A75 */
+ETM4x_AMBA_ID(0x000bb802), /* Qualcomm Kryo 385
Cortex-A55 */
Please add them in chronological order.
Quoted 10 lines
{},};
For msm8996, cpu debug module pid returned is same as ETM which is causing the probe failure for cpu debug coresight module as shown in below logs.
For this case, I tried adding these ids to cpu debug driver, but it splits some errors (coresight-cpu-debug: probe of 3840000.etm failed with error -16) since the ids are same. Can we override for this case or there is something else we can do here?
That is another problem. See this patchset [1] from Mike Leach for a description of the problem and how to fix it.
[1]. https://lkml.org/lkml/2018/12/7/784
Quoted 24 lines
[ 5.480629] resname=debug@3810000 pid = 0x102f0211 [ 5.480920] OF: graph: no port node found in /soc/debug@3810000 [ 5.513214] coresight-etm4x: probe of 3810000.debug failed with error -22 [ 5.524362] [ 5.524362] resname=debug@3910000 pid = 0x102f0211 [ 5.524888] OF: graph: no port node found in /soc/debug@3910000 [ 5.537586] coresight-etm4x: probe of 3910000.debug failed with error -22 [ 5.541481] [ 5.549643] resname=debug@3a10000 pid = 0x102f0205 [ 5.580990] OF: graph: no port node found in /soc/debug@3a10000 [ 5.586817] coresight-etm4x: probe of 3a10000.debug failed with error -22 [ 5.592082] [ 5.592629] resname=debug@3b10000 pid = 0x102f0205 [ 5.604922] OF: graph: no port node found in /soc/debug@3b10000 [ 5.611234] coresight-etm4x: probe of 3b10000.debug failed with error -22Thanks,
Sai--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
Hi Mathieu,
Quoted 6 lines · Mathieu Poirier
On Wed, 23 Jan 2019 at 05:12, Sai Prakash Ranjan
<[email protected]> wrote:That depends on whether the ETMs have been modified at all, something Suzuki has asked to be clarified. If ETMs have been modified then we need to understand how they differ from the driver's implementation.
We had asked hardware team for clarification regarding this. Let me poke them again. As for the driver, downstream implementation also uses the same driver, so I am not sure what do you mean by differing from the driver's implementation.
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If the implementations are the same:
Review static const struct amba_id etm4_ids[] = { · line 1083
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-0@@ -1079,6 +1079,10 @@ static const struct amba_id etm4_ids[] = { ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */ ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */ ETM4x_AMBA_ID(0x000bb9da), /* Cortex-A35 */ + ETM4x_AMBA_ID(0x000f0211), /* Qualcomm Kryo */ + ETM4x_AMBA_ID(0x000f0205), /* Qualcomm Kryo */What version of the Kryo CPU? And the above will need to be in a separate patch with the modifications to address the problem you mentionned below.
There is no Kryo version for MSM8996 (its only given as Kryo), MSM8998 onwards we have Kryo versions like Kryo 280 and so on. Hence I skipped for this one and added the version for SDM845.
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-0+ ETM4x_AMBA_ID(0x000bb803), /* Qualcomm Kryo 385Cortex-A75 */
+ETM4x_AMBA_ID(0x000bb802), /* Qualcomm Kryo 385
Cortex-A55 */Please add them in chronological order.
Sure, will do it.
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{},};
For msm8996, cpu debug module pid returned is same as ETM which is causing the probe failure for cpu debug coresight module as shown in below logs.
For this case, I tried adding these ids to cpu debug driver, but it splits some errors (coresight-cpu-debug: probe of 3840000.etm failed with error -16) since the ids are same. Can we override for this case or there is something else we can do here?
Quoted 5 lines
That is another problem. See this patchset [1] from Mike Leach for a description of the problem and how to fix it.
Thanks a lot for this link. I will check this out.
- Sai
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Suzuki K Poulose
maintainerRe: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
In reply to Sai Prakash RanjanHi Sai,
Quoted 56 lines · Sai Prakash Ranjan
Hi Suzuki,
Quoted 5 lines · Suzuki K Poulose
Hi Sai,
Quoted 2 lines · Sai Prakash Ranjan
Hi Suzuki,
[..]
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SDM845 has 4 Kryo 385 Gold (ARM A75) + 4 Kryo 385 Silver (ARM A55), so the PID values should be same for 4 ETMs atleast. But here one pid value(001bb803) is same for 6 ETMs and other one for 2 ETMs(001bb802) which seems odd and hence the doubt if these pids are even valid ones.
Quoted 5 lines
Have you checked other SoCs with A55 for the ETM PID ? The drivers usually only care about PID0[7-0], PID1[7-0], PID2[3-0] and ignores the other fields that may change over revisions of the core. So, in your case the ETM ID could be treated as
0xbb802and0xbb803.Very sorry to have mislead you here. I checked again today on SDM845 and as you said 4 ETMs based on A75 has
0xbb803and other 4 ETMs based on A55 has0Xbb803. I wrongly mentioned it as 6 and 2.[ 6.688809] resname=etm@7040000 pid = 0x1bb803 [ 6.694957] [ 6.694957] resname=etm@7140000 pid = 0x1bb803 [ 6.701135] [ 6.701135] resname=etm@7240000 pid = 0x1bb803 [ 6.707256] [ 6.707256] resname=etm@7340000 pid = 0x1bb803 [ 6.713454] [ 6.713454] resname=etm@7440000 pid = 0x1bb802 [ 6.719621] [ 6.719621] resname=etm@7540000 pid = 0x1bb802 [ 6.725814] [ 6.725814] resname=etm@7640000 pid = 0x1bb802 [ 6.731971] [ 6.731971] resname=etm@7740000 pid = 0x1bb802So is it ok to add these to table as below in etm4x driver with the following comment since these do not exactly match A75 and A55 PIDs which you provided? Or any other way you prefer?
(quoted diff) +3
-0@@ -1079,6 +1079,10 @@ static const struct amba_id etm4_ids[] = { ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */ ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */ ETM4x_AMBA_ID(0x000bb9da), /* Cortex-A35 */ + ETM4x_AMBA_ID(0x000f0211), /* Qualcomm Kryo */ + ETM4x_AMBA_ID(0x000f0205), /* Qualcomm Kryo */ + ETM4x_AMBA_ID(0x000bb803), /* Qualcomm Kryo 385Cortex-A75 */
+ETM4x_AMBA_ID(0x000bb802), /* Qualcomm Kryo 385
Cortex-A55 */
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{},That looks fine with me. But as Mathieu said, this needs to be a separate patch. But before all that please could you provide me the PIDR4 value for the Kryo A75 and A55 please ?
Kind regards
Suzuki
Re: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
In reply to Sai Prakash RanjanQuoted 7 lines · Sai Prakash Ranjan
Quoted 1 line · Mathieu Poirier
What version of the Kryo CPU?
There is no Kryo version for MSM8996 (its only given as Kryo), MSM8998 onwards we have Kryo versions like Kryo 280 and so on. Hence I skipped for this one and added the version for SDM845.
Speaking of MSM8998 (aka SDM835) ... could you take a stab at adding coresight support for that platform as well? ^_^
Regards.
Re: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
In reply to Sai Prakash RanjanGood day Sai,
Quoted 7 lines · Sai Prakash Ranjan
Hi Mathieu,
Quoted 3 lines · Mathieu Poirier
On Wed, 23 Jan 2019 at 05:12, Sai Prakash Ranjan
<[email protected]> wrote:
Quoted 8 lines
Quoted 3 lines
That depends on whether the ETMs have been modified at all, something Suzuki has asked to be clarified. If ETMs have been modified then we need to understand how they differ from the driver's implementation.
We had asked hardware team for clarification regarding this. Let me poke them again. As for the driver, downstream implementation also uses the same driver, so I am not sure what do you mean by differing from the driver's implementation.
The driver has been implemented in accordance to ARM's coresight technical reference manual and expects the HW to behave in accordance to that specification. Here we want to make sure the IP on your board is conformant to the same specification. If not then the driver needs to be made flexible to handle both kind IPs.
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If the implementations are the same:
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Review static const struct amba_id etm4_ids[] = { · line 1083
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(quoted diff) +2
-0@@ -1079,6 +1079,10 @@ static const struct amba_id etm4_ids[] = { ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */ ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */ ETM4x_AMBA_ID(0x000bb9da), /* Cortex-A35 */ + ETM4x_AMBA_ID(0x000f0211), /* Qualcomm Kryo */ + ETM4x_AMBA_ID(0x000f0205), /* Qualcomm Kryo */What version of the Kryo CPU? And the above will need to be in a separate patch with the modifications to address the problem you mentionned below.
Quoted 3 lines
There is no Kryo version for MSM8996 (its only given as Kryo), MSM8998 onwards we have Kryo versions like Kryo 280 and so on. Hence I skipped for this one and added the version for SDM845.
Very well.
Mathieu
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(quoted diff) +1
-0+ ETM4x_AMBA_ID(0x000bb803), /* Qualcomm Kryo 385Cortex-A75 */
+ETM4x_AMBA_ID(0x000bb802), /* Qualcomm Kryo 385
Cortex-A55 */Please add them in chronological order.
Sure, will do it.
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{},};
For msm8996, cpu debug module pid returned is same as ETM which is causing the probe failure for cpu debug coresight module as shown in below logs.
For this case, I tried adding these ids to cpu debug driver, but it splits some errors (coresight-cpu-debug: probe of 3840000.etm failed with error -16) since the ids are same. Can we override for this case or there is something else we can do here?Quoted 5 lines
That is another problem. See this patchset [1] from Mike Leach for a description of the problem and how to fix it.
Thanks a lot for this link. I will check this out.
- Sai
--
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Re: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
In reply to Suzuki K PouloseHi Suzuki,
Quoted 7 lines · Suzuki K Poulose
Hi Sai,
That looks fine with me. But as Mathieu said, this needs to be a separate patch. But before all that please could you provide me the PIDR4 value for the Kryo A75 and A55 please ?
Sure.
PIDR4 value is 0x4.
I get it now. So we are looking for JEP106 identification(PIDR1[7:4] and PIDR2[2:0]) and continuation code(PIDR4[3:0]).
From ARM Coresight Spec:
DES_0, PIDR1 bits[7:4] JEP106 identification code bits[3:0]. DES_1, PIDR2 bits[2:0] JEP106 identification code bits[6:4]. DES_2, PIDR4 bits[3:0] JEP106 continuation code.
For SDM845(A75 based):
*0xB_B8_03* does indicate that the JEP106 identification code is 0x3B and continuation code is 0x4 which is of ARM and not QCOM(JEP106 ID is 0x70) which is expected.
And the other values of PIDR0[0:7] and PIDR1[3:0] are *Implementation defined part numbers* and can be different from ARM A75/A55.
I think this clears up case for SDM845.
As for MSM8996, it is not based on any ARM derivative and hence the JEP106 ID is of QCOM(0x70) from the value of pid = *0xF_02_11* based on PIDR1[7:4] and PIDR2[2:0]. This clears this as well.
Please correct me if I am wrong and also let me know if I can continue with PID addition to table.
Thanks,
Sai
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Re: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
In reply to Marc GonzalezQuoted 6 lines · Marc Gonzalez
Quoted 4 lines · Sai Prakash Ranjan
Quoted 1 line · Mathieu Poirier
What version of the Kryo CPU?
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There is no Kryo version for MSM8996 (its only given as Kryo), MSM8998 onwards we have Kryo versions like Kryo 280 and so on. Hence I skipped for this one and added the version for SDM845.
Speaking of MSM8998 (aka SDM835) ... could you take a stab at adding coresight support for that platform as well? ^_^
Regards.
Sure Marc, I can do it on the next spin probably.
- Sai
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Re: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
In reply to Mathieu PoirierGood day Mathieu,
Quoted 20 lines · Mathieu Poirier
Good day Sai,
Quoted 7 lines · Sai Prakash Ranjan
Hi Mathieu,
Quoted 3 lines · Mathieu Poirier
On Wed, 23 Jan 2019 at 05:12, Sai Prakash Ranjan
<[email protected]> wrote:Quoted 8 lines
Quoted 3 lines
That depends on whether the ETMs have been modified at all, something Suzuki has asked to be clarified. If ETMs have been modified then we need to understand how they differ from the driver's implementation.
We had asked hardware team for clarification regarding this. Let me poke them again. As for the driver, downstream implementation also uses the same driver, so I am not sure what do you mean by differing from the driver's implementation.
Quoted 6 lines
The driver has been implemented in accordance to ARM's coresight technical reference manual and expects the HW to behave in accordance to that specification. Here we want to make sure the IP on your board is conformant to the same specification. If not then the driver needs to be made flexible to handle both kind IPs.
The HW does behave as per the specification. As discussed in reply to
Suzuki, Coresight peripherals do use JEP106 ID of ARM for SDM845 and for MSM8996, the ID is of QCOM(0x70) since it was not based on any ARM derivative. And the etm4x driver handles it all well. Other values of PID registers
are implementation defined and can be different from standard ARM cpu
core types.
Thanks,
Sai
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Re: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
In reply to Sai Prakash RanjanQuoted 34 lines · Sai Prakash Ranjan
Hi Suzuki,
Quoted 7 lines · Suzuki K Poulose
Hi Sai,
That looks fine with me. But as Mathieu said, this needs to be a separate patch. But before all that please could you provide me the PIDR4 value for the Kryo A75 and A55 please ?
Sure.
PIDR4 value is
0x4.I get it now. So we are looking for JEP106
identification(PIDR1[7:4] and PIDR2[2:0])and continuationcode(PIDR4[3:0]).From ARM Coresight Spec:
DES_0, PIDR1 bits[7:4] JEP106 identification code bits[3:0].DES_1, PIDR2 bits[2:0] JEP106 identification code bits[6:4].DES_2, PIDR4 bits[3:0] JEP106 continuation code.For SDM845(A75 based):
*0xB_B8_03* does indicate that the JEP106 identification code is
0x3Band continuation code is0x4which is of ARM and not QCOM(JEP106 ID is0x70) which is expected.And the other values of PIDR0[0:7] and PIDR1[3:0] are *Implementation defined part numbers* and can be different from ARM A75/A55.
Quoted 8 lines
I think this clears up case for SDM845.
As for MSM8996, it is not based on any ARM derivative and hence the JEP106 ID is of QCOM(0x70) from the value of pid = *0xF_02_11* based on PIDR1[7:4] and PIDR2[2:0]. This clears this as well.
Please correct me if I am wrong and also let me know if I can continue with PID addition to table.
Please proceed.
Quoted 7 lines
Thanks,
Sai--
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Re: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
Quoted 11 lines · Mathieu Poirier
Quoted 11 lines
For SDM845(A75 based):
*0xB_B8_03* does indicate that the JEP106 identification code is
0x3Band continuation code is0x4which is of ARM and not QCOM(JEP106 ID is0x70) which is expected.And the other values of PIDR0[0:7] and PIDR1[3:0] are *Implementation defined part numbers* and can be different from ARM A75/A55.
I think this clears up case for SDM845.
Quoted 9 lines
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As for MSM8996, it is not based on any ARM derivative and hence the JEP106 ID is of QCOM(0x70) from the value of pid = *0xF_02_11* based on PIDR1[7:4] and PIDR2[2:0]. This clears this as well.
Please correct me if I am wrong and also let me know if I can continue with PID addition to table.
Please proceed.
Thanks Mathieu, posted the next version now.
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