Add coresight support for SDM845, MSM8998 and MSM8996
Subsystems (5)
v6 cover Add coresight support for SDM845, MSM8998 and MSM8996
This patch series adds support for coresight on SDM845, MSM8998, and MSM8996.
* Patch 1 adds device tree nodes for SDM845 coresight components.
* Patch 2 adds device tree nodes for MSM8998 coresight components.
* Patch 3 adds device tree nodes for MSM8996 coresight components.
* Patch 4 enables support for ETMv4.2 and enables SDM845 to make use of same driver(etm4x).
* Patch 5 adds ETM PIDs for SDM845 and MSM8996.
* Patch 6 adds UCI table for coresight CPU debug module.
NOTE: All the dependent patches are applied in the below tree,
the first 12 commits represent the dependent patches.
* https://github.com/saiprakash-ranjan/linux/tree/coresight-next
Patch 1 and 4 depends on below AOSS QMP, AMBA bus pclk and address cell change:
* https://lore.kernel.org/lkml/[email protected]/
* https://lore.kernel.org/lkml/[email protected]/
* https://lore.kernel.org/lkml/[email protected]/
* https://lore.kernel.org/lkml/[email protected]/
* https://lore.kernel.org/lkml/[email protected]/
* https://lore.kernel.org/lkml/[email protected]/
Patch 2 depends on MSM8998 rpm clocks and rpmcc nodes:
* https://lore.kernel.org/lkml/[email protected]/
* https://lore.kernel.org/lkml/[email protected]/
* https://lore.kernel.org/lkml/[email protected]/
Patch 5 and 6 depends on UCI support by Mike Leach:
* https://lore.kernel.org/lkml/[email protected]/
This patch series has been tested on SDM845 MTP and MSM8996 based Dragonboard 820c and MSM8998 MTP.
v6:
* Update the UCI table with the new macro introduced by Mike.
* Rebase on top of coresight-next and provide a tree with all the dependent patches applied.
v5:
* Added coresight support for MSM8998.
* Added ETM PIDs for SDM845 and MSM8996 as suggested by Suzuki.
* Added UCI table for Coresight CPU debug module.
v4:
* Mask out the minor version as suggested by Mathieu.
* Added the dependent patch description in patch 1.
v3:
* Added arm,scatter-gather property as suggested by Suzuki.
v2:
* Added coresight support for msm8996 based on Vivek's patch. Cleaned up and added coresight cpu debug nodes for msm8996.
* Merged coresight dtsi file into sdm845.dtsi as suggested by Bjorn
* Addressed Mathieu's feedback about masking the minor version in etm4_arch_supported() and added a comment for reason to bypass the AMBA bus discovery method.
Sai Prakash Ranjan (5):
arm64: dts: qcom: sdm845: Add Coresight support
arm64: dts: qcom: msm8998: Add Coresight support
coresight: etm4x: Add support to enable ETMv4.2
coresight: etm4x: Add ETM PIDs for SDM845 and MSM8996
coresight: debug: Add Unique Component Identifier (UCI) table
Vivek Gautam (1):
arm64: dts: qcom: msm8996: Add Coresight support
arch/arm64/boot/dts/qcom/msm8996.dtsi | 434 +++++++++++++++++ arch/arm64/boot/dts/qcom/msm8998.dtsi | 435 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 434 +++++++++++++++++ .../hwtracing/coresight/coresight-cpu-debug.c | 33 +- drivers/hwtracing/coresight/coresight-etm4x.c | 17 +- 5 files changed, 1330 insertions(+), 23 deletions(-)
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v6 1/6 arm64: dts: qcom: sdm845: Add Coresight support
Add coresight components found on Qualcomm SDM845 SoC.
---
For testing, all dependent patches are in below tree:
* https://github.com/saiprakash-ranjan/linux/tree/coresight-next
- Depends on AOSS QMP side channel patches by Bjorn Andersson [1] - [4].
- AMBA bus pclk change [5].
- Also depends on patch ("arm64: dts: qcom: sdm845: Increase address and size cells for soc") [6].
[1] https://lore.kernel.org/lkml/[email protected]/
[2] https://lore.kernel.org/lkml/[email protected]/
[3] https://lore.kernel.org/lkml/[email protected]/
[4] https://lore.kernel.org/lkml/[email protected]/
[5] https://lore.kernel.org/lkml/[email protected]/
[6] https://lore.kernel.org/lkml/[email protected]/
--- arch/arm64/boot/dts/qcom/sdm845.dtsi | 434 +++++++++++++++++++++++++++ 1 file changed, 434 insertions(+)
arch/arm64/boot/dts/qcom/sdm845.dtsi +434 -0
@@ -1349,6 +1349,440 @@ }; }; + stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x06002000 0 0x1000>, + <0 0x16280000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = + <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x06041000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@6043000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x06043000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + funnel2_out: endpoint { + remote-endpoint = + <&merge_funnel_in2>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + funnel2_in5: endpoint { + remote-endpoint = + <&apss_merge_funnel_out>; + }; + }; + }; + }; + + funnel@6045000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x06045000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@2 { + reg = <2>; + merge_funnel_in2: endpoint { + remote-endpoint = + <&funnel2_out>; + }; + }; + }; + }; + + replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06046000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf@6047000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06047000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + etf_in: endpoint { + remote-endpoint = + <&merge_funnel_out>; + }; + }; + }; + }; + + etr@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06048000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = + <&replicator_out>; + }; + }; + }; + }; + + etm@7040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07040000 0 0x1000>; + + cpu = <&CPU0>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07140000 0 0x1000>; + + cpu = <&CPU1>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07240000 0 0x1000>; + + cpu = <&CPU2>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07340000 0 0x1000>; + + cpu = <&CPU3>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel_in3>; + }; + }; + }; + }; + + etm@7440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07440000 0 0x1000>; + + cpu = <&CPU4>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&apss_funnel_in4>; + }; + }; + }; + }; + + etm@7540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07540000 0 0x1000>; + + cpu = <&CPU5>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&apss_funnel_in5>; + }; + }; + }; + }; + + etm@7640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07640000 0 0x1000>; + + cpu = <&CPU6>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&apss_funnel_in6>; + }; + }; + }; + }; + + etm@7740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07740000 0 0x1000>; + + cpu = <&CPU7>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&apss_funnel_in7>; + }; + }; + }; + }; + + funnel@7800000 { /* APSS Funnel */ + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x07800000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel_in0: endpoint { + remote-endpoint = + <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel_in1: endpoint { + remote-endpoint = + <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel_in2: endpoint { + remote-endpoint = + <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel_in3: endpoint { + remote-endpoint = + <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel_in4: endpoint { + remote-endpoint = + <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel_in5: endpoint { + remote-endpoint = + <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel_in6: endpoint { + remote-endpoint = + <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel_in7: endpoint { + remote-endpoint = + <&etm7_out>; + }; + }; + }; + }; + + funnel@7810000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x07810000 0 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = + <&funnel2_in5>; + }; + }; + }; + + in-ports { + port { + apss_merge_funnel_in: endpoint { + remote-endpoint = + <&apss_funnel_out>; + }; + }; + }; + }; + usb_1_hsphy: phy@88e2000 { compatible = "qcom,sdm845-qusb2-phy"; reg = <0 0x088e2000 0 0x400>;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v6 2/6 arm64: dts: qcom: msm8998: Add Coresight support
In reply to Sai Prakash RanjanEnable coresight support by adding device nodes for the available source, sinks and channel blocks on MSM8998.
---
For testing, all dependent patches are in below tree:
* https://github.com/saiprakash-ranjan/linux/tree/coresight-next
This depends on MSM8998 rpm clocks and rpmcc node by Jeffrey Hugo and Marc Gonzalez [1][2][3].
[1] https://lore.kernel.org/lkml/[email protected]/
[2] https://lore.kernel.org/lkml/[email protected]/
[3] https://lore.kernel.org/lkml/[email protected]/
--- arch/arm64/boot/dts/qcom/msm8998.dtsi | 435 ++++++++++++++++++++++++++ 1 file changed, 435 insertions(+)
arch/arm64/boot/dts/qcom/msm8998.dtsi +435 -0
@@ -566,6 +566,441 @@ #interrupt-cells = <0x2>; }; + stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x06002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x06041000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@6042000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x06042000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = + <&merge_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + funnel1_in6: endpoint { + remote-endpoint = + <&apss_merge_funnel_out>; + }; + }; + }; + }; + + funnel@6045000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x06045000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = + <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = + <&funnel1_out>; + }; + }; + }; + }; + + replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x06046000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf@6047000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x06047000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = + <&merge_funnel_out>; + }; + }; + }; + }; + + etr@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x06048000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = + <&replicator_out>; + }; + }; + }; + }; + + etm@7840000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07840000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU0>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7940000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07940000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU1>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7a40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07a40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU2>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7b40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07b40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU3>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel_in3>; + }; + }; + }; + }; + + funnel@7b60000 { /* APSS Funnel */ + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07b60000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel_in0: endpoint { + remote-endpoint = + <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel_in1: endpoint { + remote-endpoint = + <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel_in2: endpoint { + remote-endpoint = + <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel_in3: endpoint { + remote-endpoint = + <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel_in4: endpoint { + remote-endpoint = + <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel_in5: endpoint { + remote-endpoint = + <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel_in6: endpoint { + remote-endpoint = + <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel_in7: endpoint { + remote-endpoint = + <&etm7_out>; + }; + }; + }; + }; + + funnel@7b70000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x07b70000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = + <&funnel1_in6>; + }; + }; + }; + + in-ports { + port { + apss_merge_funnel_in: endpoint { + remote-endpoint = + <&apss_funnel_out>; + }; + }; + }; + }; + + etm@7c40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07c40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU4>; + + port{ + etm4_out: endpoint { + remote-endpoint = <&apss_funnel_in4>; + }; + }; + }; + + etm@7d40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07d40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU5>; + + port{ + etm5_out: endpoint { + remote-endpoint = <&apss_funnel_in5>; + }; + }; + }; + + etm@7e40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07e40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU6>; + + port{ + etm6_out: endpoint { + remote-endpoint = <&apss_funnel_in6>; + }; + }; + }; + + etm@7f40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07f40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU7>; + + port{ + etm7_out: endpoint { + remote-endpoint = <&apss_funnel_in7>; + }; + }; + }; + spmi_bus: spmi@800f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x800f000 0x1000>,
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v6 3/6 arm64: dts: qcom: msm8996: Add Coresight support
In reply to Sai Prakash RanjanFrom: Vivek Gautam <[email protected]>
Enable coresight support by adding device nodes for the available source, sinks and channel blocks on msm8996.
This also adds coresight cpu debug nodes.
--- arch/arm64/boot/dts/qcom/msm8996.dtsi | 434 ++++++++++++++++++++++++++ 1 file changed, 434 insertions(+)
arch/arm64/boot/dts/qcom/msm8996.dtsi +434 -0
@@ -429,6 +429,440 @@ reg = <0x300000 0x90000>; }; + stm@3002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x3002000 0x1000>, + <0x8280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = + <&funnel0_in>; + }; + }; + }; + }; + + tpiu@3020000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x3020000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + tpiu_in: endpoint { + remote-endpoint = + <&replicator_out1>; + }; + }; + }; + }; + + funnel@3021000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x3021000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + funnel0_in: endpoint { + remote-endpoint = + <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&merge_funnel_in0>; + }; + }; + }; + }; + + funnel@3022000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x3022000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + funnel1_in: endpoint { + remote-endpoint = + <&apss_merge_funnel_out>; + }; + }; + }; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = + <&merge_funnel_in1>; + }; + }; + }; + }; + + funnel@3025000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x3025000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = + <&funnel1_out>; + }; + }; + }; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = + <&etf_in>; + }; + }; + }; + }; + + replicator@3026000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x3026000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = + <&etf_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = + <&etr_in>; + }; + }; + + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = + <&tpiu_in>; + }; + }; + }; + }; + + etf@3027000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x3027000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = + <&merge_funnel_out>; + }; + }; + }; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + }; + + etr@3028000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x3028000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = + <&replicator_out0>; + }; + }; + }; + }; + + debug@3810000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3810000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU0>; + }; + + etm@3840000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3840000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU0>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel0_in0>; + }; + }; + }; + }; + + debug@3910000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3910000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + }; + + etm@3940000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3940000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU1>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel0_in1>; + }; + }; + }; + }; + + funnel@39b0000 { /* APSS Funnel 0 */ + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x39b0000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel0_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel0_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + }; + + out-ports { + port { + apss_funnel0_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in0>; + }; + }; + }; + }; + + debug@3a10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3a10000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU2>; + }; + + etm@3a40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3a40000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU2>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel1_in0>; + }; + }; + }; + }; + + debug@3b10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3b10000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + }; + + etm@3b40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3b40000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU3>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel1_in1>; + }; + }; + }; + }; + + funnel@3bb0000 { /* APSS Funnel 1 */ + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x3bb0000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel1_in0: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel1_in1: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + + out-ports { + port { + apss_funnel1_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in1>; + }; + }; + }; + }; + + funnel@3bc0000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x3bc0000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_merge_funnel_in0: endpoint { + remote-endpoint = + <&apss_funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_merge_funnel_in1: endpoint { + remote-endpoint = + <&apss_funnel1_out>; + }; + }; + }; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = + <&funnel1_in>; + }; + }; + }; + }; + kryocc: clock-controller@6400000 { compatible = "qcom,apcc-msm8996"; reg = <0x6400000 0x90000>;
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QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v6 4/6 coresight: etm4x: Add support to enable ETMv4.2
In reply to Sai Prakash RanjanSDM845 has ETMv4.2 and can use the existing etm4x driver. But the current etm driver checks only for ETMv4.0 and errors out for other etm4x versions. This patch adds this missing support to enable SoC's with ETMv4x to use same driver by checking only the ETM architecture major version number.
Without this change, we get below error during etm probe:
/ # dmesg | grep etm
[ 6.660093] coresight-etm4x: probe of 7040000.etm failed with error -22 [ 6.666902] coresight-etm4x: probe of 7140000.etm failed with error -22 [ 6.673708] coresight-etm4x: probe of 7240000.etm failed with error -22 [ 6.680511] coresight-etm4x: probe of 7340000.etm failed with error -22 [ 6.687313] coresight-etm4x: probe of 7440000.etm failed with error -22 [ 6.694113] coresight-etm4x: probe of 7540000.etm failed with error -22 [ 6.700914] coresight-etm4x: probe of 7640000.etm failed with error -22 [ 6.707717] coresight-etm4x: probe of 7740000.etm failed with error -22
With this change, etm probe is successful:
/ # dmesg | grep etm
[ 6.659198] coresight-etm4x 7040000.etm: CPU0: ETM v4.2 initialized [ 6.665848] coresight-etm4x 7140000.etm: CPU1: ETM v4.2 initialized [ 6.672493] coresight-etm4x 7240000.etm: CPU2: ETM v4.2 initialized [ 6.679129] coresight-etm4x 7340000.etm: CPU3: ETM v4.2 initialized [ 6.685770] coresight-etm4x 7440000.etm: CPU4: ETM v4.2 initialized [ 6.692403] coresight-etm4x 7540000.etm: CPU5: ETM v4.2 initialized [ 6.699024] coresight-etm4x 7640000.etm: CPU6: ETM v4.2 initialized [ 6.705646] coresight-etm4x 7740000.etm: CPU7: ETM v4.2 initialized
--- drivers/hwtracing/coresight/coresight-etm4x.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/hwtracing/coresight/coresight-etm4x.c +2 -1
@@ -55,7 +55,8 @@ static void etm4_os_unlock(struct etmv4_drvdata *drvdata)static bool etm4_arch_supported (u8 arch) { -switch (arch) { +/* Mask out the minor version number */ +switch (arch &0xf0 ) {case ETM_ARCH_V4 :break ;default :
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v6 5/6 coresight: etm4x: Add ETM PIDs for SDM845 and MSM8996
In reply to Sai Prakash RanjanInstead of overriding the peripheral id(PID) check in AMBA by hardcoding them in DT, add the PIDs to the ETM4x driver. Here we use Unique Component Identifier(UCI) for MSM8996 since the ETM and CPU debug module shares the same PIDs. SDM845 does not support CPU debug module.
---
For testing, all dependent patches are in below tree:
* https://github.com/saiprakash-ranjan/linux/tree/coresight-next
This patch depends on UCI support by Mike Leach in below link:
* https://lore.kernel.org/lkml/[email protected]/
--- drivers/hwtracing/coresight/coresight-etm4x.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)
drivers/hwtracing/coresight/coresight-etm4x.c +9 -5
@@ -1078,11 +1078,15 @@ static struct amba_cs_uci_id uci_id_etm4[] = { };static const struct amba_id etm4_ids[] = { -CS_AMBA_ID (0x000bb95d ),/* Cortex-A53 */ -CS_AMBA_ID (0x000bb95e ),/* Cortex-A57 */ -CS_AMBA_ID (0x000bb95a ),/* Cortex-A72 */ -CS_AMBA_ID (0x000bb959 ),/* Cortex-A73 */ -CS_AMBA_UCI_ID (0x000bb9da , uci_id_etm4),/* Cortex-A35 */ +CS_AMBA_ID (0x000bb95d ),/* Cortex-A53 */ +CS_AMBA_ID (0x000bb95e ),/* Cortex-A57 */ +CS_AMBA_ID (0x000bb95a ),/* Cortex-A72 */ +CS_AMBA_ID (0x000bb959 ),/* Cortex-A73 */ +CS_AMBA_UCI_ID (0x000bb9da , uci_id_etm4),/* Cortex-A35 */ +CS_AMBA_UCI_ID (0x000f0205 , uci_id_etm4),/* Qualcomm Kryo */ +CS_AMBA_UCI_ID (0x000f0211 , uci_id_etm4),/* Qualcomm Kryo */ +CS_AMBA_ID (0x000bb802 ),/* Qualcomm Kryo 385 Cortex-A55 */ +CS_AMBA_ID (0x000bb803 ),/* Qualcomm Kryo 385 Cortex-A75 */ {}, };
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v6 6/6 coresight: debug: Add Unique Component Identifier (UCI) table
In reply to Sai Prakash RanjanAdd UCI table for coresight CPU debug module. This patch adds the UCI entries for Kryo CPUs found on MSM8996 which shares the same PIDs as ETMs.
Without this, below error is observed on MSM8996:
[ 5.429867] OF: graph: no port node found in /soc/debug@3810000 [ 5.429938] coresight-etm4x: probe of 3810000.debug failed with error -22 [ 5.435415] coresight-cpu-debug 3810000.debug: Coresight debug-CPU0 initialized [ 5.446474] OF: graph: no port node found in /soc/debug@3910000 [ 5.448927] coresight-etm4x: probe of 3910000.debug failed with error -22 [ 5.454681] coresight-cpu-debug 3910000.debug: Coresight debug-CPU1 initialized [ 5.487765] OF: graph: no port node found in /soc/debug@3a10000 [ 5.488007] coresight-etm4x: probe of 3a10000.debug failed with error -22 [ 5.493024] coresight-cpu-debug 3a10000.debug: Coresight debug-CPU2 initialized [ 5.501802] OF: graph: no port node found in /soc/debug@3b10000 [ 5.512901] coresight-etm4x: probe of 3b10000.debug failed with error -22 [ 5.513192] coresight-cpu-debug 3b10000.debug: Coresight debug-CPU3 initialized
---
For testing, all dependent patches are in below tree:
* https://github.com/saiprakash-ranjan/linux/tree/coresight-next
This patch depends on UCI support by Mike Leach in below link:
* https://lore.kernel.org/lkml/[email protected]/
--- .../hwtracing/coresight/coresight-cpu-debug.c | 33 +++++++++---------- 1 file changed, 16 insertions(+), 17 deletions(-)
drivers/hwtracing/coresight/coresight-cpu-debug.c +16 -17
@@ -655,24 +655,23 @@ static int debug_remove(struct amba_device *adev)return 0 ; } +static struct amba_cs_uci_id uci_id_debug[] = { + { +/* CPU Debug UCI data */ + .devarch =0x47706a15 , + .devarch_mask =0xfff0ffff , + .devtype =0x00000015 , + } +}; +static const struct amba_id debug_ids[] = { - {/* Debug for Cortex-A53 */ - .id =0x000bbd03 , - .mask =0x000fffff , - }, - {/* Debug for Cortex-A57 */ - .id =0x000bbd07 , - .mask =0x000fffff , - }, - {/* Debug for Cortex-A72 */ - .id =0x000bbd08 , - .mask =0x000fffff , - }, - {/* Debug for Cortex-A73 */ - .id =0x000bbd09 , - .mask =0x000fffff , - }, - {0 ,0 }, +CS_AMBA_ID (0x000bbd03 ),/* Cortex-A53 */ +CS_AMBA_ID (0x000bbd07 ),/* Cortex-A57 */ +CS_AMBA_ID (0x000bbd08 ),/* Cortex-A72 */ +CS_AMBA_ID (0x000bbd09 ),/* Cortex-A73 */ +CS_AMBA_UCI_ID (0x000f0205 , uci_id_debug),/* Qualcomm Kryo */ +CS_AMBA_UCI_ID (0x000f0211 , uci_id_debug),/* Qualcomm Kryo */ + {}, };static struct amba_driver debug_driver = {
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCHv6 6/6] coresight: debug: Add Unique Component Identifier (UCI) table
Quoting Sai Prakash Ranjan (2019-01-31 06:22:24)
drivers/hwtracing/coresight/coresight-cpu-debug.c static int debug_remove(struct amba_device *adev) · line 658
Quoted 9 lines
drivers/hwtracing/coresight/coresight-cpu-debug.c +1
-0@@ -655,24 +655,23 @@ static int debug_remove(struct amba_device *adev)return 0 ; } +static struct amba_cs_uci_id uci_id_debug[] = {
Can this be const?
Quoted 7 lines
drivers/hwtracing/coresight/coresight-cpu-debug.c +7
-0+ { +/* CPU Debug UCI data */ + .devarch = 0x47706a15, + .devarch_mask = 0xfff0ffff, + .devtype = 0x00000015, + } +};
Suzuki K Poulose
maintainerRe: [PATCHv6 6/6] coresight: debug: Add Unique Component Identifier (UCI) table
In reply to Sai Prakash RanjanQuoted 5 lines · Sai Prakash Ranjan
Add UCI table for coresight CPU debug module. This patch adds the UCI entries for Kryo CPUs found on MSM8996 which shares the same PIDs as ETMs.
Without this, below error is observed on MSM8996:
nit: Subject doesn't match the patch contents. You could simply say :
coresight: cpu-debug: Add support for Qualcomm Kryo
Quoted 31 lines
[ 5.429867] OF: graph: no port node found in /soc/debug@3810000 [ 5.429938] coresight-etm4x: probe of 3810000.debug failed with error -22 [ 5.435415] coresight-cpu-debug 3810000.debug: Coresight debug-CPU0 initialized [ 5.446474] OF: graph: no port node found in /soc/debug@3910000 [ 5.448927] coresight-etm4x: probe of 3910000.debug failed with error -22 [ 5.454681] coresight-cpu-debug 3910000.debug: Coresight debug-CPU1 initialized [ 5.487765] OF: graph: no port node found in /soc/debug@3a10000 [ 5.488007] coresight-etm4x: probe of 3a10000.debug failed with error -22 [ 5.493024] coresight-cpu-debug 3a10000.debug: Coresight debug-CPU2 initialized [ 5.501802] OF: graph: no port node found in /soc/debug@3b10000 [ 5.512901] coresight-etm4x: probe of 3b10000.debug failed with error -22 [ 5.513192] coresight-cpu-debug 3b10000.debug: Coresight debug-CPU3 initializedSigned-off-by Sai Prakash Ranjan <[email protected]>---
For testing, all dependent patches are in below tree:
* https://github.com/saiprakash-ranjan/linux/tree/coresight-nextThis patch depends on UCI support by Mike Leach in below link:
* https://lore.kernel.org/lkml/[email protected]/--- .../hwtracing/coresight/coresight-cpu-debug.c | 33 +++++++++---------- 1 file changed, 16 insertions(+), 17 deletions(-)drivers/hwtracing/coresight/coresight-cpu-debug.c +0
-0
drivers/hwtracing/coresight/coresight-cpu-debug.c static int debug_remove(struct amba_device *adev) · line 658
Quoted 4 lines
drivers/hwtracing/coresight/coresight-cpu-debug.c +1
-0@@ -655,24 +655,23 @@ static int debug_remove(struct amba_device *adev)return 0 ; } +static struct amba_cs_uci_id uci_id_debug[] = {
As Stephen mentioned, this must be "const".
Rest looks fine.
Suzuki
Re: [PATCHv6 6/6] coresight: debug: Add Unique Component Identifier (UCI) table
In reply to Stephen BoydQuoted 9 lines · Stephen Boyd
Quoting Sai Prakash Ranjan (2019-01-31 06:22:24)
Quoted 8 lines
drivers/hwtracing/coresight/coresight-cpu-debug.c +0
-0@@ -655,24 +655,23 @@ static int debug_remove(struct amba_device *adev)return 0 ; }
Quoted 11 lines
drivers/hwtracing/coresight/coresight-cpu-debug.c static int debug_remove(struct amba_device *adev) · line 658
Quoted 1 line
drivers/hwtracing/coresight/coresight-cpu-debug.c +1
-0+static struct amba_cs_uci_id uci_id_debug[] = {Can this be const?
Quoted 7 lines
drivers/hwtracing/coresight/coresight-cpu-debug.c +7
-0+ { +/* CPU Debug UCI data */ + .devarch = 0x47706a15, + .devarch_mask = 0xfff0ffff, + .devtype = 0x00000015, + } +};
Yes and done in next version, thanks.
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCHv6 6/6] coresight: debug: Add Unique Component Identifier (UCI) table
In reply to Suzuki K PouloseQuoted 7 lines · Suzuki K Poulose
Quoted 4 lines · Sai Prakash Ranjan
Add UCI table for coresight CPU debug module. This patch adds the UCI entries for Kryo CPUs found on MSM8996 which shares the same PIDs as ETMs.
Quoted 6 lines
Quoted 1 line
Without this, below error is observed on MSM8996:
nit: Subject doesn't match the patch contents. You could simply say :
coresight: cpu-debug: Add support for Qualcomm Kryo
Done.
Quoted 12 lines
drivers/hwtracing/coresight/coresight-cpu-debug.c static int debug_remove(struct amba_device *adev) · line 657
Quoted 9 lines
drivers/hwtracing/coresight/coresight-cpu-debug.c +1
-0@@ -655,24 +655,23 @@ static int debug_remove(struct amba_device *adev) return 0; } +static struct amba_cs_uci_id uci_id_debug[] = {As Stephen mentioned, this must be "const".
Quoted 1 line
Rest looks fine.
Done.
Thanks,
Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCHv6 6/6] coresight: debug: Add Unique Component Identifier (UCI) table
Quoted 29 lines · Sai Prakash Ranjan
Quoted 7 lines · Suzuki K Poulose
Quoted 4 lines · Sai Prakash Ranjan
Add UCI table for coresight CPU debug module. This patch adds the UCI entries for Kryo CPUs found on MSM8996 which shares the same PIDs as ETMs.
Quoted 6 lines
Quoted 1 line
Without this, below error is observed on MSM8996:
nit: Subject doesn't match the patch contents. You could simply say :
coresight: cpu-debug: Add support for Qualcomm Kryo
Done.
Quoted 12 lines
drivers/hwtracing/coresight/coresight-cpu-debug.c static int debug_remove(struct amba_device *adev) · line 657
Quoted 9 lines
drivers/hwtracing/coresight/coresight-cpu-debug.c +1
-0@@ -655,24 +655,23 @@ static int debug_remove(struct amba_device *adev) return 0; } +static struct amba_cs_uci_id uci_id_debug[] = {As Stephen mentioned, this must be "const".
Quoted 4 lines
Quoted 1 line
Rest looks fine.
Done.
Also it should be changed in Mike's patch I suppose or else:
In file included from drivers/hwtracing/coresight/coresight-cpu-debug.c:26:0:drivers/hwtracing/coresight/coresight-cpu-debug.c:672:29: warning: initialization discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
CS_AMBA_UCI_ID(0x000f0205, uci_id_debug), /* Qualcomm Kryo */
^
drivers/hwtracing/coresight/coresight-priv.h:192:11: note: in definition of macro ‘CS_AMBA_UCI_ID’
.data = uci_ptr \
^~~~~~~
drivers/hwtracing/coresight/coresight-cpu-debug.c:673:29: warning: initialization discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
CS_AMBA_UCI_ID(0x000f0211, uci_id_debug), /* Qualcomm Kryo */
^
drivers/hwtracing/coresight/coresight-priv.h:192:11: note: in definition of macro ‘CS_AMBA_UCI_ID’
.data = uci_ptr \
^~~~~~~Signature · 2 lines
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