Convert period and duty cycle to u64

PATCH Superseded Guru Das Srinagesh 2 participants 3 messages Nov 15, 2019

Subsystems (12)

DRM drivers Media (V4L/DVB) Arm i.MX and Layerscape Intel i915 +8 more subsystems

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Guru Das Srinagesh

author

2019-11-15 09:21 UTC #0 lore raw

v2 cover Convert period and duty cycle to u64

Reworked the change pushed upstream earlier [1] so as to not add an extension to an obsolete API. With this change, pwm_ops->apply() can be used to set pwm_state parameters as usual.

[1] https://lore.kernel.org/lkml/20190916140048.GB7488@ulmo/

Changes from v1:
- Fixed compilation errors seen when compiling for different archs.

Guru Das Srinagesh (1):
pwm: Convert period and duty cycle to u64

 drivers/clk/clk-pwm.c                      |  2 +-
 drivers/gpu/drm/i915/display/intel_panel.c |  2 +-
 drivers/hwmon/pwm-fan.c                    |  2 +-
 drivers/media/rc/ir-rx51.c                 |  3 ++-
 drivers/pwm/core.c                         |  4 ++--
 drivers/pwm/pwm-clps711x.c                 |  2 +-
 drivers/pwm/pwm-imx27.c                    |  5 ++---
 drivers/pwm/pwm-sti.c                      |  4 ++--
 drivers/pwm/pwm-sun4i.c                    |  2 +-
 drivers/pwm/sysfs.c                        | 10 +++++-----
 drivers/video/backlight/pwm_bl.c           |  3 ++-
 include/linux/pwm.h                        | 16 ++++++++--------
 12 files changed, 28 insertions(+), 27 deletions(-)

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Guru Das Srinagesh

author

2019-11-15 09:21 UTC #1 lore raw

PATCH v2 1/1 pwm: Convert period and duty cycle to u64

Because period and duty cycle are defined as ints with units of nanoseconds, the maximum time duration that can be set is limited to ~2.147 seconds. Change their definitions to u64 in the structs of the PWM framework so that higher durations may be set.

Also make the relevant fixes to those drivers that use the period and duty_cycle struct members in division operations, viz. replacing the division operations with 64-bit division macros as appropriate.

Signed-off-by Guru Das Srinagesh <[email protected]>

---
 drivers/clk/clk-pwm.c                      |  2 +-
 drivers/gpu/drm/i915/display/intel_panel.c |  2 +-
 drivers/hwmon/pwm-fan.c                    |  2 +-
 drivers/media/rc/ir-rx51.c                 |  3 ++-
 drivers/pwm/core.c                         |  4 ++--
 drivers/pwm/pwm-clps711x.c                 |  2 +-
 drivers/pwm/pwm-imx27.c                    |  5 ++---
 drivers/pwm/pwm-sti.c                      |  4 ++--
 drivers/pwm/pwm-sun4i.c                    |  2 +-
 drivers/pwm/sysfs.c                        | 10 +++++-----
 drivers/video/backlight/pwm_bl.c           |  3 ++-
 include/linux/pwm.h                        | 16 ++++++++--------
 12 files changed, 28 insertions(+), 27 deletions(-)

drivers/clk/clk-pwm.c +1 -1

index 87fe0b0e..7b1f7a0 100644
@@ -89,7 +89,7 @@ static int clk_pwm_probe(struct platform_device *pdev)
 	}
 
 	if (of_property_read_u32(node, "clock-frequency", &clk_pwm->fixed_rate))
-		clk_pwm->fixed_rate = NSEC_PER_SEC / pargs.period;
+		clk_pwm->fixed_rate = div64_u64(NSEC_PER_SEC, pargs.period);
 
 	if (pargs.period != NSEC_PER_SEC / clk_pwm->fixed_rate &&
 	    pargs.period != DIV_ROUND_UP(NSEC_PER_SEC, clk_pwm->fixed_rate)) {

drivers/gpu/drm/i915/display/intel_panel.c +1 -1

index bc14e9c..ca373b8 100644
@@ -1868,7 +1868,7 @@ static int pwm_setup_backlight(struct intel_connector *connector,
 
 	panel->backlight.min = 0; /* 0% */
 	panel->backlight.max = 100; /* 100% */
-	panel->backlight.level = DIV_ROUND_UP(
+	panel->backlight.level = DIV64_U64_ROUND_UP(
 				 pwm_get_duty_cycle(panel->backlight.pwm) * 100,
 				 CRC_PMIC_PWM_PERIOD_NS);
 	panel->backlight.enabled = panel->backlight.level != 0;

drivers/hwmon/pwm-fan.c +1 -1

index 42ffd2e..283423a 100644
@@ -437,7 +437,7 @@ static int pwm_fan_resume(struct device *dev)
 		return 0;
 
 	pwm_get_args(ctx->pwm, &pargs);
-	duty = DIV_ROUND_UP(ctx->pwm_value * (pargs.period - 1), MAX_PWM);
+	duty = DIV_ROUND_UP_ULL(ctx->pwm_value * (pargs.period - 1), MAX_PWM);
 	ret = pwm_config(ctx->pwm, duty, pargs.period);
 	if (ret)
 		return ret;

drivers/media/rc/ir-rx51.c +2 -1

index 8574eda..9a5dfd7 100644
@@ -241,7 +241,8 @@ static int ir_rx51_probe(struct platform_device *dev)
 	}
 
 	/* Use default, in case userspace does not set the carrier */
-	ir_rx51.freq = DIV_ROUND_CLOSEST(pwm_get_period(pwm), NSEC_PER_SEC);
+	ir_rx51.freq = DIV_ROUND_CLOSEST_ULL(pwm_get_period(pwm),
+			NSEC_PER_SEC);
 	pwm_put(pwm);
 
 	hrtimer_init(&ir_rx51.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);

drivers/pwm/core.c +2 -2

index f877e77..0789371 100644
@@ -1156,8 +1156,8 @@ static void pwm_dbg_show(struct pwm_chip *chip, struct seq_file *s)
 		if (state.enabled)
 			seq_puts(s, " enabled");
 
-		seq_printf(s, " period: %u ns", state.period);
-		seq_printf(s, " duty: %u ns", state.duty_cycle);
+		seq_printf(s, " period: %llu ns", state.period);
+		seq_printf(s, " duty: %llu ns", state.duty_cycle);
 		seq_printf(s, " polarity: %s",
 			   state.polarity ? "inverse" : "normal");

drivers/pwm/pwm-clps711x.c +1 -1

index 924d39a..ba9500a 100644
@@ -43,7 +43,7 @@ static void clps711x_pwm_update_val(struct clps711x_chip *priv, u32 n, u32 v)
 static unsigned int clps711x_get_duty(struct pwm_device *pwm, unsigned int v)
 {
 	/* Duty cycle 0..15 max */
-	return DIV_ROUND_CLOSEST(v * 0xf, pwm->args.period);
+	return DIV64_U64_ROUND_CLOSEST(v * 0xf, pwm->args.period);
 }
 
 static int clps711x_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)

drivers/pwm/pwm-imx27.c +2 -3

index ae11d85..b4b0fbd 100644
@@ -198,7 +198,7 @@ static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,
 	sr = readl(imx->mmio_base + MX3_PWMSR);
 	fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr);
 	if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
-		period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
+		period_ms = DIV_ROUND_UP_ULL(pwm_get_period(pwm),
 					 NSEC_PER_MSEC);
 		msleep(period_ms);

@@ -231,8 +231,7 @@ static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 
 		period_cycles /= prescale;
 		c = (unsigned long long)period_cycles * state->duty_cycle;
-		do_div(c, state->period);
-		duty_cycles = c;
+		duty_cycles = div64_u64(c, state->period);
 
 		/*
 		 * according to imx pwm RM, the real period value should be

drivers/pwm/pwm-sti.c +2 -2

index 1508616..857f2ad 100644
@@ -371,10 +371,10 @@ static int sti_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
 		effective_ticks = clk_get_rate(pc->cpt_clk);
 
 		result->period = (high + low) * NSEC_PER_SEC;
-		result->period /= effective_ticks;
+		do_div(result->period, effective_ticks);
 
 		result->duty_cycle = high * NSEC_PER_SEC;
-		result->duty_cycle /= effective_ticks;
+		do_div(result->duty_cycle, effective_ticks);
 
 		break;

drivers/pwm/pwm-sun4i.c +1 -1

index 581d232..9b16591 100644
@@ -244,7 +244,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 		val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
 		sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
 		sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
-			usecs_to_jiffies(cstate.period / 1000 + 1);
+			usecs_to_jiffies(div_u64(cstate.period, 1000) + 1);
 		sun4i_pwm->needs_delay[pwm->hwpwm] = true;
 	}

drivers/pwm/sysfs.c +5 -5

index 2389b86..3fb1610 100644
@@ -42,7 +42,7 @@ static ssize_t period_show(struct device *child,
 
 	pwm_get_state(pwm, &state);
 
-	return sprintf(buf, "%u\n", state.period);
+	return sprintf(buf, "%llu\n", state.period);
 }
 
 static ssize_t period_store(struct device *child,

@@ -52,10 +52,10 @@ static ssize_t period_store(struct device *child,
 	struct pwm_export *export = child_to_pwm_export(child);
 	struct pwm_device *pwm = export->pwm;
 	struct pwm_state state;
-	unsigned int val;
+	u64 val;
 	int ret;
 
-	ret = kstrtouint(buf, 0, &val);
+	ret = kstrtou64(buf, 0, &val);
 	if (ret)
 		return ret;

@@ -77,7 +77,7 @@ static ssize_t duty_cycle_show(struct device *child,
 
 	pwm_get_state(pwm, &state);
 
-	return sprintf(buf, "%u\n", state.duty_cycle);
+	return sprintf(buf, "%llu\n", state.duty_cycle);
 }
 
 static ssize_t duty_cycle_store(struct device *child,

@@ -212,7 +212,7 @@ static ssize_t capture_show(struct device *child,
 	if (ret)
 		return ret;
 
-	return sprintf(buf, "%u %u\n", result.period, result.duty_cycle);
+	return sprintf(buf, "%llu %llu\n", result.period, result.duty_cycle);
 }
 
 static DEVICE_ATTR_RW(period);

drivers/video/backlight/pwm_bl.c +2 -1

index 746eebc..c79ea13 100644
@@ -616,7 +616,8 @@ static int pwm_backlight_probe(struct platform_device *pdev)
 		pb->scale = data->max_brightness;
 	}
 
-	pb->lth_brightness = data->lth_brightness * (state.period / pb->scale);
+	pb->lth_brightness = data->lth_brightness * (div_u64(state.period,
+				pb->scale));
 
 	props.type = BACKLIGHT_RAW;
 	props.max_brightness = data->max_brightness;

include/linux/pwm.h +8 -8

index 0ef808d..df83440 100644
@@ -39,7 +39,7 @@ enum pwm_polarity {
  * current PWM hardware state.
  */
 struct pwm_args {
-	unsigned int period;
+	u64 period;
 	enum pwm_polarity polarity;
 };

@@ -56,8 +56,8 @@ enum {
  * @enabled: PWM enabled status
  */
 struct pwm_state {
-	unsigned int period;
-	unsigned int duty_cycle;
+	u64 period;
+	u64 duty_cycle;
 	enum pwm_polarity polarity;
 	bool enabled;
 };

@@ -105,13 +105,13 @@ static inline bool pwm_is_enabled(const struct pwm_device *pwm)
 	return state.enabled;
 }
 
-static inline void pwm_set_period(struct pwm_device *pwm, unsigned int period)
+static inline void pwm_set_period(struct pwm_device *pwm, u64 period)
 {
 	if (pwm)
 		pwm->state.period = period;
 }
 
-static inline unsigned int pwm_get_period(const struct pwm_device *pwm)
+static inline u64 pwm_get_period(const struct pwm_device *pwm)
 {
 	struct pwm_state state;

@@ -126,7 +126,7 @@ static inline void pwm_set_duty_cycle(struct pwm_device *pwm, unsigned int duty)
 		pwm->state.duty_cycle = duty;
 }
 
-static inline unsigned int pwm_get_duty_cycle(const struct pwm_device *pwm)
+static inline u64 pwm_get_duty_cycle(const struct pwm_device *pwm)
 {
 	struct pwm_state state;

@@ -305,8 +305,8 @@ struct pwm_chip {
  * @duty_cycle: duty cycle of the PWM signal (in nanoseconds)
  */
 struct pwm_capture {
-	unsigned int period;
-	unsigned int duty_cycle;
+	u64 period;
+	u64 duty_cycle;
 };
 
 #if IS_ENABLED(CONFIG_PWM)

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

kbuild test robot

build bot

2019-11-15 12:31 UTC #2 lore raw

Re: [PATCH v2 1/1] pwm: Convert period and duty cycle to u64

Thank you for the patch! Perhaps something to improve:

Hi Guru,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on pwm/for-next]
[cannot apply to v5.4-rc7 next-20191114]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Guru-Das-Srinagesh/Convert-period-and-duty-cycle-to-u64/20191115-172357
base:   https://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git for-next
config: sh-allmodconfig (attached as .config)
compiler: sh4-linux-gcc (GCC) 7.4.0

reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=sh

If you fix the issue, kindly add following tag

Reported-by kbuild test robot <[email protected]>

All warnings (new ones prefixed by >>):

In file included from include/linux/printk.h:332:0,

                    from include/linux/kernel.h:15,
                    from include/linux/clk.h:13,
                    from include/linux/mfd/stm32-lptimer.h:12,
                    from drivers//pwm/pwm-stm32-lp.c:13:
   drivers//pwm/pwm-stm32-lp.c: In function 'stm32_pwm_lp_apply':
>> drivers//pwm/pwm-stm32-lp.c:64:27: warning: format '%u' expects argument of type 'unsigned int', but argument 4 has type 'u64 {aka const long long unsigned int}' [-Wformat=]
      dev_dbg(priv->chip.dev, "Can't reach %u ns\n", state->period);
                              ^
   include/linux/dynamic_debug.h:125:15: note: in definition of macro '__dynamic_func_call'
      func(&id, ##__VA_ARGS__);  \
                  ^~~~~~~~~~~
   include/linux/dynamic_debug.h:157:2: note: in expansion of macro '_dynamic_func_call'
     _dynamic_func_call(fmt,__dynamic_dev_dbg,   \
     ^~~~~~~~~~~~~~~~~~
   include/linux/device.h:1751:2: note: in expansion of macro 'dynamic_dev_dbg'
     dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
     ^~~~~~~~~~~~~~~
   include/linux/device.h:1751:23: note: in expansion of macro 'dev_fmt'
     dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
                          ^~~~~~~
>> drivers//pwm/pwm-stm32-lp.c:64:3: note: in expansion of macro 'dev_dbg'
      dev_dbg(priv->chip.dev, "Can't reach %u ns\n", state->period);
      ^~~~~~~

vim +64 drivers//pwm/pwm-stm32-lp.c

e70a540b4e0230 Fabrice Gasnier  2017-08-28  @13  #include <linux/mfd/stm32-lptimer.h>
e70a540b4e0230 Fabrice Gasnier  2017-08-28   14  #include <linux/module.h>
e70a540b4e0230 Fabrice Gasnier  2017-08-28   15  #include <linux/of.h>
cce4a833fc6dfd Fabrice Gasnier  2019-04-18   16  #include <linux/pinctrl/consumer.h>
e70a540b4e0230 Fabrice Gasnier  2017-08-28   17  #include <linux/platform_device.h>
e70a540b4e0230 Fabrice Gasnier  2017-08-28   18  #include <linux/pwm.h>
e70a540b4e0230 Fabrice Gasnier  2017-08-28   19  
e70a540b4e0230 Fabrice Gasnier  2017-08-28   20  struct stm32_pwm_lp {
e70a540b4e0230 Fabrice Gasnier  2017-08-28   21  	struct pwm_chip chip;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   22  	struct clk *clk;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   23  	struct regmap *regmap;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   24  };
e70a540b4e0230 Fabrice Gasnier  2017-08-28   25  
e70a540b4e0230 Fabrice Gasnier  2017-08-28   26  static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip)
e70a540b4e0230 Fabrice Gasnier  2017-08-28   27  {
e70a540b4e0230 Fabrice Gasnier  2017-08-28   28  	return container_of(chip, struct stm32_pwm_lp, chip);
e70a540b4e0230 Fabrice Gasnier  2017-08-28   29  }
e70a540b4e0230 Fabrice Gasnier  2017-08-28   30  
e70a540b4e0230 Fabrice Gasnier  2017-08-28   31  /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */
e70a540b4e0230 Fabrice Gasnier  2017-08-28   32  #define STM32_LPTIM_MAX_PRESCALER	128
e70a540b4e0230 Fabrice Gasnier  2017-08-28   33  
e70a540b4e0230 Fabrice Gasnier  2017-08-28   34  static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
71523d1812aca6 Uwe Kleine-König 2019-08-24   35  			      const struct pwm_state *state)
e70a540b4e0230 Fabrice Gasnier  2017-08-28   36  {
e70a540b4e0230 Fabrice Gasnier  2017-08-28   37  	struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip);
e70a540b4e0230 Fabrice Gasnier  2017-08-28   38  	unsigned long long prd, div, dty;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   39  	struct pwm_state cstate;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   40  	u32 val, mask, cfgr, presc = 0;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   41  	bool reenable;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   42  	int ret;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   43  
e70a540b4e0230 Fabrice Gasnier  2017-08-28   44  	pwm_get_state(pwm, &cstate);
e70a540b4e0230 Fabrice Gasnier  2017-08-28   45  	reenable = !cstate.enabled;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   46  
e70a540b4e0230 Fabrice Gasnier  2017-08-28   47  	if (!state->enabled) {
e70a540b4e0230 Fabrice Gasnier  2017-08-28   48  		if (cstate.enabled) {
e70a540b4e0230 Fabrice Gasnier  2017-08-28   49  			/* Disable LP timer */
e70a540b4e0230 Fabrice Gasnier  2017-08-28   50  			ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
e70a540b4e0230 Fabrice Gasnier  2017-08-28   51  			if (ret)
e70a540b4e0230 Fabrice Gasnier  2017-08-28   52  				return ret;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   53  			/* disable clock to PWM counter */
e70a540b4e0230 Fabrice Gasnier  2017-08-28   54  			clk_disable(priv->clk);
e70a540b4e0230 Fabrice Gasnier  2017-08-28   55  		}
e70a540b4e0230 Fabrice Gasnier  2017-08-28   56  		return 0;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   57  	}
e70a540b4e0230 Fabrice Gasnier  2017-08-28   58  
e70a540b4e0230 Fabrice Gasnier  2017-08-28   59  	/* Calculate the period and prescaler value */
e70a540b4e0230 Fabrice Gasnier  2017-08-28   60  	div = (unsigned long long)clk_get_rate(priv->clk) * state->period;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   61  	do_div(div, NSEC_PER_SEC);
c91e3234c6035b Fabrice Gasnier  2019-09-18   62  	if (!div) {
c91e3234c6035b Fabrice Gasnier  2019-09-18   63  		/* Clock is too slow to achieve requested period. */
c91e3234c6035b Fabrice Gasnier  2019-09-18  @64  		dev_dbg(priv->chip.dev, "Can't reach %u ns\n",	state->period);
c91e3234c6035b Fabrice Gasnier  2019-09-18   65  		return -EINVAL;
c91e3234c6035b Fabrice Gasnier  2019-09-18   66  	}
c91e3234c6035b Fabrice Gasnier  2019-09-18   67  
e70a540b4e0230 Fabrice Gasnier  2017-08-28   68  	prd = div;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   69  	while (div > STM32_LPTIM_MAX_ARR) {
e70a540b4e0230 Fabrice Gasnier  2017-08-28   70  		presc++;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   71  		if ((1 << presc) > STM32_LPTIM_MAX_PRESCALER) {
e70a540b4e0230 Fabrice Gasnier  2017-08-28   72  			dev_err(priv->chip.dev, "max prescaler exceeded\n");
e70a540b4e0230 Fabrice Gasnier  2017-08-28   73  			return -EINVAL;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   74  		}
e70a540b4e0230 Fabrice Gasnier  2017-08-28   75  		div = prd >> presc;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   76  	}
e70a540b4e0230 Fabrice Gasnier  2017-08-28   77  	prd = div;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   78  
e70a540b4e0230 Fabrice Gasnier  2017-08-28   79  	/* Calculate the duty cycle */
e70a540b4e0230 Fabrice Gasnier  2017-08-28   80  	dty = prd * state->duty_cycle;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   81  	do_div(dty, state->period);
e70a540b4e0230 Fabrice Gasnier  2017-08-28   82  
e70a540b4e0230 Fabrice Gasnier  2017-08-28   83  	if (!cstate.enabled) {
e70a540b4e0230 Fabrice Gasnier  2017-08-28   84  		/* enable clock to drive PWM counter */
e70a540b4e0230 Fabrice Gasnier  2017-08-28   85  		ret = clk_enable(priv->clk);
e70a540b4e0230 Fabrice Gasnier  2017-08-28   86  		if (ret)
e70a540b4e0230 Fabrice Gasnier  2017-08-28   87  			return ret;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   88  	}
e70a540b4e0230 Fabrice Gasnier  2017-08-28   89  
e70a540b4e0230 Fabrice Gasnier  2017-08-28   90  	ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr);
e70a540b4e0230 Fabrice Gasnier  2017-08-28   91  	if (ret)
e70a540b4e0230 Fabrice Gasnier  2017-08-28   92  		goto err;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   93  
e70a540b4e0230 Fabrice Gasnier  2017-08-28   94  	if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) ||
e70a540b4e0230 Fabrice Gasnier  2017-08-28   95  	    (FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity)) {
e70a540b4e0230 Fabrice Gasnier  2017-08-28   96  		val = FIELD_PREP(STM32_LPTIM_PRESC, presc);
e70a540b4e0230 Fabrice Gasnier  2017-08-28   97  		val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity);
e70a540b4e0230 Fabrice Gasnier  2017-08-28   98  		mask = STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL;
e70a540b4e0230 Fabrice Gasnier  2017-08-28   99  
e70a540b4e0230 Fabrice Gasnier  2017-08-28  100  		/* Must disable LP timer to modify CFGR */
e70a540b4e0230 Fabrice Gasnier  2017-08-28  101  		reenable = true;
e70a540b4e0230 Fabrice Gasnier  2017-08-28  102  		ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
e70a540b4e0230 Fabrice Gasnier  2017-08-28  103  		if (ret)
e70a540b4e0230 Fabrice Gasnier  2017-08-28  104  			goto err;
e70a540b4e0230 Fabrice Gasnier  2017-08-28  105  
e70a540b4e0230 Fabrice Gasnier  2017-08-28  106  		ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask,
e70a540b4e0230 Fabrice Gasnier  2017-08-28  107  					 val);
e70a540b4e0230 Fabrice Gasnier  2017-08-28  108  		if (ret)
e70a540b4e0230 Fabrice Gasnier  2017-08-28  109  			goto err;
e70a540b4e0230 Fabrice Gasnier  2017-08-28  110  	}
e70a540b4e0230 Fabrice Gasnier  2017-08-28  111  
e70a540b4e0230 Fabrice Gasnier  2017-08-28  112  	if (reenable) {
e70a540b4e0230 Fabrice Gasnier  2017-08-28  113  		/* Must (re)enable LP timer to modify CMP & ARR */
e70a540b4e0230 Fabrice Gasnier  2017-08-28  114  		ret = regmap_write(priv->regmap, STM32_LPTIM_CR,
e70a540b4e0230 Fabrice Gasnier  2017-08-28  115  				   STM32_LPTIM_ENABLE);
e70a540b4e0230 Fabrice Gasnier  2017-08-28  116  		if (ret)
e70a540b4e0230 Fabrice Gasnier  2017-08-28  117  			goto err;
e70a540b4e0230 Fabrice Gasnier  2017-08-28  118  	}
e70a540b4e0230 Fabrice Gasnier  2017-08-28  119  
e70a540b4e0230 Fabrice Gasnier  2017-08-28  120  	ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, prd - 1);
e70a540b4e0230 Fabrice Gasnier  2017-08-28  121  	if (ret)
e70a540b4e0230 Fabrice Gasnier  2017-08-28  122  		goto err;
e70a540b4e0230 Fabrice Gasnier  2017-08-28  123  
e70a540b4e0230 Fabrice Gasnier  2017-08-28  124  	ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, prd - (1 + dty));
e70a540b4e0230 Fabrice Gasnier  2017-08-28  125  	if (ret)
e70a540b4e0230 Fabrice Gasnier  2017-08-28  126  		goto err;
e70a540b4e0230 Fabrice Gasnier  2017-08-28  127  
e70a540b4e0230 Fabrice Gasnier  2017-08-28  128  	/* ensure CMP & ARR registers are properly written */
e70a540b4e0230 Fabrice Gasnier  2017-08-28  129  	ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
e70a540b4e0230 Fabrice Gasnier  2017-08-28  130  				       (val & STM32_LPTIM_CMPOK_ARROK),
e70a540b4e0230 Fabrice Gasnier  2017-08-28  131  				       100, 1000);
e70a540b4e0230 Fabrice Gasnier  2017-08-28  132  	if (ret) {
e70a540b4e0230 Fabrice Gasnier  2017-08-28  133  		dev_err(priv->chip.dev, "ARR/CMP registers write issue\n");
e70a540b4e0230 Fabrice Gasnier  2017-08-28  134  		goto err;
e70a540b4e0230 Fabrice Gasnier  2017-08-28  135  	}
e70a540b4e0230 Fabrice Gasnier  2017-08-28  136  	ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
e70a540b4e0230 Fabrice Gasnier  2017-08-28  137  			   STM32_LPTIM_CMPOKCF_ARROKCF);
e70a540b4e0230 Fabrice Gasnier  2017-08-28  138  	if (ret)
e70a540b4e0230 Fabrice Gasnier  2017-08-28  139  		goto err;
e70a540b4e0230 Fabrice Gasnier  2017-08-28  140  
e70a540b4e0230 Fabrice Gasnier  2017-08-28  141  	if (reenable) {
e70a540b4e0230 Fabrice Gasnier  2017-08-28  142  		/* Start LP timer in continuous mode */
e70a540b4e0230 Fabrice Gasnier  2017-08-28  143  		ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
e70a540b4e0230 Fabrice Gasnier  2017-08-28  144  					 STM32_LPTIM_CNTSTRT,
e70a540b4e0230 Fabrice Gasnier  2017-08-28  145  					 STM32_LPTIM_CNTSTRT);
e70a540b4e0230 Fabrice Gasnier  2017-08-28  146  		if (ret) {
e70a540b4e0230 Fabrice Gasnier  2017-08-28  147  			regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
e70a540b4e0230 Fabrice Gasnier  2017-08-28  148  			goto err;
e70a540b4e0230 Fabrice Gasnier  2017-08-28  149  		}
e70a540b4e0230 Fabrice Gasnier  2017-08-28  150  	}
e70a540b4e0230 Fabrice Gasnier  2017-08-28  151  
e70a540b4e0230 Fabrice Gasnier  2017-08-28  152  	return 0;
e70a540b4e0230 Fabrice Gasnier  2017-08-28  153  err:
e70a540b4e0230 Fabrice Gasnier  2017-08-28  154  	if (!cstate.enabled)
e70a540b4e0230 Fabrice Gasnier  2017-08-28  155  		clk_disable(priv->clk);
e70a540b4e0230 Fabrice Gasnier  2017-08-28  156  
e70a540b4e0230 Fabrice Gasnier  2017-08-28  157  	return ret;
e70a540b4e0230 Fabrice Gasnier  2017-08-28  158  }
e70a540b4e0230 Fabrice Gasnier  2017-08-28  159

:::::: The code at line 64 was first introduced by commit
:::::: c91e3234c6035baf5a79763cb4fcd5d23ce75c2b pwm: stm32-lp: Add check in case requested period cannot be achieved

:::::: TO: Fabrice Gasnier <[email protected]> :::::: CC: Thierry Reding <[email protected]>

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