arm64: IPQ6018 PCIe support
Subsystems (9)
v2 cover arm64: IPQ6018 PCIe support
This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on().
Tested on IPQ6010 based hardware.
Changes in v2:
* Add patch moving GEN3_RELATED macros to a common header
* Drop ATU configuration from pcie-qcom
* Remove local definition of common registers
* Use bulk clk and reset APIs
* Remove msi-parent from device-tree
Baruch Siach (3):
PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
dt-bindings: phy: qcom,qmp: Add IPQ60xx PCIe PHY bindings
dt-bindings: pci: qcom: Document PCIe bindings for IPQ6018 SoC
Selvam Sathappan Periakaruppan (3):
PCI: qcom: add support for IPQ60xx PCIe controller
phy: qcom-qmp: add QMP V2 PCIe PHY support for ipq60xx
arm64: dts: ipq6018: Add pcie support
.../devicetree/bindings/pci/qcom,pcie.txt | 24 +++ .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 25 +++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 99 ++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 7 + drivers/pci/controller/dwc/pcie-qcom.c | 150 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-tegra194.c | 6 - drivers/phy/qualcomm/phy-qcom-qmp.c | 147 +++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 132 +++++++++++++++ 8 files changed, 584 insertions(+), 6 deletions(-)
Signature · 1 line
2.30.2
PATCH v2 1/6 PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
These are common dwc macros that will be used for other platforms.
--- drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++ drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------ 2 files changed, 6 insertions(+), 6 deletions(-)
drivers/pci/controller/dwc/pcie-designware.h +6 -0
@@ -74,6 +74,12 @@#define PCIE_MSI_INTR0_MASK 0x82C#define PCIE_MSI_INTR0_STATUS 0x830 +#define GEN3_RELATED_OFF 0x890 +#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) +#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) +#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 +#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) +#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0#define PORT_MLTI_UPCFG_SUPPORT BIT(7)
drivers/pci/controller/dwc/pcie-tegra194.c +0 -6
@@ -193,12 +193,6 @@#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)#define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0) -#define GEN3_RELATED_OFF 0x890 -#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) -#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) -#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 -#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) -#define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0#define AMBA_ERROR_RESPONSE_CRS_SHIFT 3#define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0)
Signature · 1 line
2.30.2
Re: [PATCH v2 1/6] PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
Quoted 8 lines · Baruch Siach
These are common dwc macros that will be used for other platforms.
Signed-off-by Baruch Siach <[email protected]>--- drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++ drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------ 2 files changed, 6 insertions(+), 6 deletions(-)
PATCH v2 2/6 PCI: qcom: add support for IPQ60xx PCIe controller
In reply to Baruch SiachFrom: Selvam Sathappan Periakaruppan <[email protected]>
IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that platform.
The code is based on downstream Codeaurora kernel v5.4. Split out the DBI registers access part from .init into .post_init. DBI registers are only accessible after phy_power_on().
---
v2:
* Drop ATU configuration; rely on common code instead
* Use more common register macros
* Use bulk clk and reset APIs
--- drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 150 +++++++++++++++++++ 2 files changed, 151 insertions(+)
drivers/pci/controller/dwc/pcie-designware.h +1 -0
@@ -76,6 +76,7 @@#define GEN3_RELATED_OFF 0x890#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) +#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
drivers/pci/controller/dwc/pcie-qcom.c +150 -0
192 lines not on this page · raw message
Signature · 1 line
2.30.2
Re: [PATCH v2 2/6] PCI: qcom: add support for IPQ60xx PCIe controller
Quoted 52 lines · Baruch Siach
From: Selvam Sathappan Periakaruppan <[email protected]>
IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that platform.
The code is based on downstream Codeaurora kernel v5.4. Split out the DBI registers access part from .init into .post_init. DBI registers are only accessible after
phy_power_on().Signed-off-by Selvam Sathappan Periakaruppan <[email protected]>Signed-off-by Baruch Siach <[email protected]>---
v2:
* Drop ATU configuration; rely on common code instead* Use more common register macros
* Use bulk clk and reset APIs
--- drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 150 +++++++++++++++++++ 2 files changed, 151 insertions(+)drivers/pci/controller/dwc/pcie-designware.h +1
-0@@ -76,6 +76,7 @@#define GEN3_RELATED_OFF 0x890#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) +#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)drivers/pci/controller/dwc/pcie-qcom.c +4
-0@@ -52,6 +52,10 @@#define PCIE20_PARF_DBI_BASE_ADDR 0x168#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 +#define AHB_CLK_EN BIT(0) +#define MSTR_AXI_CLK_EN BIT(1) +#define BYPASS BIT(4) +#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8#define PCIE20_PARF_LTSSM 0x1B0
drivers/pci/controller/dwc/pcie-qcom.c line 101
Quoted 4 lines
drivers/pci/controller/dwc/pcie-qcom.c +1
-0@@ -94,6 +98,12 @@#define SLV_ADDR_SPACE_SZ 0x10000000#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 +#define PCIE_CAP_CURR_DEEMPHASIS BIT(16)
Isn't this a standard register field?
drivers/pci/controller/dwc/pcie-qcom.c line 104
Quoted 3 lines
drivers/pci/controller/dwc/pcie-qcom.c +3
-0+#define SPEED_GEN1 0x1 +#define SPEED_GEN2 0x2 +#define SPEED_GEN3 0x3
And these?
There's already some common DWC code for setting the link speed.
Quoted 135 lines
drivers/pci/controller/dwc/pcie-qcom.c +114
-0+#define AXI_CLK_RATE 200000000 +#define RCHNG_CLK_RATE 100000000#define DEVICE_TYPE_RC 0x4@@ -168,6 +178,11 @@ struct qcom_pcie_resources_2_7_0 {struct clk *pipe_clk; }; +struct qcom_pcie_resources_2_9_0 { +struct clk_bulk_data clks[5 ]; +struct reset_control *rst; +}; +union qcom_pcie_resources {struct qcom_pcie_resources_1_0_0 v1_0_0;struct qcom_pcie_resources_2_1_0 v2_1_0;@@ -175,6 +190,7 @@ union qcom_pcie_resources {struct qcom_pcie_resources_2_3_3 v2_3_3;struct qcom_pcie_resources_2_4_0 v2_4_0;struct qcom_pcie_resources_2_7_0 v2_7_0; +struct qcom_pcie_resources_2_9_0 v2_9_0; };struct qcom_pcie ;@@ -1266,6 +1282,130 @@ static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie)clk_disable_unprepare (res->pipe_clk); } +static int qcom_pcie_get_resources_2_9_0 (struct qcom_pcie *pcie) +{ +struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; +struct dw_pcie *pci = pcie->pci; +struct device *dev = pci->dev; +int ret; + + res->clks[0 ].id ="iface" ; + res->clks[1 ].id ="axi_m" ; + res->clks[2 ].id ="axi_s" ; + res->clks[3 ].id ="axi_bridge" ; + res->clks[4 ].id ="rchng" ; + + ret =devm_clk_bulk_get (dev,ARRAY_SIZE (res->clks), res->clks); +if (ret <0 ) +return ret; + + res->rst =devm_reset_control_array_get_exclusive (dev); +if (IS_ERR (res->rst)) +return PTR_ERR (res->rst); + +return 0 ; +} + +static void qcom_pcie_deinit_2_9_0 (struct qcom_pcie *pcie) +{ +struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; + +clk_bulk_disable_unprepare (ARRAY_SIZE (res->clks), res->clks); +} + +static int qcom_pcie_init_2_9_0 (struct qcom_pcie *pcie) +{ +struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; +struct device *dev = pcie->pci->dev; +int ret; + + ret =reset_control_assert (res->rst); +if (ret) { +dev_err (dev,"reset assert failed (%d)\n" , ret); +return ret; + } + +usleep_range (2000 ,2500 ); + + ret =reset_control_deassert (res->rst); +if (ret) { +dev_err (dev,"reset deassert failed (%d)\n" , ret); +return ret; + } + +/* +* Don't have a way to see if the reset has completed. +* Wait for some time. +*/ +usleep_range (2000 ,2500 ); + + ret =clk_bulk_prepare_enable (ARRAY_SIZE (res->clks), res->clks); +if (ret) + goto err_reset; + +return 0 ; + +/* +* Not checking for failure, will anyway return +* the original failure in 'ret'. +*/ +err_reset: +reset_control_assert (res->rst); + +return ret; +} + +static int qcom_pcie_post_init_2_9_0 (struct qcom_pcie *pcie) +{ +struct dw_pcie *pci = pcie->pci; +u16 offset =dw_pcie_find_capability (pci,PCI_CAP_ID_EXP ); +u32 val; +int i; + +writel (SLV_ADDR_SPACE_SZ , + pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE); + + val =readl (pcie->parf +PCIE20_PARF_PHY_CTRL ); + val &= ~BIT (0 ); +writel (val, pcie->parf +PCIE20_PARF_PHY_CTRL ); + +writel (0 , pcie->parf +PCIE20_PARF_DBI_BASE_ADDR ); + +writel (DEVICE_TYPE_RC , pcie->parf +PCIE20_PARF_DEVICE_TYPE ); +writel (BYPASS |MSTR_AXI_CLK_EN |AHB_CLK_EN , + pcie->parf +PCIE20_PARF_MHI_CLOCK_RESET_CTRL ); +writel (GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS + |GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL , + pci->dbi_base +GEN3_RELATED_OFF ); + +writel (MST_WAKEUP_EN |SLV_WAKEUP_EN |MSTR_ACLK_CGC_DIS + |SLV_ACLK_CGC_DIS |CORE_CLK_CGC_DIS | +AUX_PWR_DET |L23_CLK_RMV_DIS |L1_CLK_RMV_DIS , + pcie->parf +PCIE20_PARF_SYS_CTRL ); + +writel (0 , pcie->parf +PCIE20_PARF_Q2A_FLUSH ); + +dw_pcie_dbi_ro_wr_en (pci); +writel (PCIE_CAP_LINK1_VAL , pci->dbi_base + offset +PCI_EXP_SLTCAP ); +
drivers/pci/controller/dwc/pcie-qcom.c static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) · line 1400
Quoted 10 lines
drivers/pci/controller/dwc/pcie-qcom.c +10
-0+/* Configure PCIe link capabilities for ASPM */ + val =readl (pci->dbi_base + offset +PCI_EXP_LNKCAP ); + val &= ~PCI_EXP_LNKCAP_ASPMS ; +writel (val, pci->dbi_base + offset +PCI_EXP_LNKCAP ); + +writel (PCI_EXP_DEVCTL2_COMP_TMOUT_DIS , pci->dbi_base + offset + +PCI_EXP_DEVCTL2 ); + +writel (PCIE_CAP_CURR_DEEMPHASIS |SPEED_GEN3 , + pci->dbi_base + offset +PCI_EXP_DEVCTL2 );
Doesn't this overwrite the prior register write?
Quoted 38 lines
drivers/pci/controller/dwc/pcie-qcom.c +18
-1+ +for (i =0 ;i <256 ;i++) +writel (0x0 , pcie->parf +PCIE20_PARF_BDF_TO_SID_TABLE_N + + (4 * i)); + +return 0 ; +} +static int qcom_pcie_link_up (struct dw_pcie *pci) {u16 offset =dw_pcie_find_capability (pci,PCI_CAP_ID_EXP );@@ -1456,6 +1596,15 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .config_sid = qcom_pcie_config_sid_sm8250, }; +/* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */ +static const struct qcom_pcie_ops ops_2_9_0 = { + .get_resources = qcom_pcie_get_resources_2_9_0, + .init = qcom_pcie_init_2_9_0, + .post_init = qcom_pcie_post_init_2_9_0, + .deinit = qcom_pcie_deinit_2_9_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, +}; +static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link,@@ -1555,6 +1704,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 }, + { .compatible = "qcom,pcie-ipq6018", .data = &ops_2_9_0 }, { } }; --2.30.2
Re: [PATCH v2 2/6] PCI: qcom: add support for IPQ60xx PCIe controller
Hi Rob,
Quoted 55 lines · Rob Herring
Quoted 54 lines · Baruch Siach
From: Selvam Sathappan Periakaruppan <[email protected]>
IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that platform.
The code is based on downstream Codeaurora kernel v5.4. Split out the DBI registers access part from .init into .post_init. DBI registers are only accessible after
phy_power_on().Signed-off-by Selvam Sathappan Periakaruppan <[email protected]>Signed-off-by Baruch Siach <[email protected]>---
v2:
* Drop ATU configuration; rely on common code instead* Use more common register macros
* Use bulk clk and reset APIs
--- drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 150 +++++++++++++++++++ 2 files changed, 151 insertions(+)drivers/pci/controller/dwc/pcie-designware.h +1
-0@@ -76,6 +76,7 @@#define GEN3_RELATED_OFF 0x890#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) +#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)drivers/pci/controller/dwc/pcie-qcom.c +4
-0@@ -52,6 +52,10 @@#define PCIE20_PARF_DBI_BASE_ADDR 0x168#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 +#define AHB_CLK_EN BIT(0) +#define MSTR_AXI_CLK_EN BIT(1) +#define BYPASS BIT(4) +#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8#define PCIE20_PARF_LTSSM 0x1B0@@ -94,6 +98,12 @@#define SLV_ADDR_SPACE_SZ 0x10000000
Quoted 4 lines
drivers/pci/controller/dwc/pcie-qcom.c line 101
Quoted 2 lines
drivers/pci/controller/dwc/pcie-qcom.c +1
-0#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 +#define PCIE_CAP_CURR_DEEMPHASIS BIT(16)Isn't this a standard register field?
I don't know. I could not find any reference to this field or the registers it's part of.
n
Quoted 7 lines
drivers/pci/controller/dwc/pcie-qcom.c line 104
Quoted 3 lines
drivers/pci/controller/dwc/pcie-qcom.c +3
-0+#define SPEED_GEN1 0x1 +#define SPEED_GEN2 0x2 +#define SPEED_GEN3 0x3And these?
There's already some common DWC code for setting the link speed.
dw_pcie_link_set_max_speed() deals with other registers, as far as I can see.
Quoted 4 lines
Quoted 4 lines
drivers/pci/controller/dwc/pcie-qcom.c +2
-0+#define AXI_CLK_RATE 200000000 +#define RCHNG_CLK_RATE 100000000#define DEVICE_TYPE_RC 0x4
[snip]
Quoted 37 lines
Quoted 37 lines
drivers/pci/controller/dwc/pcie-qcom.c +37
-0+static int qcom_pcie_post_init_2_9_0 (struct qcom_pcie *pcie) +{ +struct dw_pcie *pci = pcie->pci; +u16 offset =dw_pcie_find_capability (pci,PCI_CAP_ID_EXP ); +u32 val; +int i; + +writel (SLV_ADDR_SPACE_SZ , + pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE); + + val =readl (pcie->parf +PCIE20_PARF_PHY_CTRL ); + val &= ~BIT (0 ); +writel (val, pcie->parf +PCIE20_PARF_PHY_CTRL ); + +writel (0 , pcie->parf +PCIE20_PARF_DBI_BASE_ADDR ); + +writel (DEVICE_TYPE_RC , pcie->parf +PCIE20_PARF_DEVICE_TYPE ); +writel (BYPASS |MSTR_AXI_CLK_EN |AHB_CLK_EN , + pcie->parf +PCIE20_PARF_MHI_CLOCK_RESET_CTRL ); +writel (GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS + |GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL , + pci->dbi_base +GEN3_RELATED_OFF ); + +writel (MST_WAKEUP_EN |SLV_WAKEUP_EN |MSTR_ACLK_CGC_DIS + |SLV_ACLK_CGC_DIS |CORE_CLK_CGC_DIS | +AUX_PWR_DET |L23_CLK_RMV_DIS |L1_CLK_RMV_DIS , + pcie->parf +PCIE20_PARF_SYS_CTRL ); + +writel (0 , pcie->parf +PCIE20_PARF_Q2A_FLUSH ); + +dw_pcie_dbi_ro_wr_en (pci); +writel (PCIE_CAP_LINK1_VAL , pci->dbi_base + offset +PCI_EXP_SLTCAP ); + +/* Configure PCIe link capabilities for ASPM */ + val =readl (pci->dbi_base + offset +PCI_EXP_LNKCAP ); + val &= ~PCI_EXP_LNKCAP_ASPMS ; +writel (val, pci->dbi_base + offset +PCI_EXP_LNKCAP );
Quoted 8 lines
drivers/pci/controller/dwc/pcie-qcom.c static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) · line 1400
Quoted 6 lines
drivers/pci/controller/dwc/pcie-qcom.c +6
-0+ +writel (PCI_EXP_DEVCTL2_COMP_TMOUT_DIS , pci->dbi_base + offset + +PCI_EXP_DEVCTL2 ); + +writel (PCIE_CAP_CURR_DEEMPHASIS |SPEED_GEN3 , + pci->dbi_base + offset +PCI_EXP_DEVCTL2 );Doesn't this overwrite the prior register write?
It does. There are two mistakes here. The writel() above should set PCIE20_DEVICE_CONTROL2_STATUS2 (offset 0x98). This writel() should set PCIE20_LNK_CONTROL2_LINK_STATUS2 (offset 0xa0). So both are wrong.
Quoted 7 lines
drivers/pci/controller/dwc/pcie-qcom.c static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) · line 1407
Quoted 7 lines
drivers/pci/controller/dwc/pcie-qcom.c +7
-0+ +for (i =0 ;i <256 ;i++) +writel (0x0 , pcie->parf +PCIE20_PARF_BDF_TO_SID_TABLE_N + + (4 * i)); + +return 0 ; +}
Thanks,
baruch
Signature · 3 lines
~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- [email protected] - tel: +972.52.368.4656, http://www.tkos.co.il -Re: [PATCH v2 2/6] PCI: qcom: add support for IPQ60xx PCIe controller
Quoted 59 lines · Baruch Siach
Hi Rob,
Quoted 55 lines · Rob Herring
Quoted 54 lines · Baruch Siach
From: Selvam Sathappan Periakaruppan <[email protected]>
IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that platform.
The code is based on downstream Codeaurora kernel v5.4. Split out the DBI registers access part from .init into .post_init. DBI registers are only accessible after
phy_power_on().Signed-off-by Selvam Sathappan Periakaruppan <[email protected]>Signed-off-by Baruch Siach <[email protected]>---
v2:
* Drop ATU configuration; rely on common code instead* Use more common register macros
* Use bulk clk and reset APIs
--- drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 150 +++++++++++++++++++ 2 files changed, 151 insertions(+)drivers/pci/controller/dwc/pcie-designware.h +1
-0@@ -76,6 +76,7 @@#define GEN3_RELATED_OFF 0x890#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) +#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)drivers/pci/controller/dwc/pcie-qcom.c +4
-0@@ -52,6 +52,10 @@#define PCIE20_PARF_DBI_BASE_ADDR 0x168#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 +#define AHB_CLK_EN BIT(0) +#define MSTR_AXI_CLK_EN BIT(1) +#define BYPASS BIT(4) +#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8#define PCIE20_PARF_LTSSM 0x1B0@@ -94,6 +98,12 @@#define SLV_ADDR_SPACE_SZ 0x10000000
Quoted 7 lines
Quoted 4 lines
drivers/pci/controller/dwc/pcie-qcom.c line 101
Quoted 2 lines
drivers/pci/controller/dwc/pcie-qcom.c +1
-0#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 +#define PCIE_CAP_CURR_DEEMPHASIS BIT(16)Isn't this a standard register field?
I don't know. I could not find any reference to this field or the registers it's part of.
It is. I found it in the spec. But it's not in pci_reg.h and it is a read-only status bit (though some in DWC can be written).
Quoted 6 lines
n
Quoted 5 lines
drivers/pci/controller/dwc/pcie-qcom.c line 104
Quoted 3 lines
drivers/pci/controller/dwc/pcie-qcom.c +3
-0+#define SPEED_GEN1 0x1 +#define SPEED_GEN2 0x2 +#define SPEED_GEN3 0x3And these?
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ #define PCI_EXP_LNKCTL2_TLS 0x000f #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
Quoted 5 lines
Quoted 2 lines
There's already some common DWC code for setting the link speed.
dw_pcie_link_set_max_speed()deals with other registers, as far as I can see.
Link Control2 which is what the above function configures appears to be the same register to me. Your definition is combining 2 registers.
Quoted 54 lines
Quoted 5 lines
Quoted 5 lines
drivers/pci/controller/dwc/pcie-qcom.c +2
-0+#define AXI_CLK_RATE 200000000 +#define RCHNG_CLK_RATE 100000000#define DEVICE_TYPE_RC 0x4[snip]
Quoted 37 lines
Quoted 37 lines
drivers/pci/controller/dwc/pcie-qcom.c +37
-0+static int qcom_pcie_post_init_2_9_0 (struct qcom_pcie *pcie) +{ +struct dw_pcie *pci = pcie->pci; +u16 offset =dw_pcie_find_capability (pci,PCI_CAP_ID_EXP ); +u32 val; +int i; + +writel (SLV_ADDR_SPACE_SZ , + pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE); + + val =readl (pcie->parf +PCIE20_PARF_PHY_CTRL ); + val &= ~BIT (0 ); +writel (val, pcie->parf +PCIE20_PARF_PHY_CTRL ); + +writel (0 , pcie->parf +PCIE20_PARF_DBI_BASE_ADDR ); + +writel (DEVICE_TYPE_RC , pcie->parf +PCIE20_PARF_DEVICE_TYPE ); +writel (BYPASS |MSTR_AXI_CLK_EN |AHB_CLK_EN , + pcie->parf +PCIE20_PARF_MHI_CLOCK_RESET_CTRL ); +writel (GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS + |GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL , + pci->dbi_base +GEN3_RELATED_OFF ); + +writel (MST_WAKEUP_EN |SLV_WAKEUP_EN |MSTR_ACLK_CGC_DIS + |SLV_ACLK_CGC_DIS |CORE_CLK_CGC_DIS | +AUX_PWR_DET |L23_CLK_RMV_DIS |L1_CLK_RMV_DIS , + pcie->parf +PCIE20_PARF_SYS_CTRL ); + +writel (0 , pcie->parf +PCIE20_PARF_Q2A_FLUSH ); + +dw_pcie_dbi_ro_wr_en (pci); +writel (PCIE_CAP_LINK1_VAL , pci->dbi_base + offset +PCI_EXP_SLTCAP ); + +/* Configure PCIe link capabilities for ASPM */ + val =readl (pci->dbi_base + offset +PCI_EXP_LNKCAP ); + val &= ~PCI_EXP_LNKCAP_ASPMS ; +writel (val, pci->dbi_base + offset +PCI_EXP_LNKCAP );Quoted 8 lines
drivers/pci/controller/dwc/pcie-qcom.c static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) · line 1400
Quoted 6 lines
drivers/pci/controller/dwc/pcie-qcom.c +6
-0+ +writel (PCI_EXP_DEVCTL2_COMP_TMOUT_DIS , pci->dbi_base + offset + +PCI_EXP_DEVCTL2 ); + +writel (PCIE_CAP_CURR_DEEMPHASIS |SPEED_GEN3 , + pci->dbi_base + offset +PCI_EXP_DEVCTL2 );Doesn't this overwrite the prior register write?
Quoted 2 lines
It does. There are two mistakes here. The
writel()above should setPCIE20_DEVICE_CONTROL2_STATUS2(offset0x98).
No. Did you check what 'offset' is? PCIE20_DEVICE_CONTROL2_STATUS2 is PCI_EXP_DEVCTL2 plus the status reg. What's wrong is it should be a 16-bit write.
Quoted 18 lines
This
writel()should setPCIE20_LNK_CONTROL2_LINK_STATUS2(offset0xa0). So both are wrong.Quoted 7 lines
drivers/pci/controller/dwc/pcie-qcom.c static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) · line 1407
Quoted 7 lines
drivers/pci/controller/dwc/pcie-qcom.c +7
-0+ +for (i =0 ;i <256 ;i++) +writel (0x0 , pcie->parf +PCIE20_PARF_BDF_TO_SID_TABLE_N + + (4 * i)); + +return 0 ; +}Thanks,
baruch--
~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- [email protected] - tel: +972.52.368.4656, http://www.tkos.co.il -
Re: [PATCH v2 2/6] PCI: qcom: add support for IPQ60xx PCIe controller
Hi Rob,
Quoted 9 lines · Rob Herring
Quoted 8 lines · Baruch Siach
Quoted 7 lines · Rob Herring
Quoted 5 lines · Baruch Siach
drivers/pci/controller/dwc/pcie-qcom.c +5
-0+writel (PCI_EXP_DEVCTL2_COMP_TMOUT_DIS , pci->dbi_base + offset + +PCI_EXP_DEVCTL2 ); + +writel (PCIE_CAP_CURR_DEEMPHASIS |SPEED_GEN3 , + pci->dbi_base + offset +PCI_EXP_DEVCTL2 );
Quoted 8 lines
Quoted 4 lines
Quoted 1 line
Doesn't this overwrite the prior register write?
It does. There are two mistakes here. The
writel()above should setPCIE20_DEVICE_CONTROL2_STATUS2(offset0x98).No. Did you check what 'offset' is?
PCIE20_DEVICE_CONTROL2_STATUS2isPCI_EXP_DEVCTL2plus the status reg. What's wrong is it should be a 16-bit write.
Thanks for enlightening me. 'offset' is 0x70 here. So PCI_EXP_DEVCTL2 is at 0x98, and PCI_EXP_LNKCTL2 is at 0xa0. Only the second writel() is wrong. But since generic code handles speed, I can drop it entirely.
I see that dw_pcie_link_set_max_speed() uses dw_pcie_writel_dbi() to write to PCI_EXP_LNKCTL2. Is that 16-bit write?
Why are pci_regs.h register offsets in decimal?
Quoted 2 lines
Quoted 2 lines
This
writel()should setPCIE20_LNK_CONTROL2_LINK_STATUS2(offset0xa0). So both are wrong.
Thanks,
baruch
Signature · 3 lines
~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- [email protected] - tel: +972.52.368.4656, http://www.tkos.co.il -Re: [PATCH v2 2/6] PCI: qcom: add support for IPQ60xx PCIe controller
Quoted 22 lines · Baruch Siach
Hi Rob,
Quoted 9 lines · Rob Herring
Quoted 8 lines · Baruch Siach
Quoted 7 lines · Rob Herring
Quoted 5 lines · Baruch Siach
drivers/pci/controller/dwc/pcie-qcom.c +5
-0+writel (PCI_EXP_DEVCTL2_COMP_TMOUT_DIS , pci->dbi_base + offset + +PCI_EXP_DEVCTL2 ); + +writel (PCIE_CAP_CURR_DEEMPHASIS |SPEED_GEN3 , + pci->dbi_base + offset +PCI_EXP_DEVCTL2 );Quoted 8 lines
Quoted 4 lines
Quoted 1 line
Doesn't this overwrite the prior register write?
It does. There are two mistakes here. The
writel()above should setPCIE20_DEVICE_CONTROL2_STATUS2(offset0x98).No. Did you check what 'offset' is?
PCIE20_DEVICE_CONTROL2_STATUS2isPCI_EXP_DEVCTL2plus the status reg. What's wrong is it should be a 16-bit write.
Quoted 6 lines
Thanks for enlightening me. 'offset' is
0x70here. SoPCI_EXP_DEVCTL2is at0x98, andPCI_EXP_LNKCTL2is at0xa0. Only the secondwritel()is wrong. But since generic code handles speed, I can drop it entirely.I see that
dw_pcie_link_set_max_speed()usesdw_pcie_writel_dbi()to write toPCI_EXP_LNKCTL2. Is that 16-bit write?
No, that may be because some platforms can only do 32-bit accesses and dw_pcie_writew_dbi would be a RMW in that case. Or maybe there's some reliance on clearing the status register.
Quoted 1 line
Why are
pci_regs.hregister offsets in decimal?
No idea...
Rob
Re: [PATCH v2 2/6] PCI: qcom: add support for IPQ60xx PCIe controller
Quoted 5 lines · Rob Herring
Quoted 1 line · Baruch Siach
Why are
pci_regs.hregister offsets in decimal?No idea...
That does seem confusing and error prone. I'd merge a patch that made them hex to match the spec.
Re: [PATCH v2 2/6] PCI: qcom: add support for IPQ60xx PCIe controller
In reply to Baruch SiachIn subject:
s/add support/Add support/ to match previous history.
Quoted 8 lines · Baruch Siach
From: Selvam Sathappan Periakaruppan <[email protected]>
IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that platform.
The code is based on downstream Codeaurora kernel v5.4. Split out the DBI registers access part from .init into .post_init. DBI registers are only accessible after
phy_power_on().
The "downstream Codeaurora kernel v5.4" reference would be more useful if there were a URL reference to that driver.
drivers/pci/controller/dwc/pcie-qcom.c line 106
Quoted 2 lines
drivers/pci/controller/dwc/pcie-qcom.c +2
-0+#define AXI_CLK_RATE 200000000 +#define RCHNG_CLK_RATE 100000000
These are unused.
drivers/pci/controller/dwc/pcie-qcom.c static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) · line 1402
Quoted 1 line
drivers/pci/controller/dwc/pcie-qcom.c +1
-0+for (i =0 ;i <256 ;i++)
Add spaces after semicolons.
PATCH v2 3/6 phy: qcom-qmp: add QMP V2 PCIe PHY support for ipq60xx
In reply to Baruch SiachFrom: Selvam Sathappan Periakaruppan <[email protected]>
Based on code from downstream Codeaurora tree. The ipq60xx has one gen3 PCIe port.
--- drivers/phy/qualcomm/phy-qcom-qmp.c | 147 ++++++++++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 132 +++++++++++++++++++++++++ 2 files changed, 279 insertions(+)
drivers/phy/qualcomm/phy-qcom-qmp.c +147 -0
@@ -143,6 +143,13 @@ static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_READY_STATUS] = 0x168, }; +static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE ] = { + [QPHY_SW_RESET ] =0x00 , + [QPHY_START_CTRL ] =0x44 , + [QPHY_PCS_STATUS ] =0x14 , + [QPHY_PCS_POWER_DOWN_CONTROL ] =0x40 , +}; +static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE ] = { [QPHY_COM_SW_RESET ] =0x400 , [QPHY_COM_POWER_DOWN_CONTROL ] =0x404 ,
@@ -614,6 +621,113 @@ static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08), }; +static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_PLL_SSC_PER1 ,0x7d ), +QMP_PHY_INIT_CFG (QSERDES_PLL_SSC_PER2 ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_SSC_STEP_SIZE1_MODE0 ,0x0a ), +QMP_PHY_INIT_CFG (QSERDES_PLL_SSC_STEP_SIZE2_MODE0 ,0x05 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_SSC_STEP_SIZE1_MODE1 ,0x08 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_SSC_STEP_SIZE2_MODE1 ,0x04 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_BIAS_EN_CLKBUFLR_EN ,0x18 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_CLK_ENABLE1 ,0x90 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_SYS_CLK_CTRL ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_SYSCLK_BUF_ENABLE ,0x07 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_PLL_IVCO ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_PLL_LOCK_CMP1_MODE0 ,0xd4 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_LOCK_CMP2_MODE0 ,0x14 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_LOCK_CMP1_MODE1 ,0xaa ), +QMP_PHY_INIT_CFG (QSERDES_PLL_LOCK_CMP2_MODE1 ,0x29 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_BG_TRIM ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_PLL_CP_CTRL_MODE0 ,0x09 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_CP_CTRL_MODE1 ,0x09 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_PLL_RCTRL_MODE0 ,0x16 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_PLL_RCTRL_MODE1 ,0x16 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_PLL_CCTRL_MODE0 ,0x28 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_PLL_CCTRL_MODE1 ,0x28 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_BIAS_EN_CTRL_BY_PSM ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_SYSCLK_EN_SEL ,0x08 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_RESETSM_CNTRL ,0x20 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_LOCK_CMP_EN ,0x42 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_DEC_START_MODE0 ,0x68 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_DEC_START_MODE1 ,0x53 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_DIV_FRAC_START1_MODE0 ,0xab ), +QMP_PHY_INIT_CFG (QSERDES_PLL_DIV_FRAC_START2_MODE0 ,0xaa ), +QMP_PHY_INIT_CFG (QSERDES_PLL_DIV_FRAC_START3_MODE0 ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_DIV_FRAC_START1_MODE1 ,0x55 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_DIV_FRAC_START2_MODE1 ,0x55 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_DIV_FRAC_START3_MODE1 ,0x05 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 ,0xa0 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 ,0xa0 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_VCO_TUNE1_MODE0 ,0x24 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_VCO_TUNE2_MODE0 ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_VCO_TUNE1_MODE1 ,0xb4 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_VCO_TUNE2_MODE1 ,0x03 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_CLK_SELECT ,0x32 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_HSCLK_SEL ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_CORE_CLK_EN ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_CMN_CONFIG ,0x06 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_SVS_MODE_CLK_SEL ,0x05 ), +QMP_PHY_INIT_CFG (QSERDES_PLL_CORECLK_DIV_MODE1 ,0x08 ), +}; + +static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_TX0_RES_CODE_LANE_OFFSET_TX ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_TX0_LANE_MODE_1 ,0x06 ), +QMP_PHY_INIT_CFG (QSERDES_TX0_RCV_DETECT_LVL_2 ,0x12 ), +}; + +static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_RX0_UCDR_FO_GAIN ,0x0c ), +QMP_PHY_INIT_CFG (QSERDES_RX0_UCDR_SO_GAIN ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE ,0x7f ), +QMP_PHY_INIT_CFG (QSERDES_RX0_UCDR_PI_CONTROLS ,0x70 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 ,0x61 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 ,0x04 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 ,0x1e ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_IDAC_TSETTLE_LOW ,0xc0 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_IDAC_TSETTLE_HIGH ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 ,0x73 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 ,0x80 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_SIGDET_ENABLES ,0x1c ), +QMP_PHY_INIT_CFG (QSERDES_RX0_SIGDET_CNTRL ,0x03 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_SIGDET_DEGLITCH_CNTRL ,0x14 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_MODE_00_LOW ,0xf0 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_MODE_00_HIGH ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_MODE_00_HIGH2 ,0x2f ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_MODE_00_HIGH3 ,0xd3 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_MODE_00_HIGH4 ,0x40 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_MODE_01_LOW ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_MODE_01_HIGH ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_MODE_01_HIGH2 ,0xc8 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_MODE_01_HIGH3 ,0x09 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_MODE_01_HIGH4 ,0xb1 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_MODE_10_LOW ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_MODE_10_HIGH ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_MODE_10_HIGH2 ,0xc8 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_MODE_10_HIGH3 ,0x09 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_RX_MODE_10_HIGH4 ,0xb1 ), +QMP_PHY_INIT_CFG (QSERDES_RX0_DFE_EN_TIMER ,0x04 ), +}; + +static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { +QMP_PHY_INIT_CFG (PCS_COM_FLL_CNTRL1 ,0x01 ), +QMP_PHY_INIT_CFG (PCS_COM_REFGEN_REQ_CONFIG1 ,0x0d ), +QMP_PHY_INIT_CFG (PCS_COM_G12S1_TXDEEMPH_M3P5DB ,0x10 ), +QMP_PHY_INIT_CFG (PCS_COM_RX_SIGDET_LVL ,0xaa ), +QMP_PHY_INIT_CFG (PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L ,0x01 ), +QMP_PHY_INIT_CFG (PCS_COM_RX_DCC_CAL_CONFIG ,0x01 ), +QMP_PHY_INIT_CFG (PCS_COM_EQ_CONFIG5 ,0x01 ), +QMP_PHY_INIT_CFG (PCS_PCIE_POWER_STATE_CONFIG2 ,0x0d ), +QMP_PHY_INIT_CFG (PCS_PCIE_POWER_STATE_CONFIG4 ,0x07 ), +QMP_PHY_INIT_CFG (PCS_PCIE_ENDPOINT_REFCLK_DRIVE ,0xc1 ), +QMP_PHY_INIT_CFG (PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L ,0x01 ), +QMP_PHY_INIT_CFG (PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L ,0x01 ), +QMP_PHY_INIT_CFG (PCS_PCIE_OSC_DTCT_ACTIONS ,0x00 ), +QMP_PHY_INIT_CFG (PCS_PCIE_EQ_CONFIG1 ,0x11 ), +QMP_PHY_INIT_CFG (PCS_PCIE_PRESET_P10_PRE ,0x00 ), +QMP_PHY_INIT_CFG (PCS_PCIE_PRESET_P10_POST ,0x58 ), +}; +static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {QMP_PHY_INIT_CFG (QSERDES_COM_BIAS_EN_CLKBUFLR_EN ,0x18 ),QMP_PHY_INIT_CFG (QSERDES_COM_CLK_ENABLE1 ,0x10 ),
@@ -2646,6 +2760,36 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { .pwrdn_delay_max = 1005, /* us */ }; +static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { + .type =PHY_TYPE_PCIE , + .nlanes =1 , + + .serdes_tbl = ipq6018_pcie_serdes_tbl, + .serdes_tbl_num =ARRAY_SIZE (ipq6018_pcie_serdes_tbl), + .tx_tbl = ipq6018_pcie_tx_tbl, + .tx_tbl_num =ARRAY_SIZE (ipq6018_pcie_tx_tbl), + .rx_tbl = ipq6018_pcie_rx_tbl, + .rx_tbl_num =ARRAY_SIZE (ipq6018_pcie_rx_tbl), + .pcs_tbl = ipq6018_pcie_pcs_tbl, + .pcs_tbl_num =ARRAY_SIZE (ipq6018_pcie_pcs_tbl), + .clk_list = ipq8074_pciephy_clk_l, + .num_clks =ARRAY_SIZE (ipq8074_pciephy_clk_l), + .reset_list = ipq8074_pciephy_reset_l, + .num_resets =ARRAY_SIZE (ipq8074_pciephy_reset_l), + .vreg_list =NULL , + .num_vregs =0 , + .regs = ipq_pciephy_gen3_regs_layout, + + .start_ctrl =SERDES_START |PCS_START , + .pwrdn_ctrl =SW_PWRDN |REFCLK_DRV_DSBL , + + .has_phy_com_ctrl = false, + .has_lane_rst = false, + .has_pwrdn_delay = true, + .pwrdn_delay_min =995 ,/* us */ + .pwrdn_delay_max =1005 ,/* us */ +}; +static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { .type =PHY_TYPE_PCIE , .nlanes =1 ,
@@ -4532,6 +4676,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }, { .compatible = "qcom,ipq8074-qmp-pcie-phy", .data = &ipq8074_pciephy_cfg, + }, { + .compatible = "qcom,ipq6018-qmp-pcie-phy", + .data = &ipq6018_pciephy_cfg, }, { .compatible = "qcom,sc7180-qmp-usb3-phy", .data = &sc7180_usb3phy_cfg,
drivers/phy/qualcomm/phy-qcom-qmp.h +132 -0
138 lines not on this page · raw message
Signature · 1 line
2.30.2
Re: [PATCH v2 3/6] phy: qcom-qmp: add QMP V2 PCIe PHY support for ipq60xx
Quoted 4 lines · Baruch Siach
From: Selvam Sathappan Periakaruppan <[email protected]>
Based on code from downstream Codeaurora tree. The ipq60xx has one gen3 PCIe port.
Applied, thanks
Signature · 1 line
~Vinod
PATCH v2 4/6 arm64: dts: ipq6018: Add pcie support
In reply to Baruch SiachFrom: Selvam Sathappan Periakaruppan <[email protected]>
ipq6018 has 1 pcie gen3 port. This patch adds the support for the same.
The GICv2m reg property value is a guess based on similar SoCs description in downstream Codeaurora kernel. It appears to work.
[baruch: adjust #address-cells/#size-cells; drop unsupported property;
increase parf registers size]
---
v2: remove 'msi-parent'; doesn't really work
--- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 99 +++++++++++++++++++++++++++ 1 file changed, 99 insertions(+)
arch/arm64/boot/dts/qcom/ipq6018.dtsi +99 -0
@@ -384,6 +384,105 @@ intc: interrupt-controller@b000000 { interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + pcie_phy: phy@84000 { + compatible = "qcom,ipq6018-qmp-pcie-phy"; + reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */ + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", + "common"; + + pcie_phy0: lane@84200 { + reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */ + <0x0 0x84400 0x0 0x200>, /* Serdes Rx */ + <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */ + #phy-cells = <0>; + + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_pcie0_pipe_clk_src"; + #clock-cells = <0>; + }; + }; + + pcie0: pci@20000000 { + compatible = "qcom,pcie-ipq6018"; + reg = <0x0 0x20000000 0x0 0xf1d>, + <0x0 0x20000f20 0x0 0xa8>, + <0x0 0x20001000 0x0 0x1000>, + <0x0 0x80000 0x0 0x4000>, + <0x0 0x20100000 0x0 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + phys = <&pcie_phy0>; + phy-names = "pciephy"; + + ranges = <0x81000000 0 0x20200000 0 0x20200000 + 0 0x10000>, /* downstream I/O */ + <0x82000000 0 0x20220000 0 0x20220000 + 0 0xfde0000>; /* non-prefetchable memory */ + + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 75 + IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 78 + IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 79 + IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 83 + IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, + <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc PCIE0_RCHNG_CLK>; + clock-names = "iface", + "axi_m", + "axi_s", + "axi_bridge", + "rchng"; + + resets = <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_SLEEP_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; + reset-names = "pipe", + "sleep", + "sticky", + "axi_m", + "axi_s", + "ahb", + "axi_m_sticky", + "axi_s_sticky"; + + status = "disabled"; + }; + watchdog@b017000 { compatible = "qcom,kpss-wdt"; interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
Signature · 1 line
2.30.2
PATCH v2 5/6 dt-bindings: phy: qcom, qmp: Add IPQ60xx PCIe PHY bindings
In reply to Baruch SiachAdd ipq6018 qmp phy device for the single PCIe serdes lane on IPQ60xx SoCs.
--- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+)
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +25 -0
@@ -17,6 +17,7 @@ description: properties: compatible: enum: + - qcom,ipq6018-qmp-pcie-phy - qcom,ipq8074-qmp-pcie-phy - qcom,ipq8074-qmp-usb3-phy - qcom,msm8996-qmp-pcie-phy
@@ -294,6 +295,30 @@ allOf: items: - const: phy - const: common + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq6018-qmp-pcie-phy + then: + properties: + clocks: + items: + - description: Phy aux clock. + - description: Phy config clock. + clock-names: + items: + - const: aux + - const: cfg_ahb + resets: + items: + - description: reset of phy block. + - description: phy common block reset. + reset-names: + items: + - const: phy + - const: common - if: properties: compatible:
Signature · 1 line
2.30.2
Re: [PATCH v2 5/6] dt-bindings: phy: qcom,qmp: Add IPQ60xx PCIe PHY bindings
Quoted 2 lines · Baruch Siach
Add ipq6018 qmp phy device for the single PCIe serdes lane on IPQ60xx SoCs.
Applied, thanks
Signature · 1 line
~Vinod
PATCH v2 6/6 dt-bindings: pci: qcom: Document PCIe bindings for IPQ6018 SoC
In reply to Baruch SiachDocument qcom,pcie-ipq6018. This is similar to the ipq8074 with a few different clock sources, and one additional reset.
--- .../devicetree/bindings/pci/qcom,pcie.txt | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+)
Documentation/devicetree/bindings/pci/qcom,pcie.txt +24 -0
@@ -14,6 +14,7 @@ - "qcom,pcie-qcs404" for qcs404 - "qcom,pcie-sdm845" for sdm845 - "qcom,pcie-sm8250" for sm8250 + - "qcom,pcie-ipq6018" for ipq6018 - reg: Usage: required
@@ -123,6 +124,16 @@ - "ahb" AHB clock - "aux" Auxiliary clock +- clock-names: + Usage: required for ipq6018 + Value type: <stringlist> + Definition: Should contain the following entries + - "iface" PCIe to SysNOC BIU clock + - "axi_m" AXI Master clock + - "axi_s" AXI Slave clock + - "axi_bridge" AXI bridge clock + - "rchng" + - clock-names: Usage: required for qcs404 Value type: <stringlist>
@@ -209,6 +220,19 @@ - "ahb" AHB Reset - "axi_m_sticky" AXI Master Sticky reset +- reset-names: + Usage: required for ipq6018 + Value type: <stringlist> + Definition: Should contain the following entries + - "pipe" PIPE reset + - "sleep" Sleep reset + - "sticky" Core Sticky reset + - "axi_m" AXI Master reset + - "axi_s" AXI Slave reset + - "ahb" AHB Reset + - "axi_m_sticky" AXI Master Sticky reset + - "axi_s_sticky" AXI Slave Sticky reset + - reset-names: Usage: required for qcs404 Value type: <stringlist>
Signature · 1 line
2.30.2
Re: [PATCH v2 6/6] dt-bindings: pci: qcom: Document PCIe bindings for IPQ6018 SoC
Quoted 2 lines · Baruch Siach
Document qcom,pcie-ipq6018. This is similar to the ipq8074 with a few different clock sources, and one additional reset.
Applied, thanks
Signature · 1 line
~Vinod
Hi Lorenzo, Rob, Krzysztof,
Quoted 6 lines · Baruch Siach
This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires
phy_power_on().Tested on IPQ6010 based hardware.
It's been 3 months with no comment. Would you consider applying the dwc part (patches #1 and #2) for the v5.15 merge window?
I tested the patches here successfully on top of v5.14-rc4.
Thanks,
baruch
Quoted 32 lines
Changes in v2:
* Add patch moving
GEN3_RELATEDmacros to a common header* Drop ATU configuration from pcie-qcom
* Remove local definition of common registers
* Use bulk clk and reset APIs
* Remove msi-parent from device-tree
Baruch Siach (3):
PCI: dwc: tegra: moveGEN3_RELATEDDBI register to common header
dt-bindings: phy: qcom,qmp: Add IPQ60xx PCIe PHY bindings
dt-bindings: pci: qcom: Document PCIe bindings for IPQ6018 SoCSelvam Sathappan Periakaruppan (3):
PCI: qcom: add support for IPQ60xx PCIe controller
phy: qcom-qmp: add QMP V2 PCIe PHY support for ipq60xx
arm64: dts: ipq6018: Add pcie support.../devicetree/bindings/pci/qcom,pcie.txt | 24 +++ .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 25 +++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 99 ++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 7 + drivers/pci/controller/dwc/pcie-qcom.c | 150 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-tegra194.c | 6 - drivers/phy/qualcomm/phy-qcom-qmp.c | 147 +++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 132 +++++++++++++++ 8 files changed, 584 insertions(+), 6 deletions(-)
Signature · 3 lines
~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- [email protected] - tel: +972.52.368.4656, http://www.tkos.co.il -Quoted 8 lines · Baruch Siach
Hi Lorenzo, Rob, Krzysztof,
Quoted 5 lines · Baruch Siach
This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires
phy_power_on().
Quoted 6 lines
Quoted 1 line
Tested on IPQ6010 based hardware.
It's been 3 months with no comment. Would you consider applying the dwc part (patches #1 and #2) for the v5.15 merge window?
I tested the patches here successfully on top of v5.14-rc4.
You need an ACK from the respective drivers maintainers. We look into overall pci/controller drivers structure and common code, it is up to drivers maintainers to review and ACK your patches, I will certainly pick them up when that's done.
Thanks,
Lorenzo
Quoted 41 lines
Thanks,
baruchQuoted 32 lines
Changes in v2:
* Add patch moving
GEN3_RELATEDmacros to a common header* Drop ATU configuration from pcie-qcom
* Remove local definition of common registers
* Use bulk clk and reset APIs
* Remove msi-parent from device-tree
Baruch Siach (3):
PCI: dwc: tegra: moveGEN3_RELATEDDBI register to common header
dt-bindings: phy: qcom,qmp: Add IPQ60xx PCIe PHY bindings
dt-bindings: pci: qcom: Document PCIe bindings for IPQ6018 SoCSelvam Sathappan Periakaruppan (3):
PCI: qcom: add support for IPQ60xx PCIe controller
phy: qcom-qmp: add QMP V2 PCIe PHY support for ipq60xx
arm64: dts: ipq6018: Add pcie support.../devicetree/bindings/pci/qcom,pcie.txt | 24 +++ .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 25 +++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 99 ++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 7 + drivers/pci/controller/dwc/pcie-qcom.c | 150 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-tegra194.c | 6 - drivers/phy/qualcomm/phy-qcom-qmp.c | 147 +++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 132 +++++++++++++++ 8 files changed, 584 insertions(+), 6 deletions(-)Signature · 3 lines
~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{= - [email protected] - tel: +972.52.368.4656, http://www.tkos.co.il -
Vinod Koul
maintainerQuoted 14 lines · Lorenzo Pieralisi
Quoted 13 lines · Baruch Siach
Hi Lorenzo, Rob, Krzysztof,
Quoted 6 lines · Baruch Siach
This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires
phy_power_on().Tested on IPQ6010 based hardware.
It's been 3 months with no comment. Would you consider applying the dwc part (patches #1 and #2) for the v5.15 merge window?
Quoted 6 lines
Quoted 1 line
I tested the patches here successfully on top of v5.14-rc4.
You need an ACK from the respective drivers maintainers. We look into overall pci/controller drivers structure and common code, it is up to drivers maintainers to review and ACK your patches, I will certainly pick them up when that's done.
Also is there any dependency b/w various pieces, if not consider sending patches to respective subsystems...
Too many patch series these days are adding cross subsystem stuff even if there are no dependencies. Yes it all needs to come together to work but that does not require a common series to be posted!
Signature · 6 lines
~Vinod -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy