PCI: IPQ6018 platform support

From: Baruch Siach <[email protected]>

The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better describe its meaning.

Signed-off-by Baruch Siach <[email protected]>

---
v7:
Use FIELD_PREP for power limit and stale (Pali Rohár)

---
 drivers/pci/controller/dwc/pcie-qcom.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

From: Baruch Siach <[email protected]>

The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better describe its meaning.

Signed-off-by Baruch Siach <[email protected]>

---
v7:
Use FIELD_PREP for power limit and stale (Pali Rohár)

---
 drivers/pci/controller/dwc/pcie-qcom.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

From: Selvam Sathappan Periakaruppan <[email protected]>

IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that platform.

The code is based on downstream[1] Codeaurora kernel v5.4 (branch win.linuxopenwrt.2.0).

Split out the DBI registers access part from .init into .post_init. DBI registers are only accessible after phy_power_on().

[1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/

Signed-off-by Selvam Sathappan Periakaruppan <[email protected]>

Signed-off-by Baruch Siach <[email protected]>

---
v7:

* Rebase on v5.19-rc1 (Bjorn Helgaas)

v6:

Address Bjorn Helgaas comments:

* Rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL

* Drop a vague comment about ASPM configuration

* Add a comment about the source of delay periods

v5:

* Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)

v4:

* Rebase on v5.16-rc1

v3:
* Drop speed setup; rely on generic code (Rob Herring)

* Drop unused CLK_RATE macros (Bjorn Helgaas)

* Minor formatting fixes (Bjorn Helgaas)

* Add reference to downstream Codeaurora kernel tree (Bjorn Helgaas)

v2:
* Drop ATU configuration; rely on common code instead

* Use more common register macros

* Use bulk clk and reset APIs

---
 drivers/pci/controller/dwc/pcie-designware.h |   1 +
 drivers/pci/controller/dwc/pcie-qcom.c       | 140 +++++++++++++++++++
 2 files changed, 141 insertions(+)

From: Selvam Sathappan Periakaruppan <[email protected]>

IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that platform.

The code is based on downstream[1] Codeaurora kernel v5.4 (branch win.linuxopenwrt.2.0).

Split out the DBI registers access part from .init into .post_init. DBI registers are only accessible after phy_power_on().

[1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/

Signed-off-by Selvam Sathappan Periakaruppan <[email protected]>

Signed-off-by Baruch Siach <[email protected]>

From: Selvam Sathappan Periakaruppan <[email protected]>

IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that platform.

The code is based on downstream[1] Codeaurora kernel v5.4 (branch win.linuxopenwrt.2.0).

Split out the DBI registers access part from .init into .post_init. DBI registers are only accessible after phy_power_on().

[1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/

Signed-off-by Selvam Sathappan Periakaruppan <[email protected]>

Signed-off-by Baruch Siach <[email protected]>

---

drivers/pci/controller/dwc/pcie-qcom.c +51 -0

+}
+
+static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
+{
+	struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
+	struct device *dev = pcie->pci->dev;
+	int ret;
+
+	ret = reset_control_assert(res->rst);
+	if (ret) {
+		dev_err(dev, "reset assert failed (%d)\n", ret);
+		return ret;
+	}
+
+	/*
+	 * Delay periods before and after reset deassert are working values
+	 * from downstream Codeaurora kernel
+	 */
+	usleep_range(2000, 2500);
+
+	ret = reset_control_deassert(res->rst);
+	if (ret) {
+		dev_err(dev, "reset deassert failed (%d)\n", ret);
+		return ret;
+	}
+
+	usleep_range(2000, 2500);
+
+	ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
+	if (ret)
+		goto err_reset;
+
+	return 0;
+
+err_reset:
+	reset_control_assert(res->rst);
+
+	return ret;
+}
+
+static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
+{
+	struct dw_pcie *pci = pcie->pci;
+	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+	u32 val;
+	int i;
+
+	writel(SLV_ADDR_SPACE_SZ,
+		pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
+
+	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);

drivers/pci/controller/dwc/pcie-qcom.c +8 -0

+		AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
+		pcie->parf + PCIE20_PARF_SYS_CTRL);
+
+	writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
+
+	dw_pcie_dbi_ro_wr_en(pci);
+	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
+

Quoted 16 lines · Baruch Siach

From: Selvam Sathappan Periakaruppan <[email protected]>

IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that platform.

The code is based on downstream[1] Codeaurora kernel v5.4 (branch win.linuxopenwrt.2.0).

Split out the DBI registers access part from .init into .post_init. DBI registers are only accessible after phy_power_on().

[1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/

Signed-off-by Selvam Sathappan Periakaruppan <[email protected]>

Signed-off-by Baruch Siach <[email protected]>

---

drivers/pci/controller/dwc/pcie-qcom.c static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) · line 1356

Quoted 5 lines

drivers/pci/controller/dwc/pcie-qcom.c +5 -0

+static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
+{
+	struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
+
+	clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);

Assert reset as you do in the init error path?

Quoted 51 lines

drivers/pci/controller/dwc/pcie-qcom.c +51 -0

+}
+
+static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
+{
+	struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
+	struct device *dev = pcie->pci->dev;
+	int ret;
+
+	ret = reset_control_assert(res->rst);
+	if (ret) {
+		dev_err(dev, "reset assert failed (%d)\n", ret);
+		return ret;
+	}
+
+	/*
+	 * Delay periods before and after reset deassert are working values
+	 * from downstream Codeaurora kernel
+	 */
+	usleep_range(2000, 2500);
+
+	ret = reset_control_deassert(res->rst);
+	if (ret) {
+		dev_err(dev, "reset deassert failed (%d)\n", ret);
+		return ret;
+	}
+
+	usleep_range(2000, 2500);
+
+	ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
+	if (ret)
+		goto err_reset;
+
+	return 0;
+
+err_reset:
+	reset_control_assert(res->rst);
+
+	return ret;
+}
+
+static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
+{
+	struct dw_pcie *pci = pcie->pci;
+	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+	u32 val;
+	int i;
+
+	writel(SLV_ADDR_SPACE_SZ,
+		pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
+
+	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);

drivers/pci/controller/dwc/pcie-qcom.c static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) · line 1417

Quoted 10 lines

drivers/pci/controller/dwc/pcie-qcom.c +10 -0

+	val &= ~BIT(0);
+	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
+	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
+
+	writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
+	writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
+		pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
+	writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS
+		| GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,

I noticed that some of this probably has been copied from from qcom_pcie_init_2_3_3(), but please move the | operator to the previous line.

drivers/pci/controller/dwc/pcie-qcom.c static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) · line 1421

Quoted 4 lines

drivers/pci/controller/dwc/pcie-qcom.c +4 -0

+		pci->dbi_base + GEN3_RELATED_OFF);
+
+	writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
+		| SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |

Same here.

Quoted 8 lines

drivers/pci/controller/dwc/pcie-qcom.c +8 -0

+		AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
+		pcie->parf + PCIE20_PARF_SYS_CTRL);
+
+	writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
+
+	dw_pcie_dbi_ro_wr_en(pci);
+	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
+

drivers/pci/controller/dwc/pcie-qcom.c static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) · line 1439

Quoted 10 lines

drivers/pci/controller/dwc/pcie-qcom.c +10 -0

+	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
+	val &= ~PCI_EXP_LNKCAP_ASPMS;
+	writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
+
+	writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
+			PCI_EXP_DEVCTL2);
+
+	for (i = 0; i < 256; i++)
+		writel(0x0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N
+				+ (4 * i));

And here for +, but you should probably just remove the line break (you can go up to 100 chars if it makes the code more readable).

Please drop the 0x prefix too.

drivers/pci/controller/dwc/pcie-qcom.c static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) · line 1350

Quoted 3 lines

drivers/pci/controller/dwc/pcie-qcom.c +3 -0

+
+	return 0;
+}

Johan

Hi Johan,

Thanks for your review comments.

Quoted 18 lines · Johan Hovold

Quoted 16 lines · Baruch Siach

From: Selvam Sathappan Periakaruppan <[email protected]>

IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that platform.

The code is based on downstream[1] Codeaurora kernel v5.4 (branch win.linuxopenwrt.2.0).

Split out the DBI registers access part from .init into .post_init. DBI registers are only accessible after phy_power_on().

[1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/

Signed-off-by Selvam Sathappan Periakaruppan <[email protected]>

Signed-off-by Baruch Siach <[email protected]>

---

Quoted 7 lines

drivers/pci/controller/dwc/pcie-qcom.c static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) · line 1356

Quoted 5 lines

drivers/pci/controller/dwc/pcie-qcom.c +5 -0

+static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
+{
+	struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
+
+	clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);

Assert reset as you do in the init error path?

Not sure about that. As I understand, the reset assert/deassert sequence on init is meant to ensure clean startup state. Deinit most likely does not need that. So maybe I should remove reset assert from init error path instead?

As always, this code sequence is from downstream kernel. I have no access to documentation.