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Add definitions for AST2600 i3c clocks and resets

PATCH Superseded Jeremy Kerr 2 participants 9 messages Feb 13, 2023

Subsystems (2)
Device tree bindings Common clk

v3 of 5 Superseded Latest is v5 →

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Jeremy Kerr

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#0 lore raw

v3 cover Add definitions for AST2600 i3c clocks and resets

This series adds some base configuration for the i3c controllers on ast2600 hardware. We'll use the reset and clock definitions in the proposed dt binding example, hence sending these first.

v3:
- split dt-bindings from clk changes
- unify subject prefixes
v2:
- based on feedback from Joel Stanley: avoid adding RESERVED clock definitions, allowing empty entries in aspeed_g6_gates instead.

Jeremy Kerr (5):
clk: ast2600: allow empty entries in aspeed_g6_gates
dt-bindings: clock: ast2600: Add top-level I3C clock
clk: ast2600: Add full configs for I3C clocks
dt-bindings: clock: ast2600: remove IC36 & I3C7 clock definitions
dt-bindings: clock: ast2600: Add reset config for I3C

 drivers/clk/clk-ast2600.c                 | 41 ++++++++++++++++++-----
 include/dt-bindings/clock/ast2600-clock.h |  9 +++--
 2 files changed, 40 insertions(+), 10 deletions(-)
Signature · 1 line
2.39.1
author
#1 lore raw

PATCH v3 1/5 clk: ast2600: allow empty entries in aspeed_g6_gates

We're about to remove an entry from aspeed_g6_gates, but we won't want to alter/reorder existing entries. Allow empty entries in this array.

Signed-off-by Jeremy Kerr <[email protected]>

---
v3:
- reword commit message

---
 drivers/clk/clk-ast2600.c | 3 +++
 1 file changed, 3 insertions(+)
drivers/clk/clk-ast2600.c +3 -0
index 9c3305bcb27a..1f08ff3c60fa 100644
@@ -652,6 +652,9 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
 		const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
 		u32 gate_flags;
 
+		if (!gd->name)
+			continue;
+
 		/*
 		 * Special case: the USB port 1 clock (bit 14) is always
 		 * working the opposite way from the other ones.
Signature · 1 line
2.39.1
author
#2 lore raw

PATCH v3 2/5 dt-bindings: clock: ast2600: Add top-level I3C clock

In reply to Jeremy Kerr

The ast2600 hardware has a top-level clock for all i3c controller peripherals (then gated to each individual controller), so add a top-level i3c clock line to control this.

This is a partial cherry-pick and rework of ed44b8cdfdb and 1a35eb926d7 from Aspeed's own tree, originally by Dylan Hung <[email protected]>.

Signed-off-by Jeremy Kerr <[email protected]>

---
v3:
- split into separate bindings & clk changes
v2:
- reword commit message

---
 include/dt-bindings/clock/ast2600-clock.h | 1 +
 1 file changed, 1 insertion(+)
include/dt-bindings/clock/ast2600-clock.h +1 -0
index d8b0db2f7a7d..608ce576e63e 100644
@@ -87,6 +87,7 @@
 #define ASPEED_CLK_MAC2RCLK		68
 #define ASPEED_CLK_MAC3RCLK		69
 #define ASPEED_CLK_MAC4RCLK		70
+#define ASPEED_CLK_I3C			74
 
 /* Only list resets here that are not part of a gate */
 #define ASPEED_RESET_ADC		55
Signature · 1 line
2.39.1
author
#4 lore raw

PATCH v3 3/5 clk: ast2600: Add full configs for I3C clocks

In reply to Jeremy Kerr

The current ast2600 I3C clock definitions are top-level (rather than based on their actual hw sources: either HCLK or APLL), and include a couple of definitions for (non-existent) i3c6 and i3c7.

Re-parent the individual I3C controller clocks to the main i3c clock, explicitly sourced from the APLL rather than whatever G6_CLK_SELECTION5 was last set to.

While we're at it, remove the definitions for the i3c6 and i3c7 clock lines; this hardware isn't present.

This is a partial cherry-pick and rework of ed44b8cdfdb and 1a35eb926d7 from Aspeed's own tree, originally by Dylan Hung <[email protected]>.

Signed-off-by Jeremy Kerr <[email protected]>

---
v3:
- split dt-bindings and clk changes
v2:
- reword commit message

---
 drivers/clk/clk-ast2600.c | 38 ++++++++++++++++++++++++++++++--------
 1 file changed, 30 insertions(+), 8 deletions(-)
drivers/clk/clk-ast2600.c +30 -8
index 1f08ff3c60fa..45549cb18107 100644
@@ -4,6 +4,7 @@
 
 #define pr_fmt(fmt) "clk-ast2600: " fmt
 
+#include <linux/bitfield.h>
 #include <linux/mfd/syscon.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>

@@ -32,6 +33,18 @@
 #define ASPEED_G6_CLK_SELECTION1	0x300
 #define ASPEED_G6_CLK_SELECTION2	0x304
 #define ASPEED_G6_CLK_SELECTION4	0x310
+#define ASPEED_G6_CLK_SELECTION5	0x314
+#define   I3C_CLK_SELECTION		BIT(31)
+#define     I3C_CLK_SELECT_HCLK		0
+#define     I3C_CLK_SELECT_APLL_DIV	1
+#define   APLL_DIV_SELECTION		GENMASK(30, 28)
+#define     APLL_DIV_2			0b001
+#define     APLL_DIV_3			0b010
+#define     APLL_DIV_4			0b011
+#define     APLL_DIV_5			0b100
+#define     APLL_DIV_6			0b101
+#define     APLL_DIV_7			0b110
+#define     APLL_DIV_8			0b111
 
 #define ASPEED_HPLL_PARAM		0x200
 #define ASPEED_APLL_PARAM		0x210

@@ -97,14 +110,13 @@ static const struct aspeed_gate_data aspeed_g6_gates[] = {
 	[ASPEED_CLK_GATE_LHCCLK]	= { 37, -1, "lhclk-gate",	"lhclk", 0 },	/* LPC master/LPC+ */
 	/* Reserved 38 RSA: no longer used */
 	/* Reserved 39 */
-	[ASPEED_CLK_GATE_I3C0CLK]	= { 40,  40, "i3c0clk-gate",	NULL,	 0 },	/* I3C0 */
-	[ASPEED_CLK_GATE_I3C1CLK]	= { 41,  41, "i3c1clk-gate",	NULL,	 0 },	/* I3C1 */
-	[ASPEED_CLK_GATE_I3C2CLK]	= { 42,  42, "i3c2clk-gate",	NULL,	 0 },	/* I3C2 */
-	[ASPEED_CLK_GATE_I3C3CLK]	= { 43,  43, "i3c3clk-gate",	NULL,	 0 },	/* I3C3 */
-	[ASPEED_CLK_GATE_I3C4CLK]	= { 44,  44, "i3c4clk-gate",	NULL,	 0 },	/* I3C4 */
-	[ASPEED_CLK_GATE_I3C5CLK]	= { 45,  45, "i3c5clk-gate",	NULL,	 0 },	/* I3C5 */
-	[ASPEED_CLK_GATE_I3C6CLK]	= { 46,  46, "i3c6clk-gate",	NULL,	 0 },	/* I3C6 */
-	[ASPEED_CLK_GATE_I3C7CLK]	= { 47,  47, "i3c7clk-gate",	NULL,	 0 },	/* I3C7 */
+	[ASPEED_CLK_GATE_I3C0CLK]	= { 40,  40, "i3c0clk-gate",	"i3cclk", 0 }, /* I3C0 */
+	[ASPEED_CLK_GATE_I3C1CLK]	= { 41,  41, "i3c1clk-gate",	"i3cclk", 0 }, /* I3C1 */
+	[ASPEED_CLK_GATE_I3C2CLK]	= { 42,  42, "i3c2clk-gate",	"i3cclk", 0 }, /* I3C2 */
+	[ASPEED_CLK_GATE_I3C3CLK]	= { 43,  43, "i3c3clk-gate",	"i3cclk", 0 }, /* I3C3 */
+	[ASPEED_CLK_GATE_I3C4CLK]	= { 44,  44, "i3c4clk-gate",	"i3cclk", 0 }, /* I3C4 */
+	[ASPEED_CLK_GATE_I3C5CLK]	= { 45,  45, "i3c5clk-gate",	"i3cclk", 0 }, /* I3C5 */
+	/* Reserved: 46 & 47 */
 	[ASPEED_CLK_GATE_UART1CLK]	= { 48,  -1, "uart1clk-gate",	"uart",	 0 },	/* UART1 */
 	[ASPEED_CLK_GATE_UART2CLK]	= { 49,  -1, "uart2clk-gate",	"uart",	 0 },	/* UART2 */
 	[ASPEED_CLK_GATE_UART3CLK]	= { 50,  -1, "uart3clk-gate",	"uart",  0 },	/* UART3 */

@@ -775,6 +787,16 @@ static void __init aspeed_g6_cc(struct regmap *map)
 	/* USB 2.0 port1 phy 40MHz clock */
 	hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
 	aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
+
+	/* i3c clock: source from apll, divide by 8 */
+	regmap_read(map, ASPEED_G6_CLK_SELECTION5, &val);
+	val &= ~(I3C_CLK_SELECTION | APLL_DIV_SELECTION);
+	val |= FIELD_PREP(I3C_CLK_SELECTION, I3C_CLK_SELECT_APLL_DIV);
+	val |= FIELD_PREP(APLL_DIV_SELECTION, APLL_DIV_8);
+	regmap_write(map, ASPEED_G6_CLK_SELECTION5, val);
+
+	hw = clk_hw_register_fixed_factor(NULL, "i3cclk", "apll", 0, 1, 8);
+	aspeed_g6_clk_data->hws[ASPEED_CLK_I3C] = hw;
 };
 
 static void __init aspeed_g6_cc_init(struct device_node *np)
Signature · 1 line
2.39.1
author
#5 lore raw

PATCH v3 4/5 dt-bindings: clock: ast2600: remove IC36 & I3C7 clock definitions

In reply to Jeremy Kerr

The current ast2600 clock definitions include entries for i3c6 and i3c7 devices, which don't exist: there are no clock control lines documented for these, and only i3c devices 0 through 5 are present.

So, remove the definitions for I3C6 and I3C7. Although this is a potential ABI-breaking change, there are no in-tree users of these, and any references would be broken anyway, as the hardware doesn't exist.

This is a partial cherry-pick and rework of ed44b8cdfdb and 1a35eb926d7 from Aspeed's own tree, originally by Dylan Hung <[email protected]>.

Signed-off-by Jeremy Kerr <[email protected]>

---
v3:
- split dt-bindings and clk changes
v2:
- reword commit message

---
 include/dt-bindings/clock/ast2600-clock.h | 2 --
 1 file changed, 2 deletions(-)
include/dt-bindings/clock/ast2600-clock.h +0 -2
index 608ce576e63e..600549d7bee8 100644
@@ -57,8 +57,6 @@
 #define ASPEED_CLK_GATE_I3C3CLK		40
 #define ASPEED_CLK_GATE_I3C4CLK		41
 #define ASPEED_CLK_GATE_I3C5CLK		42
-#define ASPEED_CLK_GATE_I3C6CLK		43
-#define ASPEED_CLK_GATE_I3C7CLK		44
 
 #define ASPEED_CLK_GATE_FSICLK		45
Signature · 1 line
2.39.1
author
#7 lore raw

PATCH v3 5/5 dt-bindings: clock: ast2600: Add reset config for I3C

In reply to Jeremy Kerr

Add reset line definitions for the AST2600 I3C block's reset inputs.

Signed-off-by Jeremy Kerr <[email protected]>

---
v2:
- reword commit message

---
 include/dt-bindings/clock/ast2600-clock.h | 6 ++++++
 1 file changed, 6 insertions(+)
include/dt-bindings/clock/ast2600-clock.h +6 -0
index 600549d7bee8..16b7389bbb9c 100644
@@ -90,6 +90,12 @@
 /* Only list resets here that are not part of a gate */
 #define ASPEED_RESET_ADC		55
 #define ASPEED_RESET_JTAG_MASTER2	54
+#define ASPEED_RESET_I3C5		45
+#define ASPEED_RESET_I3C4		44
+#define ASPEED_RESET_I3C3		43
+#define ASPEED_RESET_I3C2		42
+#define ASPEED_RESET_I3C1		41
+#define ASPEED_RESET_I3C0		40
 #define ASPEED_RESET_I3C_DMA		39
 #define ASPEED_RESET_PWM		37
 #define ASPEED_RESET_PECI		36
Signature · 1 line
2.39.1
#3 lore raw

PATCH v3 2/5 dt-bindings: clock: ast2600: Add top-level I3C clock

In reply to Jeremy Kerr
Quoted 7 lines · Jeremy Kerr

The ast2600 hardware has a top-level clock for all i3c controller peripherals (then gated to each individual controller), so add a top-level i3c clock line to control this.

This is a partial cherry-pick and rework of ed44b8cdfdb and 1a35eb926d7 from Aspeed's own tree, originally by Dylan Hung <[email protected]>.

Acked-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

#6 lore raw

PATCH v3 4/5 dt-bindings: clock: ast2600: remove IC36 & I3C7 clock definitions

In reply to Jeremy Kerr
Quoted 8 lines · Jeremy Kerr

The current ast2600 clock definitions include entries for i3c6 and i3c7 devices, which don't exist: there are no clock control lines documented for these, and only i3c devices 0 through 5 are present.

So, remove the definitions for I3C6 and I3C7. Although this is a potential ABI-breaking change, there are no in-tree users of these, and any references would be broken anyway, as the hardware doesn't exist.

Quoted 5 lines

This is a partial cherry-pick and rework of ed44b8cdfdb and 1a35eb926d7 from Aspeed's own tree, originally by Dylan Hung <[email protected]>.

Signed-off-by Jeremy Kerr <[email protected]>
Acked-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof