Add Milk-V Pioneer RISC-V board support

From: Chen Wang <[email protected]>

Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2] in a standard mATX form factor. Add minimal device
tree files for the SG2042 SOC and the Milk-V Pioneer board.

Now only support basic uart drivers to boot up into a basic console.

Thanks,
Chen

---

Changes in v4:
The patch series is based on v6.6-rc1. You can simply review or test the patches at the link [6].
- Update bindings files for sg2042 clint as per intput from reviewers:
- rename filename from sophgo,sg2042-clint-mswi/sg2042-clint-mtimer to thead,c900-aclint-mswi/thead,c900-aclint-mtimer.
- rename compatible strings accordingly.
- Update dts as per input from reviewers: don't use macro for cpus's isa properties; use new compatible strings for mtimer/mswi of clint.
- Use only one email-address for SoB.

Changes in v3 [v3]:
The patch series is based on v6.6-rc1. You can simply review or test the patches at the link [5].
- add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
- updated maintainers info. for sophgo devicetree
- remove the quirk changes for uart
- updated dts, such as:
- add "riscv,isa-base"/"riscv,isa-extensions" for cpus
- update l2 cache node's name
- remove memory and pmu nodes
- fixed other issues as per input from reviewers.

Changes in v2 [v2]:
The patch series is based on v6.6-rc1. You can simply review or test the patches at the link [4].
- Improve format for comment of commitments as per input from last review.
- Improve format of DTS as per input from last review.
- Remove numa related stuff from DTS. This part is just for optimization, may add it later if really needed.

Changes in v1:
The patch series is based on v6.6-rc1. Due to it is not sent in thread, I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for quick reference. You can simply review or test the patches at the link [3].

[1]: https://milkv.io/pioneer
[2]: https://en.sophgo.com/product/introduce/sg2042.html
[3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
[4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
[5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
[6]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v4
[v1-0/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-1/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-2/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-3/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-4/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-5/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-6/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-7/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-8/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-9/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-10/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-11/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-12/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v2]:https://lore.kernel.org/linux-riscv/[email protected]/ [v3]:https://lore.kernel.org/linux-riscv/[email protected]/

---

Chen Wang (8):
riscv: Add SOPHGO SOC family Kconfig support
dt-bindings: vendor-prefixes: add milkv/sophgo
dt-bindings: riscv: add sophgo sg2042 bindings
dt-bindings: riscv: Add T-HEAD C920 compatibles
dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
riscv: dts: add initial Sophgo SG2042 SoC device tree
riscv: dts: sophgo: add Milk-V Pioneer board device tree
riscv: defconfig: enable SOPHGO SoC

Inochi Amaoto (2):
dt-bindings: timer: Add Sophgo sg2042 CLINT timer
dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi

 .../sifive,plic-1.0.0.yaml                    |    1 +
 .../thead,c900-aclint-mswi.yaml               |   43 +
 .../devicetree/bindings/riscv/cpus.yaml       |    1 +
 .../devicetree/bindings/riscv/sophgo.yaml     |   28 +
 .../timer/thead,c900-aclint-mtimer.yaml       |   43 +
 .../devicetree/bindings/vendor-prefixes.yaml  |    4 +
 MAINTAINERS                                   |    7 +
 arch/riscv/Kconfig.socs                       |    5 +
 arch/riscv/boot/dts/Makefile                  |    1 +
 arch/riscv/boot/dts/sophgo/Makefile           |    3 +
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi   | 2000 +++++++++++++++++
 .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  |   19 +
 arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  325 +++
 arch/riscv/configs/defconfig                  |    1 +
 14 files changed, 2481 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
 create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
 create mode 100644 Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
 create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi

base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d

2.25.1

From: Chen Wang <[email protected]>

The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V cores.

---
 arch/riscv/Kconfig.socs | 5 +++++
 1 file changed, 5 insertions(+)

index 6833d01e2e70..d4df7b5d0f16 100644
@@ -22,6 +22,11 @@ config SOC_SIFIVE
 	help
 	  This enables support for SiFive SoC platform hardware.
 
+config ARCH_SOPHGO
+	bool "Sophgo SoCs"
+	help
+	  This enables support for Sophgo SoC platform hardware.
+
 config ARCH_STARFIVE
 	def_bool SOC_STARFIVE
 

2.25.1

From: Chen Wang <[email protected]>

Add new vendor strings to dt bindings. These new vendor strings are used by
- SOPHGO's SG2042 SoC [1]
- Milk-V Pioneer board [2], which uses SG2042 chip.

---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
 1 file changed, 4 insertions(+)

index 573578db9509..fcca9e070a9a 100644
@@ -863,6 +863,8 @@ patternProperties:
     description: MikroElektronika d.o.o.
   "^mikrotik,.*":
     description: MikroTik
+  "^milkv,.*":
+    description: MilkV Technology Co., Ltd
   "^miniand,.*":
     description: Miniand Tech
   "^minix,.*":

@@ -1273,6 +1275,8 @@ patternProperties:
     description: Solomon Systech Limited
   "^sony,.*":
     description: Sony Corporation
+  "^sophgo,.*":
+    description: Sophgo Technology Inc.
   "^sourceparts,.*":
     description: Source Parts Inc.
   "^spansion,.*":

2.25.1

From: Chen Wang <[email protected]>

Add DT binding documentation for the SOPHGO's SG2042 Soc [1] and the Milk-V Pioneer board [2].

---
 .../devicetree/bindings/riscv/sophgo.yaml     | 28 +++++++++++++++++++
 MAINTAINERS                                   |  6 ++++
 2 files changed, 34 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml

new file mode 100644
index 000000000000..8adb5f39ca53
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SoC-based boards
+
+maintainers:
+  - Chao Wei <[email protected]>
+  - Chen Wang <[email protected]>
+
+description:
+  Sophgo SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - milkv,pioneer
+          - const: sophgo,sg2042
+
+additionalProperties: true
+
+...

index 90f13281d297..97cb8abcfeee 100644
@@ -20063,6 +20063,12 @@ F:	drivers/char/sonypi.c
 F:	drivers/platform/x86/sony-laptop.c
 F:	include/linux/sony-laptop.h
 
+SOPHGO DEVICETREES
+M:	Chao Wei <[email protected]>
+M:	Chen Wang <[email protected]>
+S:	Maintained
+F:	Documentation/devicetree/bindings/riscv/sophgo.yaml
+
 SOUND
 M:	Jaroslav Kysela <[email protected]>
 M:	Takashi Iwai <[email protected]>

2.25.1

From: Chen Wang <[email protected]>

The C920 is RISC-V CPU cores from T-HEAD Semiconductor. Notably, the C920 core is used in the SOPHGO's SG2042 SoC.

---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

index 38c0b5213736..185a0191bad6 100644
@@ -47,6 +47,7 @@ properties:
               - sifive,u74-mc
               - thead,c906
               - thead,c910
+              - thead,c920
           - const: riscv
       - items:
           - enum:

2.25.1

From: Chen Wang <[email protected]>

Add compatible string for SOPHGO SG2042 plic.

---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
 1 file changed, 1 insertion(+)

index dc1f28e55266..16f9c4760c0f 100644
@@ -65,6 +65,7 @@ properties:
       - items:
           - enum:
               - allwinner,sun20i-d1-plic
+              - sophgo,sg2042-plic
               - thead,th1520-plic
           - const: thead,c900-plic
       - items:

2.25.1

From: Inochi Amaoto <[email protected]>

The clint of Sophgo's sg2042 is based off IP designed by T-HEAD, but Sophgo changes this IP layout to fit its cpu design and is incompatible with the standard sifive clint. The timer and ipi device are on the different address, and can not be handled by the sifive,clint dt-bindings.

If we use the same compatible string for mswi and timer of the sg2042 clint like sifive,clint, the DT may be like this:

mswi: interrupt-controller@94000000 {
	compatible = "sophgo,sg2042-clint", "thead,c900-clint";
	interrupts-extended = <&cpu1intc 3>;
	reg = <0x94000000 0x00010000>;
};

timer: timer@ac000000 {
	compatible = "sophgo,sg2042-clint", "thead,c900-clint";
	interrupts-extended = <&cpu1intc 7>;
	reg = <0xac000000 0x00010000>;
};

Since the address of mswi and timer are different, it is hard to merge them directly. So we need two DT nodes to handle both devices. If we use this DT for SBI, it will parse the mswi device in the timer initialization as the compatible string is the same, so will mswi. As they are different devices, this incorrect initialization will cause the system unusable.

There is a more robust ACLINT spec. can handle this situation, but the spec. seems to be abandoned and will not be frozen in the predictable future.

So it is not the time to add ACLINT spec in the kernel bindings. Instead, using vendor bindings is more acceptable.

Add new vendor specific compatible strings to identify timer of sg2042 clint.

---
 .../timer/thead,c900-aclint-mtimer.yaml       | 43 +++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml

new file mode 100644
index 000000000000..fbd235650e52
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo CLINT Timer
+
+maintainers:
+  - Inochi Amaoto <[email protected]>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - sophgo,sg2042-aclint-mtimer
+      - const: thead,c900-aclint-mtimer
+
+  reg:
+    maxItems: 1
+
+  interrupts-extended:
+    minItems: 1
+    maxItems: 4095
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+
+examples:
+  - |
+    timer@ac000000 {
+      compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+      interrupts-extended = <&cpu1intc 7>,
+                            <&cpu2intc 7>,
+                            <&cpu3intc 7>,
+                            <&cpu4intc 7>;
+      reg = <0xac000000 0x00010000>;
+    };
+...

2.25.1

From: Inochi Amaoto <[email protected]>

The clint of Sophgo's sg2042 is based off IP designed by T-HEAD, but Sophgo changes this IP layout to fit its cpu design and is incompatible with the standard sifive clint. The timer and ipi device are on the different address, and can not be handled by the sifive,clint dt-bindings.

If we use the same compatible string for mswi and timer of the sg2042 clint like sifive,clint, the DT may be like this:

mswi: interrupt-controller@94000000 {
        compatible = "sophgo,sg2042-clint", "thead,c900-clint";
        interrupts-extended = <&cpu1intc 3>;
        reg = <0x94000000 0x00010000>;
};

timer: timer@ac000000 {
        compatible = "sophgo,sg2042-clint", "thead,c900-clint";
        interrupts-extended = <&cpu1intc 7>;
        reg = <0xac000000 0x00010000>;
};

Since the address of mswi and timer are different, it is hard to merge them directly. So we need two DT nodes to handle both devices. If we use this DT for SBI, it will parse the mswi device in the timer initialization as the compatible string is the same, so will mswi. As they are different devices, this incorrect initialization will cause the system unusable.

There is a more robust ACLINT spec. can handle this situation, but the spec. seems to be abandoned and will not be frozen in the predictable future.

So it is not the time to add ACLINT spec in the kernel bindings. Instead, using vendor bindings is more acceptable.

Add new vendor specific compatible strings to identify mswi of sg2042 clint.

---
 .../thead,c900-aclint-mswi.yaml               | 43 +++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml

new file mode 100644
index 000000000000..065f2544b63b
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
+
+maintainers:
+  - Inochi Amaoto <[email protected]>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - sophgo,sg2042-aclint-mswi
+      - const: thead,c900-aclint-mswi
+
+  reg:
+    maxItems: 1
+
+  interrupts-extended:
+    minItems: 1
+    maxItems: 4095
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+
+examples:
+  - |
+    interrupt-controller@94000000 {
+      compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
+      interrupts-extended = <&cpu1intc 3>,
+                            <&cpu2intc 3>,
+                            <&cpu3intc 3>,
+                            <&cpu4intc 3>;
+      reg = <0x94000000 0x00010000>;
+    };
+...

2.25.1

From: Chen Wang <[email protected]>

Milk-V Pioneer motherboard is powered by SG2042.

SG2042 is server grade chip with high performance, low power consumption and high data throughput.
Key features:
- 64 RISC-V cpu cores
- 4 cores per cluster, 16 clusters on chip
- More info is available at [1].

Currently only support booting into console with only uart, other features will be added soon later.

---
 MAINTAINERS                                 |    1 +
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 2000 +++++++++++++++++++
 arch/riscv/boot/dts/sophgo/sg2042.dtsi      |  325 +++
 3 files changed, 2326 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi

index 97cb8abcfeee..fedf042e5fb4 100644
@@ -20067,6 +20067,7 @@ SOPHGO DEVICETREES
 M:	Chao Wei <[email protected]>
 M:	Chen Wang <[email protected]>
 S:	Maintained
+F:	arch/riscv/boot/dts/sophgo/
 F:	Documentation/devicetree/bindings/riscv/sophgo.yaml
 
 SOUND

2.25.1

From: Chen Wang <[email protected]>

Milk-V Pioneer [1] is a developer motherboard based on SG2042 in a standard mATX form factor.

Currently only support booting into console with only uart enabled, other features will be added soon later.

---
 arch/riscv/boot/dts/Makefile                  |  1 +
 arch/riscv/boot/dts/sophgo/Makefile           |  3 +++
 .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  | 19 +++++++++++++++++++
 3 files changed, 23 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts

index f60a280abb15..72030fd727af 100644
@@ -4,6 +4,7 @@ subdir-y += canaan
 subdir-y += microchip
 subdir-y += renesas
 subdir-y += sifive
+subdir-y += sophgo
 subdir-y += starfive
 subdir-y += thead
 

new file mode 100644
index 000000000000..5a471b19df22
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
+

new file mode 100644
index 000000000000..49b4b9c2c101
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
+ */
+
+#include "sg2042.dtsi"
+
+/ {
+	model = "Milk-V Pioneer";
+	compatible = "milkv,pioneer", "sophgo,sg2042";
+
+	chosen {
+		stdout-path = "serial0";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};

2.25.1

From: Chen Wang <[email protected]>

Enable SOPHGO SoC config in defconfig to allow the default upstream kernel to boot on Milk-V Pioneer board.

---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

index ab86ec3b9eab..bf737cfa1d2c 100644
@@ -32,6 +32,7 @@ CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SOC_VIRT=y
+CONFIG_ARCH_SOPHGO=y
 CONFIG_SMP=y
 CONFIG_HOTPLUG_CPU=y
 CONFIG_PM=y

2.25.1

This is the correct patchset, please review this one. Because my incorrect operation resulted in two patchsets with the same name being sent earlier, but they were incomplete. Sorry for the confusion.

Thanks,

Chen

From: Conor Dooley <[email protected]>

[10/10] riscv: defconfig: enable SOPHGO SoC

        https://git.kernel.org/conor/c/a4bbe6e3d9f6

b4 is confused, but I applied the whole series, temporarily, to a "sophgo" branch. IIRC I asked for the defconfig patch to have savedefconfig run it it, so I did that and amended the patch. More notably, I changed the commit message for the aclint patch, to drop the discussion about incorrect use of the sifive,clint compatible. That meant that 90% of the commit message vanished, so I'd like you guys to take a look and see if the new text works for you.
If it is acceptable, I'll merge in both this series and the milkv duo stuff. Acks on that series from one of the folks added as a maintainer here are still appreciated and will be applied.

Thanks,
Conor.

...

Just double-checked with sophgo IC engineers, sg2042 plic supports external interrupt, so 11 should be better, I will try to fix this in v5.

Thanks for your kindly reminder, Jisheng.

Thanks, I'll pay attention on this next time.

Yes, it works for us, thanks.

Due to commnents from Jisheng, I want to continue changes DTS on plic node, I have submitted v5 patchset, can you please pick and merge with this? v5 also contains the changes you have made on "sophgo" branch.

Thanks,

Chen