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Introduce PCIe PHY driver for EN7581 SoC

PATCH Applied Lorenzo Bianconi 2 participants 5 messages Jun 15, 2024 – Jun 20, 2024

Subsystems (3)
Device tree bindings Generic PHY framework Airoha PCIe PHY driver
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Lorenzo Bianconi

author maintainer
#0 lore raw

v4 cover Introduce PCIe PHY driver for EN7581 SoC

Add support for Airoha PCIe PHY controller available in the EN7581 SoC.

Changes since v3:
- fix compilation errors on x86
- remove patch 2/4
Changes since v2:
- introduce registers description in dts binding
- compile PCIe PHY controller driver as module by default
- improve code readability
Changes since v1:
- add patch 4/4 to enable PCIe PHY driver
- rename documentation binding in airoha,en7581-pcie-phy.yaml
- fix kernel doc

Lorenzo Bianconi (3):
dt-bindings: phy: airoha: Add PCIe PHY controller
phy: airoha: Add PCIe PHY driver for EN7581 SoC.
arm64: defconfig: Enable Airoha pcie phy driver

 .../bindings/phy/airoha,en7581-pcie-phy.yaml  |   58 +
 MAINTAINERS                                   |    8 +
 arch/arm64/configs/defconfig                  |    1 +
 drivers/phy/Kconfig                           |   10 +
 drivers/phy/Makefile                          |    1 +
 drivers/phy/phy-airoha-pcie-regs.h            |  477 +++++++
 drivers/phy/phy-airoha-pcie.c                 | 1248 +++++++++++++++++
 7 files changed, 1803 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
 create mode 100644 drivers/phy/phy-airoha-pcie-regs.h
 create mode 100644 drivers/phy/phy-airoha-pcie.c
Signature · 1 line
2.45.1
author maintainer
#1 lore raw

PATCH v4 1/3 dt-bindings: phy: airoha: Add PCIe PHY controller

Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY controller.

Reviewed-by Krzysztof Kozlowski <[email protected]>
Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Signed-off-by Lorenzo Bianconi <[email protected]>
---
 .../bindings/phy/airoha,en7581-pcie-phy.yaml  | 58 +++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml new file +58 -0
new file mode 100644
index 000000000000..e26c30d17ff0
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7581 PCI-Express PHY
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+
+description:
+  The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
+
+properties:
+  compatible:
+    const: airoha,en7581-pcie-phy
+
+  reg:
+    items:
+      - description: PCIE analog base address
+      - description: PCIE lane0 base address
+      - description: PCIE lane1 base address
+
+  reg-names:
+    items:
+      - const: csr-2l
+      - const: pma0
+      - const: pma1
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/phy/phy.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        phy@11e80000 {
+            compatible = "airoha,en7581-pcie-phy";
+            #phy-cells = <0>;
+            reg = <0x0 0x1fa5a000 0x0 0xfff>,
+                  <0x0 0x1fa5b000 0x0 0xfff>,
+                  <0x0 0x1fa5c000 0x0 0xfff>;
+            reg-names = "csr-2l", "pma0", "pma1";
+        };
+    };
Signature · 1 line
2.45.1
author maintainer
#2 lore raw

PATCH v4 2/3 phy: airoha: Add PCIe PHY driver for EN7581 SoC.

In reply to Lorenzo Bianconi

Introduce support for Airoha PCIe PHY controller available in EN7581 SoC.

Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Tested-by Zhengping Zhang <[email protected]>
Signed-off-by Lorenzo Bianconi <[email protected]>
---
 MAINTAINERS                        |    8 +
 drivers/phy/Kconfig                |   10 +
 drivers/phy/Makefile               |    1 +
 drivers/phy/phy-airoha-pcie-regs.h |  477 +++++++++++
 drivers/phy/phy-airoha-pcie.c      | 1248 ++++++++++++++++++++++++++++
 5 files changed, 1744 insertions(+)
 create mode 100644 drivers/phy/phy-airoha-pcie-regs.h
 create mode 100644 drivers/phy/phy-airoha-pcie.c
MAINTAINERS +8 -0
index d6c90161c7bf..804dcbc448b6 100644
@@ -682,6 +682,14 @@ S:	Supported
 F:	fs/aio.c
 F:	include/linux/*aio*.h
 
+AIROHA PCIE PHY DRIVER
+M:	Lorenzo Bianconi <[email protected]>
+L:	[email protected] (moderated for non-subscribers)
+S:	Maintained
+F:	Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
+F:	drivers/phy/phy-airoha-pcie-regs.h
+F:	drivers/phy/phy-airoha-pcie.c
+
 AIROHA SPI SNFI DRIVER
 M:	Lorenzo Bianconi <[email protected]>
 M:	Ray Liu <[email protected]>
drivers/phy/Kconfig +10 -0
index 787354b849c7..dfab1c66b3e5 100644
@@ -72,6 +72,16 @@ config PHY_CAN_TRANSCEIVER
 	  functional modes using gpios and sets the attribute max link
 	  rate, for CAN drivers.
 
+config PHY_AIROHA_PCIE
+	tristate "Airoha PCIe-PHY Driver"
+	depends on ARCH_AIROHA || COMPILE_TEST
+	depends on OF
+	select GENERIC_PHY
+	help
+	  Say Y here to add support for Airoha PCIe PHY driver.
+	  This driver create the basic PHY instance and provides initialize
+	  callback for PCIe GEN3 port.
+
 source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
drivers/phy/Makefile +1 -0
index 868a220ed0f6..5fcbce5f9ab1 100644
@@ -10,6 +10,7 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG)	+= phy-lpc18xx-usb-otg.o
 obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o
 obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o
 obj-$(CONFIG_USB_LGM_PHY)		+= phy-lgm-usb.o
+obj-$(CONFIG_PHY_AIROHA_PCIE)		+= phy-airoha-pcie.o
 obj-y					+= allwinner/	\
 					   amlogic/	\
 					   broadcom/	\
drivers/phy/phy-airoha-pcie-regs.h new file +477 -0

477 lines not on this page · raw message

drivers/phy/phy-airoha-pcie.c new file +1248 -0

1,248 lines not on this page · raw message

Signature · 1 line
2.45.1
author maintainer
#3 lore raw

PATCH v4 3/3 arm64: defconfig: Enable Airoha pcie phy driver

In reply to Lorenzo Bianconi

Enables the PHY_AIROHA_PCIE config by default.

Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Signed-off-by Lorenzo Bianconi <[email protected]>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm64/configs/defconfig +1 -0
index 57a9abe78ee4..b338a9675c34 100644
@@ -1497,6 +1497,7 @@ CONFIG_RESET_QCOM_AOSS=y
 CONFIG_RESET_QCOM_PDC=m
 CONFIG_RESET_RZG2L_USBPHY_CTRL=y
 CONFIG_RESET_TI_SCI=y
+CONFIG_PHY_AIROHA_PCIE=m
 CONFIG_PHY_XGENE=y
 CONFIG_PHY_CAN_TRANSCEIVER=m
 CONFIG_PHY_SUN4I_USB=y
Signature · 1 line
2.45.1
maintainer Applied
#4 lore raw

Re: (subset) [PATCH v4 0/3] Introduce PCIe PHY driver for EN7581 SoC

In reply to Lorenzo Bianconi
Quoted 14 lines · Lorenzo Bianconi

Add support for Airoha PCIe PHY controller available in the EN7581 SoC.

Changes since v3:
- fix compilation errors on x86
- remove patch 2/4
Changes since v2:
- introduce registers description in dts binding
- compile PCIe PHY controller driver as module by default
- improve code readability
Changes since v1:
- add patch 4/4 to enable PCIe PHY driver
- rename documentation binding in airoha,en7581-pcie-phy.yaml
- fix kernel doc

Quoted 1 line

[...]

Applied, thanks!

[1/3] dt-bindings: phy: airoha: Add PCIe PHY controller

      commit: e2d0317e665884d78c56f99d2a0005213d8390b6
[2/3] phy: airoha: Add PCIe PHY driver for EN7581 SoC.
      commit: d7d2818b93837def4a33f92da2e64c3a2752c47e

Best regards,

Signature · 1 line
Vinod Koul <[email protected]>