Add Airoha EN7581 PCIe support

Introduce Airoha EN7581 entry in mediatek-gen3 PCIe controller binding

Signed-off-by Lorenzo Bianconi <[email protected]>

---
 .../bindings/pci/mediatek-pcie-gen3.yaml      | 68 +++++++++++++++++--
 1 file changed, 63 insertions(+), 5 deletions(-)

Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +18 -5

index 76d742051f73..59112adc9ba1 100644
@@ -53,6 +53,7 @@ properties:
               - mediatek,mt8195-pcie
           - const: mediatek,mt8192-pcie
       - const: mediatek,mt8192-pcie
+      - const: airoha,en7581-pcie
 
   reg:
     maxItems: 1

@@ -76,20 +77,20 @@ properties:
 
   resets:
     minItems: 1
-    maxItems: 2
+    maxItems: 3
 
   reset-names:
     minItems: 1
-    maxItems: 2
+    maxItems: 3
     items:
-      enum: [ phy, mac ]
+      enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
 
   clocks:
-    minItems: 4
+    minItems: 1
     maxItems: 6
 
   clock-names:
-    minItems: 4
+    minItems: 1
     maxItems: 6
 
   assigned-clocks:

@@ -147,6 +148,9 @@ allOf:
           const: mediatek,mt8192-pcie
     then:
       properties:
+        clocks:
+          maxItems: 6
+
         clock-names:
           items:
             - const: pl_250m

@@ -155,6 +159,15 @@ allOf:
             - const: tl_32k
             - const: peri_26m
             - const: top_133m
+
+        resets:
+          minItems: 1
+          maxItems: 2
+
+        reset-names:
+          minItems: 1
+          maxItems: 2
+
   - if:
       properties:
         compatible:

Quoted 72 lines

Introduce Airoha EN7581 entry in mediatek-gen3 PCIe controller binding

Signed-off-by Lorenzo Bianconi <[email protected]>

---
 .../bindings/pci/mediatek-pcie-gen3.yaml      | 68 +++++++++++++++++--
 1 file changed, 63 insertions(+), 5 deletions(-)

Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +18 -5

index 76d742051f73..59112adc9ba1 100644
@@ -53,6 +53,7 @@ properties:
               - mediatek,mt8195-pcie
           - const: mediatek,mt8192-pcie
       - const: mediatek,mt8192-pcie
+      - const: airoha,en7581-pcie
 
   reg:
     maxItems: 1

@@ -76,20 +77,20 @@ properties:
 
   resets:
     minItems: 1
-    maxItems: 2
+    maxItems: 3
 
   reset-names:
     minItems: 1
-    maxItems: 2
+    maxItems: 3
     items:
-      enum: [ phy, mac ]
+      enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
 
   clocks:
-    minItems: 4
+    minItems: 1
     maxItems: 6
 
   clock-names:
-    minItems: 4
+    minItems: 1
     maxItems: 6
 
   assigned-clocks:

@@ -147,6 +148,9 @@ allOf:
           const: mediatek,mt8192-pcie
     then:
       properties:
+        clocks:
+          maxItems: 6
+
         clock-names:
           items:
             - const: pl_250m

@@ -155,6 +159,15 @@ allOf:
             - const: tl_32k
             - const: peri_26m
             - const: top_133m
+
+        resets:
+          minItems: 1
+          maxItems: 2
+
+        reset-names:
+          minItems: 1
+          maxItems: 2
+
   - if:
       properties:
         compatible:

@@ -164,6 +177,9 @@ allOf:

Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml allOf: · line 181

Quoted 5 lines

Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +2 -0

               - mediatek,mt8195-pcie
     then:
       properties:
+        clocks:
+          maxItems: 6

How come this is maxItems and not minItems? The max is always 6, before and after your patch.

Cheers,
Conor.

Introduce mtk_gen3_pcie_pdata data structure in order to define multiple callbacks for each supported SoC. This is a preliminary patch to introduce EN7581 PCIe support.

Tested-by Zhengping Zhang <[email protected]>

Signed-off-by Lorenzo Bianconi <[email protected]>

Use reset_bulk APIs to manage PHY reset lines. This is a preliminary patch in order to add Airoha EN7581 PCIe support.

Tested-by Zhengping Zhang <[email protected]>

Signed-off-by Lorenzo Bianconi <[email protected]>

Introduce support for Airoha EN7581 PCIe controller to mediatek-gen3 PCIe controller driver.

Tested-by Zhengping Zhang <[email protected]>

Signed-off-by Lorenzo Bianconi <[email protected]>

---
  drivers/pci/controller/Kconfig              |  2 +-
  drivers/pci/controller/pcie-mediatek-gen3.c | 96 ++++++++++++++++++++-
  2 files changed, 96 insertions(+), 2 deletions(-)

drivers/pci/controller/Kconfig +1 -1

index e534c02ee34f..3bd6c9430010 100644
@@ -196,7 +196,7 @@ config PCIE_MEDIATEK
 
  config PCIE_MEDIATEK_GEN3
  	tristate "MediaTek Gen3 PCIe controller"
-	depends on ARCH_MEDIATEK || COMPILE_TEST
+	depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
  	depends on PCI_MSI
  	help
  	  Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.

drivers/pci/controller/pcie-mediatek-gen3.c +0 -0

index 438a5222d986..af567b4355fa 100644

  	{},
  };
  MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);

External email : Please do not click links or open attachments until you have verified the sender or the content.
Introduce support for Airoha EN7581 PCIe controller to mediatek-gen3
PCIe controller driver.

Tested-by Zhengping Zhang <[email protected]>

Signed-off-by Lorenzo Bianconi <[email protected]>

---
 drivers/pci/controller/Kconfig              |  2 +-
 drivers/pci/controller/pcie-mediatek-gen3.c | 96
++++++++++++++++++++-
 2 files changed, 96 insertions(+), 2 deletions(-)

drivers/pci/controller/Kconfig +1 -1

index e534c02ee34f..3bd6c9430010 100644
@@ -196,7 +196,7 @@ config PCIE_MEDIATEK
 
 config PCIE_MEDIATEK_GEN3
 	tristate "MediaTek Gen3 PCIe controller"
-	depends on ARCH_MEDIATEK || COMPILE_TEST
+	depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
 	depends on PCI_MSI
 	help
 	  Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.

drivers/pci/controller/pcie-mediatek-gen3.c +3 -0

index 438a5222d986..af567b4355fa 100644
@@ -7,6 +7,7 @@
  */
 
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/delay.h>
 #include <linux/iopoll.h>
 #include <linux/irq.h>

@@ -15,6 +16,8 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/msi.h>
+#include <linux/of_device.h>
+#include <linux/of_pci.h>
 #include <linux/pci.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>

drivers/pci/controller/pcie-mediatek-gen3.c +0 -0

 #define PCIE_CFGNUM_REG			0x140
 #define PCIE_CFG_DEVFN(devfn)		((devfn) & GENMASK(7,
 0))

#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8))

drivers/pci/controller/pcie-mediatek-gen3.c +1 -0

@@ -68,6 +72,7 @@
 #define PCIE_MSI_SET_ENABLE_REG		0x190
 #define PCIE_MSI_SET_ENABLE		GENMASK(PCIE_MSI_SET_NUM - 1,
 0)
 
+#define PCIE_PIPE4_PIE8_REG		0x338
 #define PCIE_MSI_SET_BASE_REG		0xc00
 #define PCIE_MSI_SET_OFFSET		0x10

#define PCIE_MSI_SET_STATUS_OFFSET 0x04

drivers/pci/controller/pcie-mediatek-gen3.c +8 -0

+
+/* PCIe-PHY initialization delay in ms */
+#define PHY_INIT_TIME_MS		30
+/* PCIe reset line delay in ms */
+#define PCIE_RESET_TIME_MS		100
+
+#define MAX_NUM_PHY_RESETS		3
 
 struct mtk_gen3_pcie;
 

@@ -847,6 +862,74 @@ static int mtk_pcie_parse_port(struct
 mtk_gen3_pcie *pcie)
 	return 0;
 }
 
+static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)

drivers/pci/controller/pcie-mediatek-gen3.c +3 -0

+	/* Setup Rx AEQ training time */
+	writel_relaxed(0x50500032, pcie->base +
 PCIE_PEXTP_DIG_LN_RX30_P0_REG);
+	writel_relaxed(0x50500032, pcie->base +

PCIE_PEXTP_DIG_LN_RX30_P1_REG);

drivers/pci/controller/pcie-mediatek-gen3.c +15 -0

+
+	err = phy_init(pcie->phy);
+	if (err) {
+		dev_err(dev, "failed to initialize PHY\n");
+		return err;
+	}
+	mdelay(PHY_INIT_TIME_MS);
+
+	err = phy_power_on(pcie->phy);
+	if (err) {
+		dev_err(dev, "failed to power on PHY\n");
+		goto err_phy_on;
+	}
+
+	err = reset_control_bulk_deassert(pcie->soc-

Quoted 1 line

phy_resets.num_resets, pcie->phy_resets);

drivers/pci/controller/pcie-mediatek-gen3.c +6 -0

+	if (err) {
+		dev_err(dev, "failed to deassert PHYs\n");
+		goto err_phy_deassert;
+	}
+	mdelay(PCIE_RESET_TIME_MS);
+

drivers/pci/controller/pcie-mediatek-gen3.c +15 -0

+
+	err = clk_bulk_enable(pcie->num_clks, pcie->clks);
+	if (err) {
+		dev_err(dev, "failed to prepare clock\n");
+		goto err_clk_enable;
+	}
+
+	return 0;
+
+err_clk_enable:
+	clk_bulk_unprepare(pcie->num_clks, pcie->clks);
+err_clk_prepare:
+	pm_runtime_put_sync(dev);
+	pm_runtime_disable(dev);
+	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,

pcie->phy_resets);

drivers/pci/controller/pcie-mediatek-gen3.c +19 -0

+err_phy_deassert:
+	phy_power_off(pcie->phy);
+err_phy_on:
+	phy_exit(pcie->phy);
+
+	return err;
+}
+
 static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
 {
 	struct device *dev = pcie->dev;

@@ -1113,8 +1196,19 @@ static const struct mtk_gen3_pcie_pdata
 mtk_pcie_soc_mt8192 = {
 	},
 };
 
+static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = {
+	.power_up = mtk_pcie_en7581_power_up,
+	.phy_resets = {
+		.id[0] = "phy-lane0",
+		.id[1] = "phy-lane1",
+		.id[2] = "phy-lane2",
+		.num_resets = 3,
+	},
+};
+
 static const struct of_device_id mtk_pcie_of_match[] = {
 	{ .compatible = "mediatek,mt8192-pcie", .data =
 &mtk_pcie_soc_mt8192 },
+	{ .compatible = "airoha,en7581-pcie", .data =
 &mtk_pcie_soc_en7581 },

{},
};
MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);

Signature · 1 line

2.45.2

Hi Lorenzo,

Quoted 54 lines

External email : Please do not click links or open attachments until you have verified the sender or the content.
Introduce support for Airoha EN7581 PCIe controller to mediatek-gen3
PCIe controller driver.

Tested-by Zhengping Zhang <[email protected]>

Signed-off-by Lorenzo Bianconi <[email protected]>

---
 drivers/pci/controller/Kconfig              |  2 +-
 drivers/pci/controller/pcie-mediatek-gen3.c | 96
++++++++++++++++++++-
 2 files changed, 96 insertions(+), 2 deletions(-)

drivers/pci/controller/Kconfig +1 -1

index e534c02ee34f..3bd6c9430010 100644
@@ -196,7 +196,7 @@ config PCIE_MEDIATEK
 
 config PCIE_MEDIATEK_GEN3
 	tristate "MediaTek Gen3 PCIe controller"
-	depends on ARCH_MEDIATEK || COMPILE_TEST
+	depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
 	depends on PCI_MSI
 	help
 	  Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.

drivers/pci/controller/pcie-mediatek-gen3.c +3 -0

index 438a5222d986..af567b4355fa 100644
@@ -7,6 +7,7 @@
  */
 
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/delay.h>
 #include <linux/iopoll.h>
 #include <linux/irq.h>

@@ -15,6 +16,8 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/msi.h>
+#include <linux/of_device.h>
+#include <linux/of_pci.h>
 #include <linux/pci.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>

@@ -29,6 +32,7 @@
 #define PCI_CLASS(class)		(class << 8)
 #define PCIE_RC_MODE			BIT(0)
 

drivers/pci/controller/pcie-mediatek-gen3.c line 35

Quoted 1 line

drivers/pci/controller/pcie-mediatek-gen3.c +1 -0

+#define PCIE_EQ_PRESET_01_REF		0x100

Should be PCIE_EQ_PRESET_01_REG

Quoted 18 lines

drivers/pci/controller/pcie-mediatek-gen3.c +0 -0

 #define PCIE_CFGNUM_REG			0x140
 #define PCIE_CFG_DEVFN(devfn)		((devfn) & GENMASK(7,
 0))

#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8))

drivers/pci/controller/pcie-mediatek-gen3.c +1 -0

@@ -68,6 +72,7 @@
 #define PCIE_MSI_SET_ENABLE_REG		0x190
 #define PCIE_MSI_SET_ENABLE		GENMASK(PCIE_MSI_SET_NUM - 1,
 0)
 
+#define PCIE_PIPE4_PIE8_REG		0x338
 #define PCIE_MSI_SET_BASE_REG		0xc00
 #define PCIE_MSI_SET_OFFSET		0x10

#define PCIE_MSI_SET_STATUS_OFFSET 0x04

drivers/pci/controller/pcie-mediatek-gen3.c +0 -0

@@ -100,7 +105,17 @@
 #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
 #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
 

drivers/pci/controller/pcie-mediatek-gen3.c line 111

Quoted 5 lines

drivers/pci/controller/pcie-mediatek-gen3.c +4 -1

-#define MAX_NUM_PHY_RESETS		1
+/* EN7581 */
+#define PCIE_PEXTP_DIG_GLB44_P0_REG	0x10044
+#define PCIE_PEXTP_DIG_LN_RX30_P0_REG	0x15030
+#define PCIE_PEXTP_DIG_LN_RX30_P1_REG	0x15130

These registers belong to PHY, I think they should be added in the phy driver, which is located at drivers/phy/mediatek/phy-mtk-pcie.c.

Quoted 17 lines

drivers/pci/controller/pcie-mediatek-gen3.c +8 -0

+
+/* PCIe-PHY initialization delay in ms */
+#define PHY_INIT_TIME_MS		30
+/* PCIe reset line delay in ms */
+#define PCIE_RESET_TIME_MS		100
+
+#define MAX_NUM_PHY_RESETS		3
 
 struct mtk_gen3_pcie;
 

@@ -847,6 +862,74 @@ static int mtk_pcie_parse_port(struct
 mtk_gen3_pcie *pcie)
 	return 0;
 }
 
+static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)

drivers/pci/controller/pcie-mediatek-gen3.c static int mtk_pcie_parse_port(struct · line 876

Quoted 10 lines

drivers/pci/controller/pcie-mediatek-gen3.c +9 -0

+{
+	struct device *dev = pcie->dev;
+	int err;
+
+	/* Wait for bulk assert completion in mtk_pcie_setup */
+	mdelay(PCIE_RESET_TIME_MS);
+
+	/* Setup Tx-Rx detect time */
+	writel_relaxed(0x23020133, pcie->base +
 PCIE_PEXTP_DIG_GLB44_P0_REG);

Please also add definitions for each field, the layout for PCIE_PEXTP_DIG_GLB44_P0_REG is:
Bit[7:0]
Name: rg_xtp_rxdet_vcm_off_stb_t_sel
Description: Stable Time Selection of tx_cmkp_en De-Assert (DC Common
Mode Turn-Off) During RX Detection, unit: 4 us
Bit[15:8]
Name: rg_xtp_rxdet_en_stb_t_sel
Description: Stable Time Selection of tx_rxdet_en Assert During RX
Detection, unit: 1 us
Bit[23:16]
Name: rg_xtp_rxdet_finish_stb_t_sel
Description: rxdet finish stable time selection, unit: 1 tx250m_ck
Bit[27:24]
Name: rg_xtp_txpd_tx_data_en_dly
Description: ckpd_tx_data_en_sync delay selection, unit: 1 tx250m_ck
Bit[28:28]
Name: rg_xtp_txpd_rxdet_done_cdt
Description: rxdet_done cdt selection, 0: !pipe_tx_detect_rx 1:
pipe_phy_status
Bit[31:29]
Name: rg_xtp_rxdet_latch_stb_t_sel
Description: rxdet_latch state stable time selection, unit: 1
tx250m_ck

Quoted 5 lines

drivers/pci/controller/pcie-mediatek-gen3.c +3 -0

+	/* Setup Rx AEQ training time */
+	writel_relaxed(0x50500032, pcie->base +
 PCIE_PEXTP_DIG_LN_RX30_P0_REG);
+	writel_relaxed(0x50500032, pcie->base +

PCIE_PEXTP_DIG_LN_RX30_P1_REG);

Layout for PEXTP_DIG_LN_RX30:
Bit[7:0] rg_xtp_ln_rx_pdown_l1p2_exit_wait_cnt
Bit[8] rg_xtp_ln_rx_pdown_t2rlb_dig_en
Bit[28:16] rg_xtp_ln_rx_pdown_e0_aeqen_wait_us

Quoted 22 lines

drivers/pci/controller/pcie-mediatek-gen3.c +15 -0

+
+	err = phy_init(pcie->phy);
+	if (err) {
+		dev_err(dev, "failed to initialize PHY\n");
+		return err;
+	}
+	mdelay(PHY_INIT_TIME_MS);
+
+	err = phy_power_on(pcie->phy);
+	if (err) {
+		dev_err(dev, "failed to power on PHY\n");
+		goto err_phy_on;
+	}
+
+	err = reset_control_bulk_deassert(pcie->soc-

Quoted 1 line

phy_resets.num_resets, pcie->phy_resets);

drivers/pci/controller/pcie-mediatek-gen3.c +6 -0

+	if (err) {
+		dev_err(dev, "failed to deassert PHYs\n");
+		goto err_phy_deassert;
+	}
+	mdelay(PCIE_RESET_TIME_MS);
+

drivers/pci/controller/pcie-mediatek-gen3.c static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) · line 908

Quoted 10 lines

drivers/pci/controller/pcie-mediatek-gen3.c +10 -0

+	pm_runtime_enable(dev);
+	pm_runtime_get_sync(dev);
+
+	err = clk_bulk_prepare(pcie->num_clks, pcie->clks);
+	if (err) {
+		dev_err(dev, "failed to prepare clock\n");
+		goto err_clk_prepare;
+	}
+
+	writel_relaxed(0x41474147, pcie->base + PCIE_EQ_PRESET_01_REF);

Bit[6:0] val_ln0_dn
Bit [3:0]: Downstream port transmitter preset Bit [6:4]: Downstream port receiver preset hint
Bit[14:8] val_ln0_up
Bit [11:8]: Upstream port transmitter preset Bit [14:12]: Upstream port receiver preset hint
Bit[22:16] val_ln1_dn
Bit [19:16]: Downstream port transmitter preset Bit [22:20]: Downstream port receiver preset hint
BIt[30:24] val_ln1_up
Bit [27:24]: Upstream port transmitter preset Bit [30:28]: Upstream port receiver preset hint

drivers/pci/controller/pcie-mediatek-gen3.c static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) · line 909

Quoted 1 line

drivers/pci/controller/pcie-mediatek-gen3.c +1 -0

+	writel_relaxed(0x1018020f, pcie->base + PCIE_PIPE4_PIE8_REG);

Bit[5:0] k_finetune_max
Bit[7:6] k_finetune_err
Bit[18:8] k_preset_to_use
Bit[19:19] k_phyparam_query
Bit[20:20] k_query_timeout
Bit[31:21] k_preset_to_use_16g

Thanks.

Quoted 53 lines

drivers/pci/controller/pcie-mediatek-gen3.c +15 -0

+
+	err = clk_bulk_enable(pcie->num_clks, pcie->clks);
+	if (err) {
+		dev_err(dev, "failed to prepare clock\n");
+		goto err_clk_enable;
+	}
+
+	return 0;
+
+err_clk_enable:
+	clk_bulk_unprepare(pcie->num_clks, pcie->clks);
+err_clk_prepare:
+	pm_runtime_put_sync(dev);
+	pm_runtime_disable(dev);
+	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,

pcie->phy_resets);

drivers/pci/controller/pcie-mediatek-gen3.c +19 -0

+err_phy_deassert:
+	phy_power_off(pcie->phy);
+err_phy_on:
+	phy_exit(pcie->phy);
+
+	return err;
+}
+
 static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
 {
 	struct device *dev = pcie->dev;

@@ -1113,8 +1196,19 @@ static const struct mtk_gen3_pcie_pdata
 mtk_pcie_soc_mt8192 = {
 	},
 };
 
+static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = {
+	.power_up = mtk_pcie_en7581_power_up,
+	.phy_resets = {
+		.id[0] = "phy-lane0",
+		.id[1] = "phy-lane1",
+		.id[2] = "phy-lane2",
+		.num_resets = 3,
+	},
+};
+
 static const struct of_device_id mtk_pcie_of_match[] = {
 	{ .compatible = "mediatek,mt8192-pcie", .data =
 &mtk_pcie_soc_mt8192 },
+	{ .compatible = "airoha,en7581-pcie", .data =
 &mtk_pcie_soc_en7581 },

{},
};
MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);

Signature · 1 line

2.45.2