SAMA7D65 Add support for Crypto, CAN and PWM
Subsystems (4)
cover SAMA7D65 Add support for Crypto, CAN and PWM
From: Ryan Wanner <[email protected]>
This set adds support for the SAMA7D65 SoC crypto subsystem and enabling them in the device tree. This set also adds PWM to the device tree, and adds and enables the CAN bus system for the SAMA7D65 SoC.
Ryan Wanner (9):
dt-bindings: crypto: add sama7d65 in Atmel AES
dt-bindings: crypto: add sama7d65 in Atmel SHA
dt-bindings: crypto: add sama7d65 in Atmel TDES
dt-bindings: rng: atmel,at91-trng: add sama7d65 TRNG
crypto: atmel - add support for AES and SHA IPs available on sama7d65
SoC
ARM: dts: microchip: sama7d65: Add crypto support
ARM: dts: microchip: sama7d65: Add PWM support
ARM: dts: microchip: sama7d65: Add CAN bus support
ARM: dts: microchip: sama7d65: Enable CAN bus
.../crypto/atmel,at91sam9g46-aes.yaml | 4 +- .../crypto/atmel,at91sam9g46-sha.yaml | 4 +- .../crypto/atmel,at91sam9g46-tdes.yaml | 4 +- .../bindings/rng/atmel,at91-trng.yaml | 1 + .../dts/microchip/at91-sama7d65_curiosity.dts | 35 +++++ arch/arm/boot/dts/microchip/sama7d65.dtsi | 128 ++++++++++++++++++ drivers/crypto/atmel-aes.c | 1 + drivers/crypto/atmel-sha.c | 1 + 8 files changed, 175 insertions(+), 3 deletions(-)
Signature · 1 line
2.43.0
PATCH 2/9 dt-bindings: crypto: add sama7d65 in Atmel SHA
From: Ryan Wanner <[email protected]>
Add DT bindings for SAMA7D65 SoC Atmel SHA.
--- .../devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml +3 -1
@@ -15,7 +15,9 @@ properties: oneOf: - const: atmel,at91sam9g46-sha - items: - - const: microchip,sam9x7-sha + - enum: + - microchip,sam9x7-sha + - microchip,sama7d65-sha - const: atmel,at91sam9g46-sha reg:
Signature · 1 line
2.43.0
PATCH 3/9 dt-bindings: crypto: add sama7d65 in Atmel TDES
In reply to [email protected]From: Ryan Wanner <[email protected]>
Add DT bindings for SAMA7D65 SoC Atmel TDES.
--- .../devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml +3 -1
@@ -15,7 +15,9 @@ properties: oneOf: - const: atmel,at91sam9g46-tdes - items: - - const: microchip,sam9x7-tdes + - enum: + - microchip,sam9x7-tdes + - microchip,sama7d65-tdes - const: atmel,at91sam9g46-tdes reg:
Signature · 1 line
2.43.0
PATCH 4/9 dt-bindings: rng: atmel,at91-trng: add sama7d65 TRNG
In reply to [email protected]From: Ryan Wanner <[email protected]>
Add compatible for Microchip SAMA7D65 SoC TRNG.
--- Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml +1 -0
@@ -24,6 +24,7 @@ properties: - items: - enum: - microchip,sam9x7-trng + - microchip,sama7d65-trng - const: microchip,sam9x60-trng clocks:
Signature · 1 line
2.43.0
PATCH 5/9 crypto: atmel - add support for AES and SHA IPs available on sama7d65 SoC
In reply to [email protected]From: Ryan Wanner <[email protected]>
This patch adds support for hardware version of AES and SHA IPs available on SAMA7D65 SoC.
--- drivers/crypto/atmel-aes.c | 1 + drivers/crypto/atmel-sha.c | 1 + 2 files changed, 2 insertions(+)
drivers/crypto/atmel-aes.c +1 -0
@@ -2296,6 +2296,7 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)/* keep only major version number */ switch (dd->hw_version &0xff0 ) { +case 0x800 :case 0x700 :case 0x600 :case 0x500 :
drivers/crypto/atmel-sha.c +1 -0
@@ -2532,6 +2532,7 @@ static void atmel_sha_get_cap(struct atmel_sha_dev *dd)/* keep only major version number */ switch (dd->hw_version &0xff0 ) { +case 0x800 :case 0x700 :case 0x600 :case 0x510 :
Signature · 1 line
2.43.0
PATCH 6/9 ARM: dts: microchip: sama7d65: Add crypto support
In reply to [email protected]From: Ryan Wanner <[email protected]>
Add and enable SHA, AES, TDES, and TRNG for SAMA7D65 SoC.
--- arch/arm/boot/dts/microchip/sama7d65.dtsi | 39 +++++++++++++++++++++++ 1 file changed, 39 insertions(+)
arch/arm/boot/dts/microchip/sama7d65.dtsi +39 -0
@@ -186,6 +186,45 @@ sdmmc1: mmc@e1208000 { status = "disabled"; }; + aes: crypto@e1600000 { + compatible = "microchip,sama7d65-aes", "atmel,at91sam9g46-aes"; + reg = <0xe1600000 0x100>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; + clock-names = "aes_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + }; + + sha: crypto@e1604000 { + compatible = "microchip,sama7d65-sha", "atmel,at91sam9g46-sha"; + reg = <0xe1604000 0x100>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 78>; + clock-names = "sha_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; + dma-names = "tx"; + }; + + tdes: crypto@e1608000 { + compatible = "microchip,sama7d65-tdes", "atmel,at91sam9g46-tdes"; + reg = <0xe1608000 0x100>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 91>; + clock-names = "tdes_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, + <&dma0 AT91_XDMAC_DT_PERID(53)>; + dma-names = "tx", "rx"; + }; + + trng: rng@e160c000 { + compatible = "microchip,sama7d65-trng", "microchip,sam9x60-trng"; + reg = <0xe160c000 0x100>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 92>; + }; + dma0: dma-controller@e1610000 { compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; reg = <0xe1610000 0x1000>;
Signature · 1 line
2.43.0
PATCH 7/9 ARM: dts: microchip: sama7d65: Add PWM support
In reply to [email protected]From: Ryan Wanner <[email protected]>
Add support for PWMs to the SAMA7D65 SoC.
--- arch/arm/boot/dts/microchip/sama7d65.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/arm/boot/dts/microchip/sama7d65.dtsi +9 -0
@@ -293,6 +293,15 @@ pit64b1: timer@e1804000 { clock-names = "pclk", "gclk"; }; + pwm: pwm@e1818000 { + compatible = "microchip,sama7d65-pwm", "atmel,sama5d2-pwm"; + reg = <0xe1818000 0x500>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 72>; + #pwm-cells = <3>; + status = "disabled"; + }; + flx0: flexcom@e1820000 { compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe1820000 0x200>;
Signature · 1 line
2.43.0
PATCH 8/9 ARM: dts: microchip: sama7d65: Add CAN bus support
In reply to [email protected]From: Ryan Wanner <[email protected]>
Add support for CAN bus to the SAMA7D65 SoC.
--- arch/arm/boot/dts/microchip/sama7d65.dtsi | 80 +++++++++++++++++++++++ 1 file changed, 80 insertions(+)
arch/arm/boot/dts/microchip/sama7d65.dtsi +80 -0
@@ -163,6 +163,86 @@ chipid@e0020000 { reg = <0xe0020000 0x8>; }; + can0: can@e0828000 { + compatible = "bosch,m_can"; + reg = <0xe0828000 0x200>, <0x100000 0x7800>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 58>; + assigned-clock-rates = <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can1: can@e082c000 { + compatible = "bosch,m_can"; + reg = <0xe082c000 0x200>, <0x100000 0xbc00>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 59>; + assigned-clock-rates = <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can2: can@e0830000 { + compatible = "bosch,m_can"; + reg = <0xe0830000 0x200>, <0x100000 0x10000>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 60>, <&pmc PMC_TYPE_GCK 60>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 60>; + assigned-clock-rates = <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can3: can@e0834000 { + compatible = "bosch,m_can"; + reg = <0xe0834000 0x200>, <0x110000 0x4400>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 61>; + assigned-clock-rates = <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can4: can@e0838000 { + compatible = "bosch,m_can"; + reg = <0xe0838000 0x200>, <0x110000 0x8800>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 62>; + assigned-clock-rates = <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; + status = "disabled"; + }; + dma2: dma-controller@e1200000 { compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; reg = <0xe1200000 0x1000>;
Signature · 1 line
2.43.0
PATCH 9/9 ARM: dts: microchip: sama7d65: Enable CAN bus
In reply to [email protected]From: Ryan Wanner <[email protected]>
Enable CAN bus for SAMA7D65 curiosity board.
--- .../dts/microchip/at91-sama7d65_curiosity.dts | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+)
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +35 -0
@@ -38,7 +38,24 @@ reg_5v: regulator-5v { regulator-max-microvolt = <5000000>; regulator-always-on; }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; +}; +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2_default>; + status = "okay"; +}; + +&can3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can3_default>; + status = "okay"; }; &dma0 {
@@ -278,6 +295,24 @@ &main_xtal { }; &pioa { + pinctrl_can1_default: can1-default { + pinmux = <PIN_PD10__CANTX1>, + <PIN_PD11__CANRX1>; + bias-disable; + }; + + pinctrl_can2_default: can2-default { + pinmux = <PIN_PD12__CANTX2>, + <PIN_PD13__CANRX2>; + bias-disable; + }; + + pinctrl_can3_default: can3-default { + pinmux = <PIN_PD14__CANTX3>, + <PIN_PD15__CANRX3>; + bias-disable; + }; + pinctrl_gmac0_default: gmac0-default { pinmux = <PIN_PA26__G0_TX0>, <PIN_PA27__G0_TX1>,
Signature · 1 line
2.43.0
PATCH 1/9 dt-bindings: crypto: add sama7d65 in Atmel AES
In reply to [email protected]From: Ryan Wanner <[email protected]>
Add DT bindings for SAMA7D65 SoC in atmel AES.
--- .../devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml +3 -1
@@ -15,7 +15,9 @@ properties: oneOf: - const: atmel,at91sam9g46-aes - items: - - const: microchip,sam9x7-aes + - enum: + - microchip,sam9x7-aes + - microchip,sama7d65-aes - const: atmel,at91sam9g46-aes reg:
Signature · 1 line
2.43.0
Rob Herring (Arm)
maintainerRe: [PATCH 1/9] dt-bindings: crypto: add sama7d65 in Atmel AES
Quoted 9 lines · On Mon, 12 May 2025 12:27:27 -0700, [email protected] wrote:
From: Ryan Wanner <[email protected]>
Add DT bindings for SAMA7D65 SoC in atmel AES.
Signed-off-by Ryan Wanner <[email protected]>--- .../devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:./Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml:19:13: [warning] wrong indentation: expected 14 but found 12 (indentation)
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Rob Herring (Arm)
maintainerRe: [PATCH 2/9] dt-bindings: crypto: add sama7d65 in Atmel SHA
In reply to [email protected]Quoted 9 lines · On Mon, 12 May 2025 12:27:28 -0700, [email protected] wrote:
From: Ryan Wanner <[email protected]>
Add DT bindings for SAMA7D65 SoC Atmel SHA.
Signed-off-by Ryan Wanner <[email protected]>--- .../devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:./Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml:19:13: [warning] wrong indentation: expected 14 but found 12 (indentation)
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Rob Herring (Arm)
maintainerRe: [PATCH 3/9] dt-bindings: crypto: add sama7d65 in Atmel TDES
In reply to [email protected]Quoted 9 lines · On Mon, 12 May 2025 12:27:29 -0700, [email protected] wrote:
From: Ryan Wanner <[email protected]>
Add DT bindings for SAMA7D65 SoC Atmel TDES.
Signed-off-by Ryan Wanner <[email protected]>--- .../devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:./Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml:19:13: [warning] wrong indentation: expected 14 but found 12 (indentation)
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Re: [PATCH 4/9] dt-bindings: rng: atmel,at91-trng: add sama7d65 TRNG
In reply to [email protected]Quoted 9 lines · On Mon, 12 May 2025 12:27:30 -0700, [email protected] wrote:
From: Ryan Wanner <[email protected]>
Add compatible for Microchip SAMA7D65 SoC TRNG.
Signed-off-by Ryan Wanner <[email protected]>--- Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml | 1 + 1 file changed, 1 insertion(+)
Claudiu Beznea
maintainerRe: [PATCH 1/9] dt-bindings: crypto: add sama7d65 in Atmel AES
In reply to [email protected]Hi, Ryan,
Quoted 3 lines · On 12.05.2025 22:27, [email protected] wrote:
From: Ryan Wanner <[email protected]>
Add DT bindings for SAMA7D65 SoC in atmel AES.
Would be good to improve the description here, e.g., specify differences, similarities b/w SAMA7D65 and SAM9X7 or SAM9G46. Same for other similar patches in this series.
Thank you,
Claudiu
Quoted 21 lines
Signed-off-by Ryan Wanner <[email protected]>--- .../devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml +3
-1@@ -15,7 +15,9 @@ properties: oneOf: - const: atmel,at91sam9g46-aes - items: - - const: microchip,sam9x7-aes + - enum: + - microchip,sam9x7-aes + - microchip,sama7d65-aes - const: atmel,at91sam9g46-aes reg:
Re: [PATCH 6/9] ARM: dts: microchip: sama7d65: Add crypto support
In reply to [email protected]Quoted 5 lines · On 12.05.2025 22:27, [email protected] wrote:
From: Ryan Wanner <[email protected]>
Add and enable SHA, AES, TDES, and TRNG for SAMA7D65 SoC.
Signed-off-by Ryan Wanner <[email protected]>
Quoted 54 lines
--- arch/arm/boot/dts/microchip/sama7d65.dtsi | 39 +++++++++++++++++++++++ 1 file changed, 39 insertions(+)arch/arm/boot/dts/microchip/sama7d65.dtsi +39
-0@@ -186,6 +186,45 @@ sdmmc1: mmc@e1208000 { status = "disabled"; }; + aes: crypto@e1600000 { + compatible = "microchip,sama7d65-aes", "atmel,at91sam9g46-aes"; + reg = <0xe1600000 0x100>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; + clock-names = "aes_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + }; + + sha: crypto@e1604000 { + compatible = "microchip,sama7d65-sha", "atmel,at91sam9g46-sha"; + reg = <0xe1604000 0x100>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 78>; + clock-names = "sha_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; + dma-names = "tx"; + }; + + tdes: crypto@e1608000 { + compatible = "microchip,sama7d65-tdes", "atmel,at91sam9g46-tdes"; + reg = <0xe1608000 0x100>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 91>; + clock-names = "tdes_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, + <&dma0 AT91_XDMAC_DT_PERID(53)>; + dma-names = "tx", "rx"; + }; + + trng: rng@e160c000 { + compatible = "microchip,sama7d65-trng", "microchip,sam9x60-trng"; + reg = <0xe160c000 0x100>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 92>; + }; + dma0: dma-controller@e1610000 { compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; reg = <0xe1610000 0x1000>;
Re: [PATCH 4/9] dt-bindings: rng: atmel,at91-trng: add sama7d65 TRNG
In reply to [email protected]Quoted 5 lines · On 12.05.2025 22:27, [email protected] wrote:
From: Ryan Wanner <[email protected]>
Add compatible for Microchip SAMA7D65 SoC TRNG.
Signed-off-by Ryan Wanner <[email protected]>
Quoted 16 lines
--- Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml +1
-0@@ -24,6 +24,7 @@ properties: - items: - enum: - microchip,sam9x7-trng + - microchip,sama7d65-trng - const: microchip,sam9x60-trng clocks:
Re: [PATCH 7/9] ARM: dts: microchip: sama7d65: Add PWM support
In reply to [email protected]Quoted 5 lines · On 12.05.2025 22:27, [email protected] wrote:
From: Ryan Wanner <[email protected]>
Add support for PWMs to the SAMA7D65 SoC.
Signed-off-by Ryan Wanner <[email protected]>
Quoted 24 lines
--- arch/arm/boot/dts/microchip/sama7d65.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)arch/arm/boot/dts/microchip/sama7d65.dtsi +9
-0@@ -293,6 +293,15 @@ pit64b1: timer@e1804000 { clock-names = "pclk", "gclk"; }; + pwm: pwm@e1818000 { + compatible = "microchip,sama7d65-pwm", "atmel,sama5d2-pwm"; + reg = <0xe1818000 0x500>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 72>; + #pwm-cells = <3>; + status = "disabled"; + }; + flx0: flexcom@e1820000 { compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe1820000 0x200>;
Re: [PATCH 8/9] ARM: dts: microchip: sama7d65: Add CAN bus support
In reply to [email protected]Quoted 5 lines · On 12.05.2025 22:27, [email protected] wrote:
From: Ryan Wanner <[email protected]>
Add support for CAN bus to the SAMA7D65 SoC.
Signed-off-by Ryan Wanner <[email protected]>
Quoted 95 lines
--- arch/arm/boot/dts/microchip/sama7d65.dtsi | 80 +++++++++++++++++++++++ 1 file changed, 80 insertions(+)arch/arm/boot/dts/microchip/sama7d65.dtsi +80
-0@@ -163,6 +163,86 @@ chipid@e0020000 { reg = <0xe0020000 0x8>; }; + can0: can@e0828000 { + compatible = "bosch,m_can"; + reg = <0xe0828000 0x200>, <0x100000 0x7800>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 58>; + assigned-clock-rates = <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can1: can@e082c000 { + compatible = "bosch,m_can"; + reg = <0xe082c000 0x200>, <0x100000 0xbc00>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 59>; + assigned-clock-rates = <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can2: can@e0830000 { + compatible = "bosch,m_can"; + reg = <0xe0830000 0x200>, <0x100000 0x10000>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 60>, <&pmc PMC_TYPE_GCK 60>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 60>; + assigned-clock-rates = <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can3: can@e0834000 { + compatible = "bosch,m_can"; + reg = <0xe0834000 0x200>, <0x110000 0x4400>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 61>; + assigned-clock-rates = <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can4: can@e0838000 { + compatible = "bosch,m_can"; + reg = <0xe0838000 0x200>, <0x110000 0x8800>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 62>; + assigned-clock-rates = <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; + status = "disabled"; + }; + dma2: dma-controller@e1200000 { compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; reg = <0xe1200000 0x1000>;
Re: [PATCH 9/9] ARM: dts: microchip: sama7d65: Enable CAN bus
In reply to [email protected]Quoted 14 lines · On 12.05.2025 22:27, [email protected] wrote:
From: Ryan Wanner <[email protected]>
Enable CAN bus for SAMA7D65 curiosity board.
Signed-off-by Ryan Wanner <[email protected]>--- .../dts/microchip/at91-sama7d65_curiosity.dts | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+)arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +0
-0
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts reg_5v: regulator-5v { · line 42
Quoted 5 lines
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +2
-0@@ -38,7 +38,24 @@ reg_5v: regulator-5v { regulator-max-microvolt = <5000000>; regulator-always-on; }; +}; +
Please drop the empty line in a different patch.
Quoted 20 lines
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +15
-0+&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; +}; +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2_default>; + status = "okay"; +}; + +&can3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can3_default>; + status = "okay"; }; &dma0 {
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts &main_xtal { · line 300
Quoted 6 lines
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +3
-0@@ -278,6 +295,24 @@ &main_xtal { }; &pioa { + pinctrl_can1_default: can1-default { + pinmux = <PIN_PD10__CANTX1>, + <PIN_PD11__CANRX1>;
The "<" on on this line would have to be aligned with the one on the previous line. Same for the other places in this patch.
I can address all these minor bits while applying, if any.
Other than this:
Quoted 18 lines
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +15
-0+ bias-disable; + }; + + pinctrl_can2_default: can2-default { + pinmux = <PIN_PD12__CANTX2>, + <PIN_PD13__CANRX2>; + bias-disable; + }; + + pinctrl_can3_default: can3-default { + pinmux = <PIN_PD14__CANTX3>, + <PIN_PD15__CANRX3>; + bias-disable; + }; + pinctrl_gmac0_default: gmac0-default { pinmux = <PIN_PA26__G0_TX0>, <PIN_PA27__G0_TX1>,