LoongArch: DTS: Fix dtbs_check warnings

PATCH Applied Binbin Zhou 3 participants 15 messages Jan 4 – Jan 15

Subsystems (5)

Device tree bindings PCI PCI native host bridge and endpoint drivers irqchip drivers +1 more subsystems

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Binbin Zhou

author

2026-01-04 06:41 UTC #0 lore raw

v3 cover LoongArch: DTS: Fix dtbs_check warnings

Hi all:

As Krzysztof pointed out in the OSS talk, LoongArch only has three DTS, but has a bunch of warnings. The patchset attempts to fix them.

Patch-1 and patch-5 are taken from Yao[1],thanks a lot!

[1]: https://lore.kernel.org/all/[email protected]/

Test environment and results:

Package Version
------------------------- -----------

attrs                     25.4.0
dtschema                  2025.12
jsonschema                4.25.1
jsonschema-specifications 2025.9.1
pip                       25.3
pylibfdt                  1.7.2.post1
referencing               0.37.0
rfc3987                   1.3.8
rpds-py                   0.30.0
ruamel.yaml               0.18.16
ruamel.yaml.clib          0.2.15
typing_extensions         4.15.0

---------
make dtbs_check W=1

SYNC include/config/auto.conf
UPD include/config/kernel.release
DTC [C] arch/loongarch/boot/dts/loongson-2k0500-ref.dtb DTC [C] arch/loongarch/boot/dts/loongson-2k1000-ref.dtb DTC [C] arch/loongarch/boot/dts/loongson-2k2000-ref.dtb

========
V3:
patch (2/9)(3/9):
- New patches, document #address-cells property;

patch (4/9):
- Rewrite commit title and message;
- Remove unneeded changes, leaving only the #address-cells value set.

patch (6/9):
- Set #address-cells = <0> to liointc node;

patch (8/9):
- Set #address-cells = <0> to liointc and eiointc node;

Link to V2:
https://lore.kernel.org/all/[email protected]/

V2:
patch(1/7)(3/7):
- Add myself s-o-b;

patch(2/7):
- Define the value of #address-cells to 0;

patch(5/7):
- Set #address-cells = <0> to liointc0 node;

patch(7/7):
- Fix commit msg about i2c@address;
- Add Reviewed-by tag form Krzysztof, thanks.

Link to V1:
https://lore.kernel.org/all/[email protected]/

Binbin Zhou (7):
dt-bindings: interrupt-controller: loongson,eiointc: Document
address-cells
dt-bindings: interrupt-controller: loongson,liointc: Document
address-cells
dt-bindings: interrupt-controller: loongson,pch-pic: Document
address-cells
LoongArch: dts: loongson-2k0500: Add default interrupt controller
address cells
LoongArch: dts: loongson-2k1000: Add default Local I/O interrupt
controller address cells
LoongArch: dts: loongson-2k2000: Add default interrupt controller
address cells
LoongArch: dts: loongson-2k1000: Fix i2c-gpio node names

Yao Zi (2):
dt-bindings: PCI: loongson: Document msi-parent property
LoongArch: dts: Describe PCI sideband IRQ through interrupt-extended

 .../loongson,eiointc.yaml                     |  3 ++
 .../loongson,liointc.yaml                     |  3 ++
 .../loongson,pch-pic.yaml                     |  3 ++
 .../devicetree/bindings/pci/loongson.yaml     |  2 ++
 arch/loongarch/boot/dts/loongson-2k0500.dtsi  |  3 ++
 arch/loongarch/boot/dts/loongson-2k1000.dtsi  | 31 +++++++---------
 arch/loongarch/boot/dts/loongson-2k2000.dtsi  | 35 ++++++++-----------
 7 files changed, 42 insertions(+), 38 deletions(-)

base-commit: e8a259e82c7c3ee53e933bb238366ec2ba0bc892

Signature · 1 line

2.47.3

Binbin Zhou

author

2026-01-04 06:41 UTC #1 lore raw

PATCH v3 1/9 dt-bindings: PCI: loongson: Document msi-parent property

From: Yao Zi <[email protected]>

Loongson PCI controllers found in LS2K1000/2000 SoCs (loongson,ls2k-pci), 7A1000/2000 bridge chips (loongson,ls7a-pci), and RS780E bridge chips (loongson,rs780e-pci) all have their paired MSI controllers.

Though only the one in LS2K2000 SoC is described in devicetree, we should document the property for all variants. For the same reason, it isn't marked as required for now.

Fixes 83e757ecfd5d ("dt-bindings: Document Loongson PCI Host Controller")

Signed-off-by Yao Zi <[email protected]>

Acked-by Rob Herring (Arm) <[email protected]>

Signed-off-by Binbin Zhou <[email protected]>

---
 Documentation/devicetree/bindings/pci/loongson.yaml | 2 ++
 1 file changed, 2 insertions(+)

Documentation/devicetree/bindings/pci/loongson.yaml +2 -0

index e5bba63aa947..26e77218b901 100644
@@ -32,6 +32,8 @@ properties:
     minItems: 1
     maxItems: 3
 
+  msi-parent: true
+
 required:
   - compatible
   - reg

Signature · 1 line

2.47.3

Huacai Chen

maintainer

2026-01-06 02:37 UTC #2 lore raw

Re: [PATCH v3 1/9] dt-bindings: PCI: loongson: Document msi-parent property

Hi, Rob,

Quoted 8 lines · Binbin Zhou

From: Yao Zi <[email protected]>
Loongson PCI controllers found in LS2K1000/2000 SoCs (loongson,ls2k-pci), 7A1000/2000 bridge chips (loongson,ls7a-pci), and RS780E bridge chips (loongson,rs780e-pci) all have their paired MSI controllers.

Quoted 7 lines

Though only the one in LS2K2000 SoC is described in devicetree, we should document the property for all variants. For the same reason, it isn't marked as required for now.
Fixes 83e757ecfd5d ("dt-bindings: Document Loongson PCI Host Controller")
Signed-off-by Yao Zi <[email protected]>
Acked-by Rob Herring (Arm) <[email protected]>

I found that you picked Patch2~Patch4 but left this one. Why?

On the other hand, Binbin said that if the first 4 and the last 5 go to different trees, then there are still build warnings in separate repos. So if possible, please also drop Patch2~Patch4 and I will take the whole series to the loongarch tree. Thanks.

Huacai

Quoted 22 lines

Signed-off-by Binbin Zhou <[email protected]>

---
 Documentation/devicetree/bindings/pci/loongson.yaml | 2 ++
 1 file changed, 2 insertions(+)

Documentation/devicetree/bindings/pci/loongson.yaml +2 -1

index e5bba63aa947..26e77218b901 100644
@@ -32,6 +32,8 @@ properties:
     minItems: 1
     maxItems: 3
 
+  msi-parent: true
+
 required:
   - compatible
   - reg
--

2.47.3

Binbin Zhou

author

2026-01-04 06:41 UTC #3 lore raw

PATCH v3 2/9 dt-bindings: interrupt-controller: loongson,eiointc: Document address-cells

In reply to Binbin Zhou

The Loongson Extend I/O interrupt controller can be referenced in interrupt-map properties (e.g. in arch/loongarch/boot/dts/loongson-2k0500.dtsi), thus the nodes should have address-cells property.

Signed-off-by Binbin Zhou <[email protected]>

---
 .../bindings/interrupt-controller/loongson,eiointc.yaml        | 3 +++
 1 file changed, 3 insertions(+)

Documentation/devicetree/bindings/interrupt-controller/loongson,eiointc.yaml +3 -0

index 393c128a41d8..3c03d90058ed 100644
@@ -29,6 +29,9 @@ properties:
   interrupts:
     maxItems: 1
 
+  '#address-cells':
+    const: 0
+
   interrupt-controller: true
 
   '#interrupt-cells':

Signature · 1 line

2.47.3

Rob Herring (Arm)

maintainer Applied

2026-01-05 21:59 UTC #4 lore raw

Re: [PATCH v3 2/9] dt-bindings: interrupt-controller: loongson,eiointc: Document address-cells

Quoted 10 lines · Binbin Zhou

The Loongson Extend I/O interrupt controller can be referenced in interrupt-map properties (e.g. in arch/loongarch/boot/dts/loongson-2k0500.dtsi), thus the nodes should have address-cells property.
Signed-off-by Binbin Zhou <[email protected]>
---
 .../bindings/interrupt-controller/loongson,eiointc.yaml        | 3 +++
 1 file changed, 3 insertions(+)

Applied, thanks!

Binbin Zhou

author

2026-01-04 06:41 UTC #5 lore raw

PATCH v3 3/9 dt-bindings: interrupt-controller: loongson,liointc: Document address-cells

In reply to Binbin Zhou

The Loongson local I/O interrupt controller can be referenced in interrupt-map properties (e.g. in arch/loongarch/boot/dts/loongson-2k1000.dtsi), thus the nodes should have address-cells property.

Signed-off-by Binbin Zhou <[email protected]>

---
 .../bindings/interrupt-controller/loongson,liointc.yaml        | 3 +++
 1 file changed, 3 insertions(+)

Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml +3 -0

index f63b23f48d8e..9f532cb11d0c 100644
@@ -40,6 +40,9 @@ properties:
       - const: isr1
     minItems: 2
 
+  '#address-cells':
+    const: 0
+
   interrupt-controller: true
 
   interrupts:

Signature · 1 line

2.47.3

Rob Herring (Arm)

maintainer Applied

2026-01-05 21:59 UTC #6 lore raw

Re: [PATCH v3 3/9] dt-bindings: interrupt-controller: loongson,liointc: Document address-cells

Quoted 10 lines · Binbin Zhou

The Loongson local I/O interrupt controller can be referenced in interrupt-map properties (e.g. in arch/loongarch/boot/dts/loongson-2k1000.dtsi), thus the nodes should have address-cells property.
Signed-off-by Binbin Zhou <[email protected]>
---
 .../bindings/interrupt-controller/loongson,liointc.yaml        | 3 +++
 1 file changed, 3 insertions(+)

Applied, thanks!

Binbin Zhou

author

2026-01-04 06:42 UTC #7 lore raw

PATCH v3 4/9 dt-bindings: interrupt-controller: loongson,pch-pic: Document address-cells

In reply to Binbin Zhou

The Loongson PCH interrupt controller can be referenced in interrupt-map properties (e.g. in arch/loongarch/boot/dts/loongson-2k2000.dtsi), thus the nodes should have address-cells property.

Signed-off-by Binbin Zhou <[email protected]>

---
 .../bindings/interrupt-controller/loongson,pch-pic.yaml        | 3 +++
 1 file changed, 3 insertions(+)

Documentation/devicetree/bindings/interrupt-controller/loongson,pch-pic.yaml +3 -0

index b7bc5cb1dff2..eee10abe9e48 100644
@@ -29,6 +29,9 @@ properties:
     minimum: 0
     maximum: 192
 
+  '#address-cells':
+    const: 0
+
   interrupt-controller: true
 
   '#interrupt-cells':

Signature · 1 line

2.47.3

Rob Herring (Arm)

maintainer Applied

2026-01-05 21:59 UTC #8 lore raw

Re: [PATCH v3 4/9] dt-bindings: interrupt-controller: loongson,pch-pic: Document address-cells

Quoted 9 lines · Binbin Zhou

The Loongson PCH interrupt controller can be referenced in interrupt-map properties (e.g. in arch/loongarch/boot/dts/loongson-2k2000.dtsi), thus the nodes should have address-cells property.
Signed-off-by Binbin Zhou <[email protected]>
---
 .../bindings/interrupt-controller/loongson,pch-pic.yaml        | 3 +++
 1 file changed, 3 insertions(+)

Applied, thanks!

Binbin Zhou

author

2026-01-04 06:42 UTC #9 lore raw

PATCH v3 5/9 LoongArch: dts: Describe PCI sideband IRQ through interrupt-extended

In reply to Binbin Zhou

From: Yao Zi <[email protected]>

SoC integrated peripherals on LS2K1000 and LS2K2000 could be discovered as PCI devices, but require sideband interrupts to function, which are previously described by interrupts and interrupt-parent properties.

However, pci/pci-device.yaml allows interrupts property to only specify PCI INTx interrupts, not sideband ones. Convert these devices to use interrupt-extended property, which describes sideband interrupts used by PCI devices since dt-schema commit e6ea659d2baa ("schemas: pci-device:
Allow interrupts-extended for sideband interrupts"), eliminating dtbs_check warnings.

Fixes 30a5532a3206 ("LoongArch: dts: DeviceTree for Loongson-2K1000")

Signed-off-by Yao Zi <[email protected]>

Signed-off-by Binbin Zhou <[email protected]>

---
 arch/loongarch/boot/dts/loongson-2k1000.dtsi | 25 ++++++---------
 arch/loongarch/boot/dts/loongson-2k2000.dtsi | 32 ++++++++------------
 2 files changed, 21 insertions(+), 36 deletions(-)

arch/loongarch/boot/dts/loongson-2k1000.dtsi +9 ~~-16~~

index 60ab425f793f..eee06b84951c 100644
@@ -437,54 +437,47 @@ pcie@1a000000 {
 
 			gmac0: ethernet@3,0 {
 				reg = <0x1800 0x0 0x0 0x0 0x0>;
-				interrupt-parent = <&liointc0>;
-				interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
-					     <13 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts-extended = <&liointc0 12 IRQ_TYPE_LEVEL_HIGH>,
+						      <&liointc0 13 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-names = "macirq", "eth_lpi";
 				status = "disabled";
 			};
 
 			gmac1: ethernet@3,1 {
 				reg = <0x1900 0x0 0x0 0x0 0x0>;
-				interrupt-parent = <&liointc0>;
-				interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
-					     <15 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts-extended = <&liointc0 14 IRQ_TYPE_LEVEL_HIGH>,
+						      <&liointc0 15 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-names = "macirq", "eth_lpi";
 				status = "disabled";
 			};
 
 			ehci0: usb@4,1 {
 				reg = <0x2100 0x0 0x0 0x0 0x0>;
-				interrupt-parent = <&liointc1>;
-				interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts-extended = <&liointc1 18 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			ohci0: usb@4,2 {
 				reg = <0x2200 0x0 0x0 0x0 0x0>;
-				interrupt-parent = <&liointc1>;
-				interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts-extended = <&liointc1 19 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			display@6,0 {
 				reg = <0x3000 0x0 0x0 0x0 0x0>;
-				interrupt-parent = <&liointc0>;
-				interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts-extended = <&liointc0 28 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			hda@7,0 {
 				reg = <0x3800 0x0 0x0 0x0 0x0>;
-				interrupt-parent = <&liointc0>;
-				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts-extended = <&liointc0 4 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			sata: sata@8,0 {
 				reg = <0x4000 0x0 0x0 0x0 0x0>;
-				interrupt-parent = <&liointc0>;
-				interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts-extended = <&liointc0 19 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};

arch/loongarch/boot/dts/loongson-2k2000.dtsi +12 ~~-20~~

index 6c77b86ee06c..87c45f1f7cc7 100644
@@ -291,65 +291,57 @@ pcie@1a000000 {
 
 			gmac0: ethernet@3,0 {
 				reg = <0x1800 0x0 0x0 0x0 0x0>;
-				interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
-					     <13 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts-extended = <&pic 12 IRQ_TYPE_LEVEL_HIGH>,
+						      <&pic 13 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-names = "macirq", "eth_lpi";
-				interrupt-parent = <&pic>;
 				status = "disabled";
 			};
 
 			gmac1: ethernet@3,1 {
 				reg = <0x1900 0x0 0x0 0x0 0x0>;
-				interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
-					     <15 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts-extended = <&pic 14 IRQ_TYPE_LEVEL_HIGH>,
+						      <&pic 15 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-names = "macirq", "eth_lpi";
-				interrupt-parent = <&pic>;
 				status = "disabled";
 			};
 
 			gmac2: ethernet@3,2 {
 				reg = <0x1a00 0x0 0x0 0x0 0x0>;
-				interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
-					     <18 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts-extended = <&pic 17 IRQ_TYPE_LEVEL_HIGH>,
+						      <&pic 18 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-names = "macirq", "eth_lpi";
-				interrupt-parent = <&pic>;
 				status = "disabled";
 			};
 
 			xhci0: usb@4,0 {
 				reg = <0x2000 0x0 0x0 0x0 0x0>;
-				interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-parent = <&pic>;
+				interrupts-extended = <&pic 48 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			xhci1: usb@19,0 {
 				reg = <0xc800 0x0 0x0 0x0 0x0>;
-				interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-parent = <&pic>;
+				interrupts-extended = <&pic 22 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			display@6,1 {
 				reg = <0x3100 0x0 0x0 0x0 0x0>;
-				interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-parent = <&pic>;
+				interrupts-extended = <&pic 28 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			i2s@7,0 {
 				reg = <0x3800 0x0 0x0 0x0 0x0>;
-				interrupts = <78 IRQ_TYPE_LEVEL_HIGH>,
-					     <79 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts-extended = <&pic 78 IRQ_TYPE_LEVEL_HIGH>,
+						      <&pic 79 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-names = "tx", "rx";
-				interrupt-parent = <&pic>;
 				status = "disabled";
 			};
 
 			sata: sata@8,0 {
 				reg = <0x4000 0x0 0x0 0x0 0x0>;
-				interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-parent = <&pic>;
+				interrupts-extended = <&pic 16 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};

Signature · 1 line

2.47.3

Binbin Zhou

author

2026-01-04 06:42 UTC #10 lore raw

PATCH v3 6/9 LoongArch: dts: loongson-2k0500: Add default interrupt controller address cells

In reply to Binbin Zhou

Add missing address-cells 0 to the extend I/O and Local I/O interrupt controller node to silence W=1 warning:

loongson-2k0500.dtsi:513.5-51: Warning (interrupt_map): /bus@10000000/pcie@1a000000/pcie@0,0:interrupt-map:
Missing property '#address-cells' in node /bus@10000000/interrupt-controller@1fe11600, using 0 as fallback

Value '0' is correct because:
1. The extend I/O and Local I/O interrupt controller do not have children,
2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0)

Signed-off-by Binbin Zhou <[email protected]>

---
 arch/loongarch/boot/dts/loongson-2k0500.dtsi | 3 +++
 1 file changed, 3 insertions(+)

arch/loongarch/boot/dts/loongson-2k0500.dtsi +3 -0

index 357de4ca7555..e759fae77dcf 100644
@@ -131,6 +131,7 @@ liointc0: interrupt-controller@1fe11400 {
 			reg-names = "main", "isr0";
 
 			interrupt-controller;
+			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			interrupt-parent = <&cpuintc>;
 			interrupts = <2>;

@@ -149,6 +150,7 @@ liointc1: interrupt-controller@1fe11440 {
 			reg-names = "main", "isr0";
 
 			interrupt-controller;
+			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			interrupt-parent = <&cpuintc>;
 			interrupts = <4>;

@@ -164,6 +166,7 @@ eiointc: interrupt-controller@1fe11600 {
 			compatible = "loongson,ls2k0500-eiointc";
 			reg = <0x0 0x1fe11600 0x0 0xea00>;
 			interrupt-controller;
+			#address-cells = <0>;
 			#interrupt-cells = <1>;
 			interrupt-parent = <&cpuintc>;
 			interrupts = <3>;

Signature · 1 line

2.47.3

Binbin Zhou

author

2026-01-04 06:42 UTC #11 lore raw

PATCH v3 7/9 LoongArch: dts: loongson-2k1000: Add default Local I/O interrupt controller address cells

In reply to Binbin Zhou

Add missing address-cells 0 to the local I/O interrupt controller node to silence W=1 warning:

loongson-2k1000.dtsi:498.5-55: Warning (interrupt_map): /bus@10000000/pcie@1a000000/pcie@9,0:interrupt-map:
Missing property '#address-cells' in node /bus@10000000/interrupt-controller@1fe01440, using 0 as fallback

Value '0' is correct because:
1. The local I/O interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0)

Signed-off-by Binbin Zhou <[email protected]>

---
 arch/loongarch/boot/dts/loongson-2k1000.dtsi | 2 ++
 1 file changed, 2 insertions(+)

arch/loongarch/boot/dts/loongson-2k1000.dtsi +2 -0

index eee06b84951c..440a8f3c01f4 100644
@@ -114,6 +114,7 @@ liointc0: interrupt-controller@1fe01400 {
 			      <0x0 0x1fe01140 0x0 0x8>;
 			reg-names = "main", "isr0", "isr1";
 			interrupt-controller;
+			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			interrupt-parent = <&cpuintc>;
 			interrupts = <2>;

@@ -131,6 +132,7 @@ liointc1: interrupt-controller@1fe01440 {
 			      <0x0 0x1fe01148 0x0 0x8>;
 			reg-names = "main", "isr0", "isr1";
 			interrupt-controller;
+			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			interrupt-parent = <&cpuintc>;
 			interrupts = <3>;

Signature · 1 line

2.47.3

Binbin Zhou

author

2026-01-04 06:42 UTC #12 lore raw

PATCH v3 8/9 LoongArch: dts: loongson-2k2000: Add default interrupt controller address cells

In reply to Binbin Zhou

Add missing address-cells 0 to the PCH/Local I/O/Extend I/O Interrupt Controller node to silence W=1 warning:

loongson-2k2000.dtsi:364.5-49: Warning (interrupt_map): /bus@10000000/pcie@1a000000/pcie@9,0:interrupt-map:

    Missing property '#address-cells' in node /bus@10000000/interrupt-controller@10000000, using 0 as fallback

Value '0' is correct because:
1. The PCH interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0)

Signed-off-by Binbin Zhou <[email protected]>

---
 arch/loongarch/boot/dts/loongson-2k2000.dtsi | 3 +++
 1 file changed, 3 insertions(+)

arch/loongarch/boot/dts/loongson-2k2000.dtsi +3 -0

index 87c45f1f7cc7..3678c084adf7 100644
@@ -126,6 +126,7 @@ liointc: interrupt-controller@1fe01400 {
 			reg = <0x0 0x1fe01400 0x0 0x64>;
 
 			interrupt-controller;
+			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			interrupt-parent = <&cpuintc>;
 			interrupts = <2>;

@@ -140,6 +141,7 @@ eiointc: interrupt-controller@1fe01600 {
 			compatible = "loongson,ls2k2000-eiointc";
 			reg = <0x0 0x1fe01600 0x0 0xea00>;
 			interrupt-controller;
+			#address-cells = <0>;
 			#interrupt-cells = <1>;
 			interrupt-parent = <&cpuintc>;
 			interrupts = <3>;

@@ -149,6 +151,7 @@ pic: interrupt-controller@10000000 {
 			compatible = "loongson,pch-pic-1.0";
 			reg = <0x0 0x10000000 0x0 0x400>;
 			interrupt-controller;
+			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			loongson,pic-base-vec = <0>;
 			interrupt-parent = <&eiointc>;

Signature · 1 line

2.47.3

Binbin Zhou

author

2026-01-04 06:42 UTC #13 lore raw

PATCH v3 9/9 LoongArch: dts: loongson-2k1000: Fix i2c-gpio node names

In reply to Binbin Zhou

From: Binbin Zhou <[email protected]>

The binding wants the node to be named "i2c-number", but those are named "i2c-gpio-number" instead.

Rename those to i2c-0, i2c-1 to adhere to the binding and suppress dtbs_check warnings.

Signed-off-by Binbin Zhou <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

---
 arch/loongarch/boot/dts/loongson-2k1000.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/loongarch/boot/dts/loongson-2k1000.dtsi +2 -2

index 440a8f3c01f4..be4f7d119660 100644
@@ -46,7 +46,7 @@ cpuintc: interrupt-controller {
 	};
 
 	/* i2c of the dvi eeprom edid */
-	i2c-gpio-0 {
+	i2c-0 {
 		compatible = "i2c-gpio";
 		scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 		sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

@@ -57,7 +57,7 @@ i2c-gpio-0 {
 	};
 
 	/* i2c of the eeprom edid */
-	i2c-gpio-1 {
+	i2c-1 {
 		compatible = "i2c-gpio";
 		scl-gpios = <&gpio0 33 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 		sda-gpios = <&gpio0 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

Signature · 1 line

2.47.3

Huacai Chen

maintainer

2026-01-15 10:55 UTC #14 lore raw

In reply to Binbin Zhou

Applied the last 5 patches, thanks.

Huacai

Quoted 107 lines · Binbin Zhou

Hi all:
As Krzysztof pointed out in the OSS talk, LoongArch only has three DTS, but has a bunch of warnings. The patchset attempts to fix them.
Patch-1 and patch-5 are taken from Yao[1],thanks a lot!
[1]: https://lore.kernel.org/all/[email protected]/
Test environment and results:
Package Version
------------------------- -----------
attrs                     25.4.0
dtschema                  2025.12
jsonschema                4.25.1
jsonschema-specifications 2025.9.1
pip                       25.3
pylibfdt                  1.7.2.post1
referencing               0.37.0
rfc3987                   1.3.8
rpds-py                   0.30.0
ruamel.yaml               0.18.16
ruamel.yaml.clib          0.2.15
typing_extensions         4.15.0
---------
make dtbs_check W=1
SYNC include/config/auto.conf
UPD include/config/kernel.release
DTC [C] arch/loongarch/boot/dts/loongson-2k0500-ref.dtb DTC [C] arch/loongarch/boot/dts/loongson-2k1000-ref.dtb DTC [C] arch/loongarch/boot/dts/loongson-2k2000-ref.dtb
========
V3:
patch (2/9)(3/9):
- New patches, document #address-cells property;
patch (4/9):
- Rewrite commit title and message;
- Remove unneeded changes, leaving only the #address-cells value set.
patch (6/9):
- Set #address-cells = <0> to liointc node;
patch (8/9):
- Set #address-cells = <0> to liointc and eiointc node;
Link to V2:
https://lore.kernel.org/all/[email protected]/
V2:
patch(1/7)(3/7):
- Add myself s-o-b;
patch(2/7):
- Define the value of #address-cells to 0;
patch(5/7):
- Set #address-cells = <0> to liointc0 node;
patch(7/7):
- Fix commit msg about i2c@address;
- Add Reviewed-by tag form Krzysztof, thanks.
Link to V1:
https://lore.kernel.org/all/[email protected]/
Binbin Zhou (7):
dt-bindings: interrupt-controller: loongson,eiointc: Document
address-cells
dt-bindings: interrupt-controller: loongson,liointc: Document
address-cells
dt-bindings: interrupt-controller: loongson,pch-pic: Document
address-cells
LoongArch: dts: loongson-2k0500: Add default interrupt controller
address cells
LoongArch: dts: loongson-2k1000: Add default Local I/O interrupt
controller address cells
LoongArch: dts: loongson-2k2000: Add default interrupt controller
address cells
LoongArch: dts: loongson-2k1000: Fix i2c-gpio node names
Yao Zi (2):
dt-bindings: PCI: loongson: Document msi-parent property
LoongArch: dts: Describe PCI sideband IRQ through interrupt-extended
 .../loongson,eiointc.yaml                     |  3 ++
 .../loongson,liointc.yaml                     |  3 ++
 .../loongson,pch-pic.yaml                     |  3 ++
 .../devicetree/bindings/pci/loongson.yaml     |  2 ++
 arch/loongarch/boot/dts/loongson-2k0500.dtsi  |  3 ++
 arch/loongarch/boot/dts/loongson-2k1000.dtsi  | 31 +++++++---------
 arch/loongarch/boot/dts/loongson-2k2000.dtsi  | 35 ++++++++-----------
 7 files changed, 42 insertions(+), 38 deletions(-)
base-commit: e8a259e82c7c3ee53e933bb238366ec2ba0bc892 --
2.47.3