arm64: dts: imx8mm-var-dart: update SoM support

This series updates the Variscite DART-MX8M-MINI SoM device tree to better reflect the currently supported hardware configuration.

The changes configure SAI3 in synchronous RX mode, add TPM support, and increase the Ethernet PHY reset deassert delay to improve PHY detection reliability.

v1->v2:
- Add tpm pinctrl
- Add comment on tpm reset line

Stefano Radaelli (3):
arm64: dts: imx8mm-var-dart: configure SAI3 synchronous RX mode
arm64: dts: imx8mm-var-dart: add TPM support
arm64: dts: imx8mm-var-dart: increase PHY reset deassert delay

 .../boot/dts/freescale/imx8mm-var-dart.dtsi   | 21 ++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

base-commit: 46d8fa682d263271f3ef7bf95166b124c19d6c62

2.47.3

From: Stefano Radaelli <[email protected]>

Configure SAI3 to operate in synchronous RX mode, so that the trasmit path uses the receive bit clock and frame sync signals.

Remove the TX_SYNC and TX_BCLK pinmux entries, as these signals are not used in this configuration.

---
v1->v2:
-

 arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

index 2324063f8fd9..c7a9eb23e5e8 100644
@@ -305,6 +305,7 @@ &sai3 {
 	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
 	assigned-clock-rates = <1536000>;
 	fsl,sai-mclk-direction-output;
+	fsl,sai-synchronous-rx;
 	status = "okay";
 };
 

@@ -446,8 +447,6 @@ pinctrl_sai3: sai3grp {
 			MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC		0xd6
 			MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK		0xd6
 			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0		0xd6
-			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0xd6
-			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0xd6
 			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0xd6
 			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK		0xd6
 		>;

2.47.3

From: Stefano Radaelli <[email protected]>

Add support for the TPM available on the Variscite DART-MX8M-MINI SOM.

---
v1->v2:
- Add tpm pinctrl
- Add comment on tpm reset line

 .../boot/dts/freescale/imx8mm-var-dart.dtsi      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

index c7a9eb23e5e8..953950e55bf9 100644
@@ -138,6 +138,16 @@ &i2c1 {
 	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 
+	st33ktpm2xi2c_som: tpm@2e {
+		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
+		reg = <0x2e>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_tpm_reset>;
+		label = "tpm";
+		/* active-low TPM reset line. */
+		reset-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+	};
+
 	pmic@4b {
 		compatible = "rohm,bd71847";
 		reg = <0x4b>;

@@ -452,6 +462,12 @@ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK		0xd6
 		>;
 	};
 
+	pinctrl_tpm_reset: tpm-resetgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31		0x19
+		>;
+	};
+
 	pinctrl_uart4: uart4grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX		0x140

2.47.3

tpm_tis_core.c have not parser reset-gpios. ref

static int reset_gpio_assert(struct reset_controller_dev *rc, unsigned long id)

{
        struct reset_gpio_priv *priv = rc_to_reset_gpio(rc);

        return gpiod_set_value_cansleep(priv->reset, 1);
}

suppose it should be GPIO_ACTIVE_LOW to assert reset line

Frank

Thanks Frank.

You're right, tpm_tis_i2c currently does not parse a reset control. I have proposed a separate patch to add optional reset support using the reset framework:

https://patchwork.kernel.org/project/linux-integrity/patch/[email protected]/

Also, the reset line is active-low, so you are right, GPIO_ACTIVE_LOW is the correct polarity here.

Would you prefer me to send v3 without the TPM DTS patch for now, and add it back once the reset support patch has been accepted?

Best Regards,
Stefano

You leave reset-gpios if binding already here. Just need fix GPIO_ACTIVE_LOW

Frank

From: Stefano Radaelli <[email protected]>

The Ethernet PHY reset signal also controls the regulators supplying VDDA2P5 and VDD1P0, so releasing reset restores the PHY's 2.5 V and 1.0 V analog supplies.

The existing 100 ms reset deassertion delay is not sufficient for reliable PHY detection. The TI DP83867 requires 200 ms of stabilization after power-up before MDIO register access.

Increase the reset deassertion delay to 200 ms to ensure reliable PHY detection across repeated boots.

---
v1->v2:
-

 arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index 953950e55bf9..4d6a79bbb132 100644
@@ -123,7 +123,7 @@ ethphy0: ethernet-phy@0 {
 			reg = <0>;
 			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <10000>;
-			reset-deassert-us = <100000>;
+			reset-deassert-us = <200000>;
 			vddio-supply = <&reg_phy_vddio>;
 		};
 	};

2.47.3