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arm64: dts: allwinner: add A733/Cubie A7S support

PATCH In review Enzo Adriano 3 participants 8 messages Nov 10 – Nov 11

Subsystems (2)
Device tree bindings Arm/Allwinner sunXi SoC support
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Enzo Adriano

author
#0 lore raw

v3 cover arm64: dts: allwinner: add A733/Cubie A7S support

This series adds the initial Allwinner A733 and Radxa Cubie A7S device trees, enabling UART0, the AXP318W PMIC and the 3.3 V microSD path.

Base: v7.4-rc1 (6628e7d4c6b25c8d18f1345e3a20d21829aae7e4). Previous posting (v2):
https://lore.kernel.org/r/[email protected]

Changes in v3:
- Defer SMHC3/mmc3 until it has a tested user; omit binding, node and pins.
- Rebase on v7.4-rc1 and list public schema prerequisites.

Dependencies, in application order:
[1] A733 CCU v6:
https://lore.kernel.org/r/[email protected]
[2] AXP318W PMIC v8:
https://lore.kernel.org/r/[email protected]
[3] Pinctrl IRQ-bank v3:
https://lore.kernel.org/r/[email protected]
[4] A733 8250_dw v2, patches 2-4:
https://lore.kernel.org/r/[email protected]
[5] Firmware clocks (separate from CCU v6):
https://lore.kernel.org/r/[email protected]
[6] Pinctrl voltage-mode fix v3:
https://lore.kernel.org/r/[email protected]

DTB/schema checks need only [1] 1/8, [2] 3/5, [3] 2/3 and [4] 3/4, applied in that order before this series. Runtime needs the full CCU, PMIC and IRQ-bank series, [4] patches 2-4, and [5]-[6]. The clock helpers listed in v2 are already in v7.4-rc1.

Validation: arm/sunxi.yaml schema check, W=2 CHECK_DTBS=y DTB build and clean git-am reader test passed. The November 4 DT v2 RAM boot exercised UART0, PMIC and MMC0 reads on Cubie A7S with vendor firmware and pinctrl v2; v3 removes a disabled controller and unused pin group.

Untested: boot with pinctrl v3, card writes, hotplug, 1.8 V switching, other UART/I2C and storage instances, RTC alarms, EL2/ITS/MSI, and physical BLDO2 voltage.

Enzo Adriano (3):
dt-bindings: arm: sunxi: document Radxa Cubie A7S
arm64: dts: allwinner: add A733 SoC description
arm64: dts: allwinner: add Radxa Cubie A7S board

 .../devicetree/bindings/arm/sunxi.yaml        |   5 +
 arch/arm64/boot/dts/allwinner/Makefile        |   1 +
 .../dts/allwinner/sun60i-a733-cubie-a7s.dts   | 284 +++++++++
 .../arm64/boot/dts/allwinner/sun60i-a733.dtsi | 601 ++++++++++++++++++
 4 files changed, 891 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun60i-a733-cubie-a7s.dts
 create mode 100644 arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi

base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4

author
#1 lore raw

PATCH v3 1/3 dt-bindings: arm: sunxi: document Radxa Cubie A7S

Document the Radxa Cubie A7S board and Allwinner A733 SoC compatibles for the accompanying initial board device tree, so it can be identified and validated.

Acked-by Krzysztof Kozlowski <[email protected]>
Signed-off-by Enzo Adriano <[email protected]>
---
 Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++
 1 file changed, 5 insertions(+)
Documentation/devicetree/bindings/arm/sunxi.yaml +5 -0
index 28437c47ac01..37a7d713ac71 100644
@@ -857,6 +857,11 @@ properties:
           - const: radxa,cubie-a5e
           - const: allwinner,sun55i-a527
 
+      - description: Radxa Cubie A7S
+        items:
+          - const: radxa,cubie-a7s
+          - const: allwinner,sun60i-a733
+
       - description: Remix Mini PC
         items:
           - const: jide,remix-mini-pc
author
#2 lore raw

PATCH v3 2/3 arm64: dts: allwinner: add A733 SoC description

In reply to Enzo Adriano

Provide the SoC description needed for the Cubie A7S console, PMIC and microSD support. Describe the CPUs, PSCI, architectural timers, GIC, RTC, main and always-on clock/reset and pin controllers. Include the main and R-domain UART/I2C instances and MMC0-2 with their pin groups.

The GIC maintenance PPI 9 and ARMv8.2 EL2 virtual-timer PPI 12 follow the A733 User Manual v1.00, section 12.2.3. The GICD/GICR/ITS windows and noncoherent attributes follow Andre Przywara's public A733 reference and the A523 precedent. The CPUX interconnect diagram in section 5.1.2 supports noncoherency as an integration inference. The ITS stays disabled pending its clock/reset and MSI integration.

The enabled console, R-I2C0/PMIC and MMC0 paths were exercised on a Cubie A7S with vendor firmware in the November 4 RAM boot of DT v2. EL2 interrupt delivery and ITS/MSI were not tested.

Link https://gist.githubusercontent.com/apritzel/60fd7379b9560a15b8b352986b69d39f/raw/efd9cdf8f26ba5b0c7e138f093af44a1cf322469/sun60i-a733.dts
Signed-off-by Enzo Adriano <[email protected]>
---
 .../arm64/boot/dts/allwinner/sun60i-a733.dtsi | 601 ++++++++++++++++++
 1 file changed, 601 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi
arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi new file +601 -0
new file mode 100644
index 000000000000..d0b9f432e3ab
@@ -0,0 +1,601 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+
+#include <dt-bindings/clock/sun6i-rtc.h>
+#include <dt-bindings/clock/allwinner,sun60i-a733-ccu.h>
+#include <dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/allwinner,sun60i-a733-ccu.h>
+#include <dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a55";
+			device_type = "cpu";
+			reg = <0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@100 {
+			compatible = "arm,cortex-a55";
+			device_type = "cpu";
+			reg = <0x100>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@200 {
+			compatible = "arm,cortex-a55";
+			device_type = "cpu";
+			reg = <0x200>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@300 {
+			compatible = "arm,cortex-a55";
+			device_type = "cpu";
+			reg = <0x300>;
+			enable-method = "psci";
+		};
+
+		cpu4: cpu@400 {
+			compatible = "arm,cortex-a55";
+			device_type = "cpu";
+			reg = <0x400>;
+			enable-method = "psci";
+		};
+
+		cpu5: cpu@500 {
+			compatible = "arm,cortex-a55";
+			device_type = "cpu";
+			reg = <0x500>;
+			enable-method = "psci";
+		};
+
+		cpu6: cpu@600 {
+			compatible = "arm,cortex-a76";
+			device_type = "cpu";
+			reg = <0x600>;
+			enable-method = "psci";
+		};
+
+		cpu7: cpu@700 {
+			compatible = "arm,cortex-a76";
+			device_type = "cpu";
+			reg = <0x700>;
+			enable-method = "psci";
+		};
+	};
+
+	osc: osc-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		arm,no-tick-in-suspend;
+	};
+
+	soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x0 0x40000000>;
+
+		pio: pinctrl@2000000 {
+			compatible = "allwinner,sun60i-a733-pinctrl";
+			reg = <0x02000000 0x800>;
+			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_APB1>, <&osc>, <&rtc CLK_OSC32K>;
+			clock-names = "apb", "hosc", "losc";
+			gpio-controller;
+			#gpio-cells = <3>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+
+			mmc0_pins: mmc0-pins {
+				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+				function = "mmc0";
+				allwinner,pinmux = <2>;
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
+			mmc1_pins: mmc1-pins {
+				pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
+				function = "mmc1";
+				allwinner,pinmux = <2>;
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
+			mmc2_pins: mmc2-pins {
+				pins = "PC5", "PC6", "PC8", "PC9", "PC10", "PC11",
+				       "PC13", "PC14", "PC15", "PC16";
+				function = "mmc2";
+				allwinner,pinmux = <3>;
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
+			uart0_pb_pins: uart0-pb-pins {
+				pins = "PB9", "PB10";
+				function = "uart0";
+				allwinner,pinmux = <2>;
+			};
+		};
+
+		ccu: clock-controller@2002000 {
+			compatible = "allwinner,sun60i-a733-ccu";
+			reg = <0x02002000 0x2000>;
+			clocks = <&osc>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
+				 <&rtc CLK_OSC32K_FANOUT>;
+			clock-names = "hosc", "losc", "iosc", "losc-fanout";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		uart0: serial@2500000 {
+			compatible = "allwinner,sun60i-a733-uart",
+				     "snps,dw-apb-uart";
+			reg = <0x02500000 0x400>;
+			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART0>;
+			resets = <&ccu RST_BUS_UART0>;
+			status = "disabled";
+		};
+
+		uart1: serial@2501000 {
+			compatible = "allwinner,sun60i-a733-uart",
+				     "snps,dw-apb-uart";
+			reg = <0x02501000 0x400>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART1>;
+			resets = <&ccu RST_BUS_UART1>;
+			status = "disabled";
+		};
+
+		uart2: serial@2502000 {
+			compatible = "allwinner,sun60i-a733-uart",
+				     "snps,dw-apb-uart";
+			reg = <0x02502000 0x400>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART2>;
+			resets = <&ccu RST_BUS_UART2>;
+			status = "disabled";
+		};
+
+		uart3: serial@2503000 {
+			compatible = "allwinner,sun60i-a733-uart",
+				     "snps,dw-apb-uart";
+			reg = <0x02503000 0x400>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART3>;
+			resets = <&ccu RST_BUS_UART3>;
+			status = "disabled";
+		};
+
+		uart4: serial@2504000 {
+			compatible = "allwinner,sun60i-a733-uart",
+				     "snps,dw-apb-uart";
+			reg = <0x02504000 0x400>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART4>;
+			resets = <&ccu RST_BUS_UART4>;
+			status = "disabled";
+		};
+
+		uart5: serial@2505000 {
+			compatible = "allwinner,sun60i-a733-uart",
+				     "snps,dw-apb-uart";
+			reg = <0x02505000 0x400>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART5>;
+			resets = <&ccu RST_BUS_UART5>;
+			status = "disabled";
+		};
+
+		uart6: serial@2506000 {
+			compatible = "allwinner,sun60i-a733-uart",
+				     "snps,dw-apb-uart";
+			reg = <0x02506000 0x400>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART6>;
+			resets = <&ccu RST_BUS_UART6>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@2510000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x02510000 0x400>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C0>;
+			resets = <&ccu RST_BUS_I2C0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@2511000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x02511000 0x400>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C1>;
+			resets = <&ccu RST_BUS_I2C1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@2512000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x02512000 0x400>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C2>;
+			resets = <&ccu RST_BUS_I2C2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@2513000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x02513000 0x400>;
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C3>;
+			resets = <&ccu RST_BUS_I2C3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@2514000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x02514000 0x400>;
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C4>;
+			resets = <&ccu RST_BUS_I2C4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@2515000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x02515000 0x400>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C5>;
+			resets = <&ccu RST_BUS_I2C5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@2516000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x02516000 0x400>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C6>;
+			resets = <&ccu RST_BUS_I2C6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c7: i2c@2517000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x02517000 0x400>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C7>;
+			resets = <&ccu RST_BUS_I2C7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c8: i2c@2518000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x02518000 0x400>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C8>;
+			resets = <&ccu RST_BUS_I2C8>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c9: i2c@2519000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x02519000 0x400>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C9>;
+			resets = <&ccu RST_BUS_I2C9>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c10: i2c@251a000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x0251a000 0x400>;
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C10>;
+			resets = <&ccu RST_BUS_I2C10>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c11: i2c@251b000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x0251b000 0x400>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C11>;
+			resets = <&ccu RST_BUS_I2C11>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c12: i2c@251c000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x0251c000 0x400>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C12>;
+			resets = <&ccu RST_BUS_I2C12>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@3400000 {
+			compatible = "arm,gic-v3";
+			reg = <0x03400000 0x10000>, <0x03460000 0x100000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			dma-noncoherent;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			its: msi-controller@3440000 {
+				compatible = "arm,gic-v3-its";
+				reg = <0x03440000 0x20000>;
+				msi-controller;
+				#msi-cells = <1>;
+				dma-noncoherent;
+				status = "disabled";
+			};
+		};
+
+		mmc0: mmc@4020000 {
+			compatible = "allwinner,sun60i-a733-mmc",
+				     "allwinner,sun20i-d1-mmc";
+			reg = <0x04020000 0x1000>;
+			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC0>;
+			reset-names = "ahb";
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc0_pins>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		mmc1: mmc@4021000 {
+			compatible = "allwinner,sun60i-a733-mmc",
+				     "allwinner,sun20i-d1-mmc";
+			reg = <0x04021000 0x1000>;
+			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC1>;
+			reset-names = "ahb";
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc1_pins>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		mmc2: mmc@4022000 {
+			compatible = "allwinner,sun60i-a733-mmc",
+				     "allwinner,sun20i-d1-mmc";
+			reg = <0x04022000 0x1000>;
+			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC2>;
+			reset-names = "ahb";
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc2_pins>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		r_ccu: clock-controller@7010000 {
+			compatible = "allwinner,sun60i-a733-r-ccu";
+			reg = <0x07010000 0x250>;
+			clocks = <&osc>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
+				 <&ccu CLK_SYS_24M>, <&ccu CLK_PLL_PERIPH0_200M>,
+				 <&ccu CLK_PLL_PERIPH0_300M>,
+				 <&ccu CLK_PLL_PERIPH1_300M>;
+			clock-names = "hosc", "losc", "iosc", "sys-24m",
+				      "pll-periph0-200m", "pll-periph0-300m",
+				      "pll-periph1-300m";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		nmi_intc: interrupt-controller@7010320 {
+			compatible = "allwinner,sun60i-a733-nmi",
+				     "allwinner,sun55i-a523-nmi";
+			reg = <0x07010320 0xc>;
+			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		r_pio: pinctrl@7025000 {
+			compatible = "allwinner,sun60i-a733-r-pinctrl";
+			reg = <0x07025000 0x800>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&r_ccu CLK_R_APB0>, <&osc>, <&rtc CLK_OSC32K>;
+			clock-names = "apb", "hosc", "losc";
+			gpio-controller;
+			#gpio-cells = <3>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+
+			r_i2c0_pl_pins: r-i2c0-pl-pins {
+				pins = "PL0", "PL1";
+				function = "r_i2c0";
+				allwinner,pinmux = <2>;
+			};
+		};
+
+		r_uart0: serial@7080000 {
+			compatible = "allwinner,sun60i-a733-uart",
+				     "snps,dw-apb-uart";
+			reg = <0x07080000 0x400>;
+			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&r_ccu CLK_BUS_R_UART0>;
+			resets = <&r_ccu RST_BUS_R_UART0>;
+			status = "disabled";
+		};
+
+		r_uart1: serial@7081000 {
+			compatible = "allwinner,sun60i-a733-uart",
+				     "snps,dw-apb-uart";
+			reg = <0x07081000 0x400>;
+			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&r_ccu CLK_BUS_R_UART1>;
+			resets = <&r_ccu RST_BUS_R_UART1>;
+			status = "disabled";
+		};
+
+		r_i2c0: i2c@7083000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x07083000 0x400>;
+			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&r_ccu CLK_BUS_R_I2C0>;
+			resets = <&r_ccu RST_BUS_R_I2C0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		r_i2c1: i2c@7084000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x07084000 0x400>;
+			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&r_ccu CLK_BUS_R_I2C1>;
+			resets = <&r_ccu RST_BUS_R_I2C1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		r_i2c2: i2c@7085000 {
+			compatible = "allwinner,sun60i-a733-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x07085000 0x400>;
+			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&r_ccu CLK_BUS_R_I2C2>;
+			resets = <&r_ccu RST_BUS_R_I2C2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		rtc: rtc@7090000 {
+			compatible = "allwinner,sun60i-a733-rtc",
+				     "allwinner,sun50i-r329-rtc";
+			reg = <0x07090000 0x400>;
+			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&r_ccu CLK_BUS_R_RTC>, <&osc>, <&r_ccu CLK_R_AHB>;
+			clock-names = "bus", "hosc", "ahb";
+			#clock-cells = <1>;
+		};
+	};
+};
AI review
#3 lore raw

Re: [PATCH v3 2/3] arm64: dts: allwinner: add A733 SoC description

Thank you for your contribution! Sashiko AI review found 3 potential issues to consider: - [High] arm64: dts: allwinner: missing A733 CCU dt-bindings headers and schemas - [High] arm64: dts…

Thank you for your contribution! Sashiko AI review found 3 potential issues to consider:
- [High] arm64: dts: allwinner: missing A733 CCU dt-bindings headers and schemas
- [High] arm64: dts: allwinner: pio node lists 10 interrupts instead of 11 on A733
- [Low] arm64: dts: allwinner: undocumented allwinner,sun60i-a733-uart compatible
--

commit 7fc84ade8f1b2531c3b62b4ae64bebc46f692d4e
Author: Enzo Adriano <[email protected]>

arm64: dts: allwinner: add A733 SoC description

This commit adds the base SoC device tree description for the Allwinner A733 (sun60i-a733.dtsi), covering the CPUs, PSCI, timers, GIC, RTC, clock/reset and pin controllers, UARTs, I2C controllers, and MMC0-2.

Link https://gist.githubusercontent.com/apritzel/60fd7379b9560a15b8b352986b69d39f/raw/efd9cdf8f26ba5b0c7e138f093af44a1cf322469/sun60i-a733.dts
Quoted 6 lines
arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi new file +0 -0
new file mode 100644
index 0000000000000..d0b9f432e3ab3

arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi line 8

Quoted 8 lines
arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi new file +8 -0
@@ -0,0 +1,601 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+
+#include <dt-bindings/clock/sun6i-rtc.h>
+#include <dt-bindings/clock/allwinner,sun60i-a733-ccu.h>
+#include <dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/allwinner,sun60i-a733-ccu.h>
+#include <dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h>

[Severity: High]
Are the A733 CCU and R-CCU dt-binding headers and schemas missing from the tree?

None of dt-bindings/clock/allwinner,sun60i-a733-ccu.h, dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h, dt-bindings/reset/allwinner,sun60i-a733-ccu.h, or dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h exist under include/dt-bindings/, so preprocessing any DTB that includes sun60i-a733.dtsi fails immediately and leaves all CCU and R-CCU clock and reset macros undefined. In addition, the allwinner,sun60i-a733-ccu and allwinner,sun60i-a733-r-ccu compatibles used by ccu and r_ccu below have no binding documentation or driver support.

[ ... ]

arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi line 114

Quoted 13 lines
arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi new file +13 -0
+		pio: pinctrl@2000000 {
+			compatible = "allwinner,sun60i-a733-pinctrl";
+			reg = <0x02000000 0x800>;
+			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;

[Severity: High]
Does omitting Port A's interrupt (GIC_SPI 67) shift all GPIO bank interrupts on pio off by one bank?

Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml requires 11 interrupts for allwinner,sun60i-a733-pinctrl to cover Port A through Port K. In drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c, prepare_function_table() assigns irq_bank = 1 to Port B through irq_bank = 10 to Port K (since Port A has 0 pins at bank 0), and sunxi_irq_base_reg() indexes IRQ status/control registers by 0-based bank number:

drivers/pinctrl/sunxi/pinctrl-sunxi.h:sunxi_irq_base_reg() {
	if (pctl->flags & SUNXI_PINCTRL_NCAT3_REG_LAYOUT)
		return pctl->bank_offset + bank * pctl->bank_mem_size +
		       A733_IRQ_REGS_OFFSET;
    ...
}

Listing only 10 interrupts starting at Port B (GIC_SPI 69) maps GIC_SPI 69 to bank 0 (Port A) instead of bank 1 (Port B), so when any GPIO interrupt on Port B through Port K fires, sunxi_pinctrl_irq_handler() reads the preceding bank's status register and fails to clear or dispatch the interrupt.

[ ... ]

arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi line 166

Quoted 3 lines
arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi new file +3 -0
+		uart0: serial@2500000 {
+			compatible = "allwinner,sun60i-a733-uart",
+				     "snps,dw-apb-uart";

[Severity: Low]
Is "allwinner,sun60i-a733-uart" documented in Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml?

The binding schema does not list allwinner,sun60i-a733-uart, which causes dtbs_check validation failures on uart0..uart6 and r_uart0..r_uart1 (other Allwinner arm64 SoCs use "snps,dw-apb-uart" directly).

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
Tested-by on v3 2/3
#4 lore raw

Re: [PATCH v3 2/3] arm64: dts: allwinner: add A733 SoC description

In reply to Enzo Adriano
Quoted 2 lines · Enzo Adriano

Provide the SoC description needed for the Cubie A7S console, PMIC and microSD support.

Tested-by Vinicius Pedrosa <[email protected]> # Radxa Cubie A7Z

I tested the A733 SoC dtsi with the posted prerequisite series and a local board DT.

UART0, R-I2C0/AXP318W, RTC, MMC0 at 3.3 V (hash-checked reads and writes), eight CPUs, PSCI reboot/power-off and 20 CPU hotplug cycles worked. GPIO interrupts worked on both edges for PB, PC, PD, PE, PG, PH, PJ and PK.

MMC0 card-detect hotplug needed my separate A733 EINT-mux fix. PI is not exposed on this board, and I haven't tested the R-PIO interrupts or the A7S-specific DT patches.

I'll send the A7Z board DT as a separate series based on this one.

author
#5 lore raw

PATCH v3 3/3 arm64: dts: allwinner: add Radxa Cubie A7S board

In reply to Enzo Adriano

Enable the Cubie A7S serial console, PMIC and microSD slot to provide an initial usable board configuration. Supply the 26 MHz crystal and 32768 Hz RTC input, enable UART0 and the AXP318W on R-I2C0, and describe the PMIC input/output and CPU supply connections from the Radxa Cubie A7S schematic v1.10. Preserve firmware settings on rails whose working voltage is not established. BLDO2 has no programmed voltage constraint:
its software 3.3 V selector does not establish its physical output with the schematic's nominal 2.4 V input.

Describe the card's SWOUT2 supply and PF6 active-high detect with an internal pull-down. Enable MMC0 at up to 50 MHz using 3.3 V signaling only. Its high-voltage path uses VCCIO; CLDO5 also feeds PC and the PF 1.8 V input and must not be raised for SD signaling. Firmware must select the 3.3 V PF path; dynamic voltage switching is not provided. Keep other storage off.

Connect the documented bank supplies. PL's self-supply phandle is omitted to avoid the PMIC/I2C/pinctrl bootstrap cycle, as on the upstream Cubie A5E; ALDO1 is retained always-on. The separate pinctrl voltage-mode fix is required for these bank-supply connections.

These board DTS bytes were RAM-booted on a Cubie A7S with vendor firmware on November 4: UART0, PMIC registration and MMC0 read-only transfers worked. Card writes, physical hotplug, 1.8 V signaling and physical BLDO2 voltage were not tested.

Signed-off-by Enzo Adriano <[email protected]>
---
 arch/arm64/boot/dts/allwinner/Makefile        |   1 +
 .../dts/allwinner/sun60i-a733-cubie-a7s.dts   | 284 ++++++++++++++++++
 2 files changed, 285 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun60i-a733-cubie-a7s.dts
arch/arm64/boot/dts/allwinner/Makefile +1 -0
index d1f768dd6461..792152525b43 100644
@@ -68,3 +68,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun55i-a527-cubie-a5e.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun55i-h728-x96qpro+.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun55i-t527-avaota-a1.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun55i-t527-orangepi-4a.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun60i-a733-cubie-a7s.dtb
arch/arm64/boot/dts/allwinner/sun60i-a733-cubie-a7s.dts new file +284 -0

284 lines not on this page · raw message

AI review
#6 lore raw

Re: [PATCH v3 3/3] arm64: dts: allwinner: add Radxa Cubie A7S board

Thank you for your contribution! Sashiko AI review found 3 potential issues to consider: - [High] arm64: dts: allwinner: cubie-a7s DTB build fails on missing A733 CCU headers - [High] arm64: dts…

Thank you for your contribution! Sashiko AI review found 3 potential issues to consider:
- [High] arm64: dts: allwinner: cubie-a7s DTB build fails on missing A733 CCU headers
- [High] arm64: dts: allwinner: unsupported x-powers,axp318w PMIC blocks consumer probe
- [High] arm64: dts: allwinner: cubie-a7s sets 1.8V vcc-pf-supply for 3.3V-only mmc0
--

commit 572e2012767dbd5d4ea9dfb9c1da49853b19d780
Author: Enzo Adriano <[email protected]>

arm64: dts: allwinner: add Radxa Cubie A7S board

This commit adds the device tree for the Radxa Cubie A7S board based on the Allwinner A733 SoC, enabling UART0, the AXP318W PMIC, and MMC0, and wires it into the sunxi DTB build.

arch/arm64/boot/dts/allwinner/Makefile dtb-$(CONFIG_ARCH_SUNXI) += sun55i-a527-cubie-a5e.dtb · line 71

Quoted 9 lines
arch/arm64/boot/dts/allwinner/Makefile +1 -0
index d1f768dd6461d..792152525b433 100644
@@ -68,3 +68,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun55i-a527-cubie-a5e.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun55i-h728-x96qpro+.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun55i-t527-avaota-a1.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun55i-t527-orangepi-4a.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun60i-a733-cubie-a7s.dtb

[Severity: High]
Does adding sun60i-a733-cubie-a7s.dtb to dtb-$(CONFIG_ARCH_SUNXI) break the DTB build?

sun60i-a733-cubie-a7s.dts includes sun60i-a733.dtsi and references CLK_BUS_R_RTC and CLK_R_AHB in the &rtc node, and sun60i-a733.dtsi includes:

arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi {
	#include <dt-bindings/clock/allwinner,sun60i-a733-ccu.h>
	#include <dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/reset/allwinner,sun60i-a733-ccu.h>
	#include <dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h>
}

None of those four A733 clock and reset binding headers exist in include/dt-bindings/, so compiling dtbs with CONFIG_ARCH_SUNXI enabled fails at the preprocessor stage. In addition, there are no in-tree drivers for allwinner,sun60i-a733-ccu or allwinner,sun60i-a733-r-ccu to provide clocks and resets at runtime.

Quoted 5 lines
arch/arm64/boot/dts/allwinner/sun60i-a733-cubie-a7s.dts new file +0 -0
new file mode 100644
index 0000000000000..341c24360ce29

[ ... ]

Quoted 13 lines

+&mmc0 {

arch/arm64/boot/dts/allwinner/sun60i-a733-cubie-a7s.dts new file +12 -0
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
+	disable-wp;
+	max-frequency = <50000000>;
+	no-1-8-v;
+	vmmc-supply = <&reg_swout2>;
+	/* The 3.3 V path uses VCC-IO; no Port F voltage switching yet. */
+	vqmmc-supply = <&reg_swout2>;
+	status = "okay";
+};
+

arch/arm64/boot/dts/allwinner/sun60i-a733-cubie-a7s.dts line 100

Quoted 10 lines
arch/arm64/boot/dts/allwinner/sun60i-a733-cubie-a7s.dts new file +10 -0
+&osc {
+	clock-frequency = <26000000>;
+};
+
+&pio {
+	vcc-pb-supply = <&reg_swout2>;
+	vcc-pc-supply = <&reg_cldo5>;
+	vcc-pd-supply = <&reg_swout1>;
+	vcc-pe-supply = <&reg_bldo1>;
+	vcc-pf-supply = <&reg_cldo5>;

[Severity: High]
Will setting vcc-pf-supply = <&reg_cldo5> configure Port F's IO bias for 1.8 V while &mmc0 operates at 3.3 V?

&mmc0 uses Port F pins (PF0-PF6) with no-1-8-v and vqmmc-supply = <&reg_swout2> for 3.3 V signaling, whereas reg_cldo5 is fixed at 1800000 uV. When mmc0 requests its pins, sunxi_pmx_request() -> sunxi_pinctrl_set_io_bias_cfg() reads the voltage of vcc-pf-supply and programs the bank's PIO_POW_MOD_SEL bit for 1.8 V whenever uV <= 1800000, mismatching the 3.3 V SD signaling path. Pointing vcc-pf-supply at the 3.3 V supply (&reg_swout2, with a defined 3.3 V voltage or parent supply) would keep Port F's bias configuration aligned with 3.3 V signaling.

Quoted 20 lines
arch/arm64/boot/dts/allwinner/sun60i-a733-cubie-a7s.dts new file +20 -0
+	vcc-pg-supply = <&reg_aldo1>;
+	vcc-ph-supply = <&reg_swout2>;
+	vcc-pj-supply = <&reg_swout1>;
+	vcc-pk-supply = <&reg_bldo1>;
+};
+
+&r_i2c0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&r_i2c0_pl_pins>;
+
+	axp318w: pmic@36 {
+		compatible = "x-powers,axp318w";
+		reg = <0x36>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		aldo156in-supply = <&reg_ps>;

arch/arm64/boot/dts/allwinner/sun60i-a733-cubie-a7s.dts line 130

Quoted 10 lines
arch/arm64/boot/dts/allwinner/sun60i-a733-cubie-a7s.dts new file +10 -0
+		aldo234in-supply = <&reg_aldo1>;
+		bldoin-supply = <&reg_ldo_input>;
+		cldoin-supply = <&reg_ldo_input>;
+		dldoin-supply = <&reg_ps>;
+		eldoin-supply = <&reg_dcdc9>;
+		ips-supply = <&reg_ps>;
+		vin19-supply = <&reg_ps>;
+		vin23-supply = <&reg_ps>;
+		vin45-supply = <&reg_ps>;
+		vin678-supply = <&reg_ps>;

[Severity: High]
Does axp318w prevent &pio, &uart0, and &mmc0 from probing because "x-powers,axp318w" has no in-tree driver or DT binding?

Neither drivers/mfd/axp20x*.c, drivers/regulator/axp20x-regulator.c, nor Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml supports "x-powers,axp318w" (or its grouped input supplies and swout1/swout2/dcdc8/dcdc9 regulators). Because &pio, &r_pio, and &mmc0 reference child regulator nodes under axp318w, of_regulator_dev_lookup() finds the DT nodes without registered regulator devices and returns -EPROBE_DEFER, causing sunxi_pmx_request() for uart0 and mmc0 as well as mmc_regulator_get_supply() to defer indefinitely.

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=3
author
#7 lore raw
In reply to Enzo Adriano
Quoted 2 lines

[4] A733 8250_dw v2, patches 2-4:
https://lore.kernel.org/r/[email protected]

Correction: the runtime dependency is patches 1-4, the complete posted v2 series. Patch 2/4 needs context introduced by 1/4, which is absent from v7.4-rc1 and the checked tty-next and next-20261109 snapshots; all four applied cleanly together.

AXP318W PMIC v8 5/5 also needs a context-only change on v7.4-rc1 from sizeof(*desc) to sizeof(*new_desc), introduced by b53a09c957b68. After IRQ-bank v3, pinctrl voltage-mode v3 needs its hunk context adjusted to the IRQ-bank map; its voltage-mode change is unchanged.
The older clock helpers are already in v7.4-rc1; no other input adaptation was needed, and DT v3 itself applied with ordinary git am.

Quoted 1 line

Untested: boot with pinctrl v3, card writes, hotplug, 1.8 V switching,

DT v3 with pinctrl v3 reached an initramfs shell on one Cubie A7S with vendor firmware. In these boots, warm reboot returned to vendor Linux only with bus-r-riscv and bus-r-msgbox marked critical (firmware-clock patch [5]). No card-write, hotplug, 1.8 V switching or other functional coverage was added, and no new schema check was run.

Thanks,
Enzo