dt-bindings: msm: disp: add yaml schemas for DPU and DSI bindings
Subsystems (5)
PATCH v9 1/2 dt-bindings: msm: disp: add yaml schemas for DPU and DSI bindings
MSM Mobile Display Subsytem (MDSS) encapsulates sub-blocks like DPU display controller, DSI etc. Add YAML schema for the device tree bindings for the same.
Changes in v2:
- Changed dpu to DPU (Sam Ravnborg)
- Fixed indentation issues (Sam Ravnborg)
- Added empty line between different properties (Sam Ravnborg)
- Replaced reference txt files with their corresponding yaml files (Sam Ravnborg)
- Modified the file to use "|" only when it is necessary (Sam Ravnborg)
Changes in v3:
- Corrected the license used (Rob Herring)
- Added maxItems for properties (Rob Herring)
- Dropped generic descriptions (Rob Herring)
- Added ranges property (Rob Herring)
- Corrected the indendation (Rob Herring)
- Added additionalProperties (Rob Herring)
- Split dsi file into two, one for dsi controller and another one for dsi phy per target (Rob Herring)
- Corrected description for pinctrl-names (Rob Herring)
- Corrected the examples used in yaml file (Rob Herring)
- Delete dsi.txt and dpu.txt (Rob Herring)
Changes in v4:
- Move schema up by one level (Rob Herring)
- Add patternProperties for mdp node (Rob Herring)
- Corrected description of some properties (Rob Herring)
Changes in v5:
- Correct the indentation (Rob Herring)
- Remove unnecessary description from properties (Rob Herring)
- Correct the number of interconnect entries (Rob Herring)
- Add interconnect names for sc7180 (Rob Herring)
- Add description for ports (Rob Herring)
- Remove common properties (Rob Herring)
- Add unevalutatedProperties (Rob Herring)
- Reference existing dsi controller yaml in the common dsi controller file (Rob Herring)
- Correct the description of clock names to include only the clocks that are required (Rob Herring)
- Remove properties which are already covered under the common binding (Rob Herring)
- Add dsi phy supply nodes which are required for sc7180 and sdm845 targets (Rob Herring)
- Add type ref for syscon-sfpb (Rob Herring)
Changes in v6:
- Fixed errors during dt_binding_check (Rob Herring)
- Add maxItems for phys and phys-names (Rob Herring)
- Use unevaluatedProperties wherever required (Rob Herring)
- Removed interrupt controller from required properties for dsi controller (Rob Herring)
- Add constraints for dsi-phy reg-names based on the compatible phy version (Rob Herring)
- Add constraints for dsi-phy supply nodes based on the compatible phy version (Rob Herring)
Changes in v7:
- Add default value for qcom,mdss-mdp-transfer-time-us (Rob Herring)
- Modify the schema for data-lanes (Rob Herring)
- Split the phy schema into separate schemas based on the phy version (Rob Herring)
Changes in v8:
- Resolve merge conflicts with latest dsi.txt file
- Include dp yaml change also in the same series
Changes in v9:
- Combine target specific dsi controller yaml files to a single yaml file (Rob Herring)
- Combine target specific dsi phy yaml files into a single yaml file (Rob Herring)
- Use unevaluatedProperties and additionalProperties wherever required
- Remove duplicate properties from common yaml files
--- .../bindings/display/msm/dpu-sc7180.yaml | 235 +++++++++++++++++++ .../bindings/display/msm/dpu-sdm845.yaml | 216 ++++++++++++++++++ .../devicetree/bindings/display/msm/dpu.txt | 141 ------------ .../display/msm/dsi-common-controller.yaml | 235 +++++++++++++++++++ .../bindings/display/msm/dsi-controller-main.yaml | 119 ++++++++++ .../bindings/display/msm/dsi-phy-10nm.yaml | 64 ++++++ .../bindings/display/msm/dsi-phy-14nm.yaml | 64 ++++++ .../bindings/display/msm/dsi-phy-20nm.yaml | 68 ++++++ .../bindings/display/msm/dsi-phy-28nm.yaml | 64 ++++++ .../devicetree/bindings/display/msm/dsi-phy.yaml | 81 +++++++ .../devicetree/bindings/display/msm/dsi.txt | 249 --------------------- 11 files changed, 1146 insertions(+), 390 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy.yaml delete mode 100644 Documentation/devicetree/bindings/display/msm/dsi.txt
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +235 -0
@@ -0,0 +1,235 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DPU dt properties. + +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS and DPU are mentioned for SC7180 target. + +properties: + compatible: + items: + - const: qcom,sc7180-mdss + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + iommus: + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + interconnects: + description: | + Interconnect path specifier for MDSS according to + Documentation/devicetree/bindings/interconnect/interconnect.txt. + An entry should contain 2 paths corresponding to 2 AXI ports representing + source and destination ports. + minItems: 1 + + interconnect-names: + description: | + MDSS will have 2 port names to differentiate between the + 2 interconnect paths defined with interconnect specifier. + items: + - const: mdp0-mem + + assigned-clocks: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + +patternProperties: + "^mdp@[0-9a-f]+$": + type: object + description: Node containing the properties of DPU. + + properties: + compatible: + items: + - const: qcom,sc7180-dpu + + reg: + maxItems: 2 + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + maxItems: 6 + + clock-names: + description: | + Device clock names, must be in same order as clocks property. + The following clocks are required. + items: + - const: bus + - const: iface + - const: rot + - const: lut + - const: core + - const: vsync + + interrupts: + maxItems: 1 + + ports: + type: object + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. These + are described by the standard properties documented in files + mentioned below. + + Documentation/devicetree/bindings/graph.txt + Documentation/devicetree/bindings/media/video-interfaces.txt + + properties: + port@0: + type: object + description: DPU_INTF1 (DSI1) + port@1: + type: object + description: DPU_INTF2 (DSI2) + + assigned-clocks: + maxItems: 4 + + assigned-clock-rates: + maxItems: 4 + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - clock-names + - interrupts + - interrupt-controller + - iommus + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sc7180.h> + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sdm845.h> + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + + mdss: mdss@ae00000 { + compatible = "qcom,sc7180-mdss"; + reg = <0 0xae00000 0 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + clock-names = "iface", "ahb", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; + + interconnect-names = "mdp0-mem"; + + iommus = <&apps_smmu 0x800 0x2>; + + #address-cells = <2>; + #size-cells = <2>; + + mdp: mdp@ae01000 { + compatible = "qcom,sc7180-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "rot", "lut", "core", + "vsync"; + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>; + assigned-clock-rates = <300000000>, + <19200000>, + <19200000>, + <19200000>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + }; + }; +...
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +216 -0
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Documentation/devicetree/bindings/display/msm/dpu.txt deleted +0 -141
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Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +235 -0
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Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +119 -0
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Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml new file +64 -0
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Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml new file +64 -0
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Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml new file +68 -0
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Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml new file +64 -0
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Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +81 -0
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Signature · 1 line
2.7.4
PATCH v9 2/2 dt-bindings: msm/dp: Add bindings of MSM DisplayPort controller
Changes in v10:
- Change title of this patch as it does not contain PLL bindings anymore
- Remove redundant properties
- Remove use of IRQ flag
- Fix ports property
Previous Change log:
https://lkml.kernel.org/lkml/[email protected]/
--- .../bindings/display/msm/dp-controller.yaml | 120 +++++++++++++++++++++ .../bindings/display/msm/dpu-sc7180.yaml | 10 ++ 2 files changed, 130 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller.yaml
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +120 -0
@@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MSM Display Port Controller. + +maintainers: + - Chandan Uddaraju <[email protected]> + - Vara Reddy <[email protected]> + - Tanmay Shah <[email protected]> + +description: | + Device tree bindings for DisplayPort host controller for MSM targets + that are compatible with VESA DisplayPort interface specification. + +properties: + compatible: + enum: + - qcom,sc7180-dp + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: AHB clock to enable register access + - description: Display Port AUX clock + - description: Display Port Link clock + - description: Link interface clock between DP and PHY + - description: Display Port Pixel clock + + clock-names: + items: + - const: core_iface + - const: core_aux + - const: ctrl_link + - const: ctrl_link_iface + - const: stream_pixel + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: Input endpoint of the controller. + + port@1: + type: object + description: Output endpoint of the controller. + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,dispcc-sc7180.h> + + mdss: mdss { + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + + msm_dp: displayport-controller@ae90000 { + compatible = "qcom,sc7180-dp"; + reg = <0 0xae90000 0 0x1400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { + }; + }; + }; + }; + }; +...
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml +10 -0
@@ -132,6 +132,9 @@ patternProperties: port@1: type: object description: DPU_INTF2 (DSI2) + port@2: + type: object + description: DPU_INTF0 (DP) assigned-clocks: maxItems: 4
@@ -228,6 +231,13 @@ examples: remote-endpoint = <&dsi0_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; + }; + }; }; }; };
Signature · 1 line
2.7.4
Re: [PATCH v9 2/2] dt-bindings: msm/dp: Add bindings of MSM DisplayPort controller
Quoting Krishna Manikandan (2020-12-10 23:09:45)
Quoted 8 lines
Changes in v10:
- Change title of this patch as it does not contain PLL bindings anymore
- Remove redundant properties
- Remove use of IRQ flag
- Fix ports propertyPrevious Change log:
https://lkml.kernel.org/lkml/[email protected]/
Why can't that be put in here instead of making me click the link?
Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 1
Quoted 7 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +1
-0@@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
Why two spaces between 'only and 'OR'?
Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 7
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +6
-0+%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MSM Display Port Controller.
Drop the full-stop?
Quoted 26 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +26
-0+ +maintainers: + - Chandan Uddaraju <[email protected]> + - Vara Reddy <[email protected]> + - Tanmay Shah <[email protected]> + +description: | + Device tree bindings for DisplayPort host controller for MSM targets + that are compatible with VESA DisplayPort interface specification. + +properties: + compatible: + enum: + - qcom,sc7180-dp + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: AHB clock to enable register access + - description: Display Port AUX clock + - description: Display Port Link clock
Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 43
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +10
-0+ - description: Link interface clock between DP and PHY + - description: Display Port Pixel clock + + clock-names: + items: + - const: core_iface + - const: core_aux + - const: ctrl_link + - const: ctrl_link_iface + - const: stream_pixel
There should be a dp-phy too, so 'phy' and 'phy-names' property. I see a 'power-domains' property downstream, so please add that too. And also '#sound-dai-cells".
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +10
-0+ + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + properties: + "#address-cells": + const: 1 +
Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 63
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +10
-0+ "#size-cells": + const: 0 + + port@0: + type: object + description: Input endpoint of the controller. + + port@1: + type: object + description: Output endpoint of the controller.
This should have a required section too, and state that all the above properties are required.
Quoted 9 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +9
-0+ + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names
Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 82
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +10
-0+ - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,dispcc-sc7180.h> + + mdss: mdss {
Can drop the label. Also this node name is bad! Should be 'subsystem@<reg>' I guess? And then the reg can just be the first address in a reg property that is remapped for the children nodes.
Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 87
Quoted 5 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +5
-0+ #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + + msm_dp: displayport-controller@ae90000 {
Can drop the label.
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +10
-0+ compatible = "qcom,sc7180-dp"; + reg = <0 0xae90000 0 0x1400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", "core_aux",
Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 107
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +10
-0+ "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp_in: endpoint {
Can drop the label.
Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 114
Quoted 7 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +7
-0+ remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint {
Can drop the label and show some remote-endpoint connection?
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +6
-0+ }; + }; + }; + }; + }; +...
Re: [PATCH v9 2/2] dt-bindings: msm/dp: Add bindings of MSM DisplayPort controller
Quoted 8 lines · Stephen Boyd
Quoting Krishna Manikandan (2020-12-10 23:09:45)
Quoted 7 lines
Changes in v10:
- Change title of this patch as it does not contain PLL bindings anymore
- Remove redundant properties
- Remove use of IRQ flag
- Fix ports property
Quoted 5 lines
Quoted 2 lines
Previous Change log:
https://lkml.kernel.org/lkml/[email protected]/Why can't that be put in here instead of making me click the link?
Thanks Stephen for reviews.
I just wanted to use space efficiently. But if it helps in reviews, I will bring all the previous change logs back.
Quoted 102 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 1
Quoted 9 lines
diff --git
a/Documentation/devicetree/bindings/display/msm/dp-controller.yamlb/Documentation/devicetree/bindings/display/msm/dp-controller.yamlnew file mode 100644
index 0000000..bc80632Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +1
-0@@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)Why two spaces between 'only and 'OR'?
Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 7
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +6
-0+%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MSM Display Port Controller.Drop the full-stop?
Quoted 27 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +8
-0+ +maintainers: + - Chandan Uddaraju <[email protected]> + - Vara Reddy <[email protected]> + - Tanmay Shah <[email protected]> + +description: | + Device tree bindings for DisplayPort host controller for MSMtargets
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +18
-0+ that are compatible with VESA DisplayPort interface specification. + +properties: + compatible: + enum: + - qcom,sc7180-dp + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: AHB clock to enable register access + - description: Display Port AUX clock + - description: Display Port Link clockDocumentation/devicetree/bindings/display/msm/dp-controller.yaml line 43
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +10
-0+ - description: Link interface clock between DP and PHY + - description: Display Port Pixel clock + + clock-names: + items: + - const: core_iface + - const: core_aux + - const: ctrl_link + - const: ctrl_link_iface + - const: stream_pixelThere should be a dp-phy too, so 'phy' and 'phy-names' property. I see a 'power-domains' property downstream, so please add that too. And also '#sound-dai-cells".
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +10
-0+ + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + properties: + "#address-cells": + const: 1 +Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 63
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +10
-0+ "#size-cells": + const: 0 + + port@0: + type: object + description: Input endpoint of the controller. + + port@1: + type: object + description: Output endpoint of the controller.This should have a required section too, and state that all the above properties are required.
Quoted 15 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +15
-0+ + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - |
Quoted 9 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 82
Quoted 4 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +4
-0+ #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,dispcc-sc7180.h> + + mdss: mdss {Can drop the label. Also this node name is bad! Should be 'subsystem@<reg>' I guess? And then the reg can just be the first address in a reg property that is remapped for the children nodes.
I didn't get this part:
"And then the reg can just be the first address in a reg property that is remapped for children nodes."
Does this mean, I should add reg property for mdss node as well? Node mdss address is 0x0ae00000. So something like:
reg = <0 0x0ae00000 0 0x1000>;
Quoted 39 lines
Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 87
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Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +5
-0+ #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + + msm_dp: displayport-controller@ae90000 {Can drop the label.
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Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +10
-0+ compatible = "qcom,sc7180-dp"; + reg = <0 0xae90000 0 0x1400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", "core_aux",Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 107
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Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +10
-0+ "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp_in: endpoint {Can drop the label.
Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 114
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Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +7
-0+ remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint {
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Can drop the label and show some remote-endpoint connection?
I am not sure what should I include here as connection. IIRC, Robh suggested It should connect to the Type-C connector through some sort of mixing node. However, I see only typec connector node at: Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml. Should we use that directly or should we use ec node?
Can we do something like:
remote-endpoint = <&typec> or <&ec>
Rest of the comments looks good and I will address them in next patch.
Thanks.
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Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +6
-0+ }; + }; + }; + }; + }; +...
Re: [PATCH v9 2/2] dt-bindings: msm/dp: Add bindings of MSM DisplayPort controller
Quoting Tanmay Shah (2020-12-17 14:52:54)
Quoted 12 lines · Stephen Boyd
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Quoting Krishna Manikandan (2020-12-10 23:09:45)
Quoted 9 lines
Changes in v10:
- Change title of this patch as it does not contain PLL bindings anymore
- Remove redundant properties
- Remove use of IRQ flag
- Fix ports propertyPrevious Change log:
https://lkml.kernel.org/lkml/[email protected]/
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Why can't that be put in here instead of making me click the link?
Thanks Stephen for reviews.
I just wanted to use space efficiently. But if it helps in reviews, I will bring all the previous change logs back.
Or it can be left under the cut (---). This is probably going to merge through the binding tree so it doesn't follow drm practice of putting version history in the commit text.
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diff --git
a/Documentation/devicetree/bindings/display/msm/dp-controller.yamlb/Documentation/devicetree/bindings/display/msm/dp-controller.yamlnew file mode 100644
index 0000000..bc80632Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +0
-0
[...]
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Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 82
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Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +5
-0+ - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,dispcc-sc7180.h> + + mdss: mdss {Can drop the label. Also this node name is bad! Should be 'subsystem@<reg>' I guess? And then the reg can just be the first address in a reg property that is remapped for the children nodes.
Quoted 9 lines
I didn't get this part:
"And then the reg can just be the first address in a reg property that is remapped for children nodes."Does this mean, I should add reg property for mdss node as well? Node mdss address is
0x0ae00000. So something like:reg = <0
0x0ae0000000x1000>;
Yes and then a ranges property so that child nodes can figure out their reg property appropriately.
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Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +3
-0+ #address-cells = <2>; + #size-cells = <2>; + interrupt-controller;
[...]
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Documentation/devicetree/bindings/display/msm/dp-controller.yaml line 114
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Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +7
-0+ remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint {Can drop the label and show some remote-endpoint connection?
I am not sure what should I include here as connection. IIRC, Robh suggested It should connect to the Type-C connector through some sort of mixing node. However, I see only typec connector node at:
Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml. Should we use that directly or should we use ec node?
Quoted 3 lines
Can we do something like:
remote-endpoint = <&typec> or <&ec>
Sure. I suppose <&typec> would work.
Quoting Krishna Manikandan (2020-12-10 23:09:44)
Quoted 4 lines
.../bindings/display/msm/dpu-sc7180.yaml | 235 +++++++++++++++++++ .../bindings/display/msm/dpu-sdm845.yaml | 216 ++++++++++++++++++ .../devicetree/bindings/display/msm/dpu.txt | 141 ------------ .../display/msm/dsi-common-controller.yaml | 235 +++++++++++++++++++
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.../bindings/display/msm/dsi-controller-main.yaml | 119 ++++++++++ .../bindings/display/msm/dsi-phy-10nm.yaml | 64 ++++++ .../bindings/display/msm/dsi-phy-14nm.yaml | 64 ++++++ .../bindings/display/msm/dsi-phy-20nm.yaml | 68 ++++++ .../bindings/display/msm/dsi-phy-28nm.yaml | 64 ++++++ .../devicetree/bindings/display/msm/dsi-phy.yaml | 81 +++++++ .../devicetree/bindings/display/msm/dsi.txt | 249 --------------------- 11 files changed, 1146 insertions(+), 390 deletions(-)
This is quite a bit to review. Any chance to split it up into different patches? Looks like that could be: dpu, phy, and dsi to make this a bit more reviewable.
Quoted 18 lines
create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy.yaml delete mode 100644 Documentation/devicetree/bindings/display/msm/dsi.txtDocumentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +0
-0
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 7
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +7
-0@@ -0,0 +1,235 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DPU dt properties.
Drop the full stop?
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 20
Quoted 13 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +13
-0+ +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS and DPU are mentioned for SC7180 target. + +properties: + compatible: + items: + - const: qcom,sc7180-mdss
Add a newline here please.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 31
Quoted 11 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +11
-0+ reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + maxItems: 3
items:
- const: "description"
...
Quoted 22 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +22
-0+ + clock-names: + items: + - const: iface + - const: ahb + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + iommus: + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells":
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 63
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +10
-0+ const: 2 + + ranges: true + + interconnects: + description: | + Interconnect path specifier for MDSS according to + Documentation/devicetree/bindings/interconnect/interconnect.txt. + An entry should contain 2 paths corresponding to 2 AXI ports representing + source and destination ports.
Why such a long description?
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 64
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +1
-0+ minItems: 1
Why not items: and then a const element with description?
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 69
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +5
-0+ + interconnect-names: + description: | + MDSS will have 2 port names to differentiate between the + 2 interconnect paths defined with interconnect specifier.
Drop description?
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 77
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +8
-0+ items: + - const: mdp0-mem + + assigned-clocks: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1
Are these properties necessary? Aren't they able to be applied to any node? Seems like they don't need to be called out here.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 80
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +3
-0+ +patternProperties: + "^mdp@[0-9a-f]+$":
Name should be 'display-controller'?
Quoted 13 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +13
-0+ type: object + description: Node containing the properties of DPU. + + properties: + compatible: + items: + - const: qcom,sc7180-dpu + + reg: + maxItems: 2 + + reg-names: + items:
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 103
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +10
-0+ - const: mdp + - const: vbif + + clocks: + maxItems: 6 + + clock-names: + description: | + Device clock names, must be in same order as clocks property. + The following clocks are required.
Just drop this description and have items.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 113
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +10
-0+ items: + - const: bus + - const: iface + - const: rot + - const: lut + - const: core + - const: vsync + + interrupts: + maxItems: 1
It's optional?
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +8
-0+ + ports: + type: object + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. These
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 131
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +10
-0+ are described by the standard properties documented in files + mentioned below. + + Documentation/devicetree/bindings/graph.txt + Documentation/devicetree/bindings/media/video-interfaces.txt + + properties: + port@0: + type: object + description: DPU_INTF1 (DSI1)
Add a newline please.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 140
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +9
-0+ port@1: + type: object + description: DPU_INTF2 (DSI2) + + assigned-clocks: + maxItems: 4 + + assigned-clock-rates: + maxItems: 4
These two properties can be dropped.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 145
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +5
-0+ +required: + - compatible + - reg + - reg-names
reg-names shouldn't be required.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 148
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +3
-0+ - power-domains + - clocks + - clock-names
Same for clock-names technically.
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +4
-0+ - interrupts + - interrupt-controller + - iommus +
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 162
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +10
-0+additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sc7180.h> + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sdm845.h> + + soc: soc {
Is this node needed? Seems like we can remove it.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 166
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +4
-0+ #address-cells = <2>; + #size-cells = <2>; + + mdss: mdss@ae00000 {
Node name should be something like 'subsystem@<reg>'.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 169
Quoted 3 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +3
-0+ compatible = "qcom,sc7180-mdss"; + reg = <0 0xae00000 0 0x1000>; + reg-names = "mdss";
Please drop this useless reg-names.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 175
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +6
-0+ power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; +
Drop newline?
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 179
Quoted 4 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +4
-0+ clock-names = "iface", "ahb", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>;
Ok I guess.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 186
Quoted 7 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +7
-0+ + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; +
Drop newline please.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 192
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +6
-0+ interconnect-names = "mdp0-mem"; + + iommus = <&apps_smmu 0x800 0x2>; + + #address-cells = <2>; + #size-cells = <2>;
Can this be much higher up?
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 194
Quoted 2 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +2
-0+ + mdp: mdp@ae01000 {
Node name needs some work. Drop label?
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 197
Quoted 3 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +3
-0+ compatible = "qcom,sc7180-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>;
Wow size ends in 8!
Quoted 5 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +5
-0+ + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>,
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 212
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Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +10
-0+ <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "rot", "lut", "core", + "vsync"; + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>;
Is ROT_CLK here twice for some reason?
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 219
Quoted 7 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +7
-0+ assigned-clock-rates = <300000000>, + <19200000>, + <19200000>, + <19200000>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
Drop flags?
Quoted 27 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +16
-0+ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + }; + }; +...Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +5
-0@@ -0,0 +1,216 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml line 15
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +10
-0+ +title: Description of Qualcomm Display DPU dt properties. + +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS and DPU are mentioned for SDM845 target.
Is this substantially different from the previous binding? Can they just be merged together?
Quoted 377 lines
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +201
-0+ +properties: + compatible: + items: + - const: qcom,sdm845-mdss + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + description: | + Device clock names in the same order as mentioned in clocks property. + The required clocks are mentioned below. + items: + - const: iface + - const: bus + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + iommus: + maxItems: 2 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + assigned-clocks: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + +patternProperties: + "^mdp@[0-9a-f]+$": + type: object + description: Node containing the properties of DPU. + + properties: + compatible: + items: + - const: qcom,sdm845-dpu + reg: + maxItems: 2 + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + maxItems: 4 + + clock-names: + description: | + Device clock names, must be in same order as clocks property. + The following clocks are required. + items: + - const: iface + - const: bus + - const: core + - const: vsync + + interrupts: + maxItems: 1 + + ports: + type: object + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. These + are described by the standard properties documented in files + mentioned below. + + Documentation/devicetree/bindings/graph.txt + Documentation/devicetree/bindings/media/video-interfaces.txt + + properties: + port@0: + type: object + description: DPU_INTF1 (DSI1) + port@1: + type: object + description: DPU_INTF2 (DSI2) + + assigned-clocks: + maxItems: 2 + + assigned-clock-rates: + maxItems: 2 + + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - clock-names + - interrupts + - interrupt-controller + - iommus + +additionalProperties: false + +examples: +- | + #include <dt-bindings/clock/qcom,dispcc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + + mdss: mdss@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + #address-cells = <2>; + #size-cells = <2>; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <300000000>, + <19200000>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + }; + }; +...Documentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-141@@ -1,141 +0,0 @@ -Qualcomm Technologies, Inc. DPU KMS - -Description: - -Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates -sub-blocks like DPU display controller, DSI and DP interfaces etc. -The DPU display controller is found in SDM845 SoC. - -MDSS: -Required properties: -- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss" -- reg: physical base address and length of contoller's registers. -- reg-names: register region names. The following region is required: - * "mdss" -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt -- clocks: list of clock specifiers for clocks needed by the device. -- clock-names: device clock names, must be in same order as clocks property. - The following clocks are required: - * "iface" - * "bus" - * "core" -- interrupts: interrupt signal from MDSS. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- iommus: phandle of iommu device node. -- #address-cells: number of address cells for the MDSS children. Should be 1. -- #size-cells: Should be 1. -- ranges: parent bus address space is the same as the child bus address space. -- interconnects : interconnect path specifier for MDSS according to - Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be - 2 paths corresponding to 2 AXI ports. -- interconnect-names : MDSS will have 2 port names to differentiate between the - 2 interconnect paths defined with interconnect specifier. - -Optional properties: -- assigned-clocks: list of clock specifiers for clocks needing rate assignment -- assigned-clock-rates: list of clock frequencies sorted in the same order as - the assigned-clocks property. - -MDP: -Required properties: -- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu" -- reg: physical base address and length of controller's registers. -- reg-names : register region names. The following region is required: - * "mdp" - * "vbif" -- clocks: list of clock specifiers for clocks needed by the device. -- clock-names: device clock names, must be in same order as clocks property. - The following clocks are required. - * "bus" - * "iface" - * "core" - * "vsync" -- interrupts: interrupt line from DPU to MDSS. -- ports: contains the list of output ports from DPU device. These ports connect - to interfaces that are external to the DPU hardware, such as DSI, DP etc. - - Each output port contains an endpoint that describes how it is connected to an - external interface. These are described by the standard properties documented - here: - Documentation/devicetree/bindings/graph.txt - Documentation/devicetree/bindings/media/video-interfaces.txt - - Port 0 -> DPU_INTF1 (DSI1) - Port 1 -> DPU_INTF2 (DSI2) - -Optional properties: -- assigned-clocks: list of clock specifiers for clocks needing rate assignment -- assigned-clock-rates: list of clock frequencies sorted in the same order as - the assigned-clocks property. - -Example: - - mdss: mdss@ae00000 { - compatible = "qcom,sdm845-mdss"; - reg = <0xae00000 0x1000>; - reg-names = "mdss"; - - power-domains = <&clock_dispcc 0>; - - clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "core"; - - assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - - interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>, - <&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>; - - interconnect-names = "mdp0-mem", "mdp1-mem"; - - iommus = <&apps_iommu 0>; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xae00000 0xb2008>; - - mdss_mdp: mdp@ae01000 { - compatible = "qcom,sdm845-dpu"; - reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, - <&clock_dispcc DISP_CC_MDSS_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, - <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; - - assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, - <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <0 0 300000000 19200000>; - - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - }; - };Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +23
-0@@ -0,0 +1,235 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-common-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI controller dt properties. + +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Common Device tree bindings for DSI controller. + +allOf: + - $ref: "../dsi-controller.yaml#" + +properties: + compatible: + items: + - const: qcom,mdss-dsi-ctrl + + vdd-supply:
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-0+ description: Phandle to vdd regulator device node. + + vddio-supply: + description: Phandle to vdd-io regulator device node. + + vdda-supply: + description: Phandle to vdda regulator device node. + + phys: + description: Phandle to DSI PHY device node.
Don't think we need descriptions on these.
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-0+ maxItems: 1
It's optional?
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-0+ + phy-names: + description: Name of the corresponding PHY device.
Doesn't seem like it's optional so just items: const?
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-0+ maxItems: 1 + + syscon-sfpb: + description: A phandle to mmss_sfpb syscon node (only for DSIv2). + $ref: "/schemas/types.yaml#/definitions/phandle" + + # Optional Properties for dsi controller
Weird tab?
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Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +12
-0+ qcom,mdss-mdp-transfer-time-us: + description: | + Specifies the DSI transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + DSI link rate since anyways this would be the maximum
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-0+ transfer time that could be achieved. + If ping pong split is enabled, this time should not be higher + than two times the DSI link rate time. + This is an optional property. + default: 14000 + + qcom,dual-dsi-mode: + type: boolean + description: | + Boolean value indicating if the DSI controller is
"Boolean value" is redundant.
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-0+ driving a panel which needs 2 DSI links.
Shouldn't this be a property of the panel?
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-0+ + qcom,master-dsi: + type: boolean + description: | + Boolean value indicating if the DSI controller is driving + the master link of the 2-DSI panel.
Shouldn't this be a property of the panel?
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-0+ + qcom,sync-dual-dsi: + type: boolean + description: | + Boolean value indicating if the DSI controller is driving a + 2-DSI panel whose 2 links need receive command simultaneously.
Shouldn't this be a property of the panel?
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-0+ + pinctrl-names: + description: The pin control state names. + items: + - const: default + - const: sleep + + pinctrl-0: + description: The default pinctrl state (active) + + pinctrl-1: + description: The sleep pinctrl state (suspend)
These can be left out? Doesn't seem like they're non-standard.
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Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +13
-0+ + ports: + type: object + description: | + Contains DSI controller input and output ports as children, each + containing one endpoint subnode as defined in + Documentation/devicetree/bindings/graph.txt and + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + port@0: + type: object + description: |
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-0+ Input endpoints of the controller. + + properties: + reg: + const: 0 + + endpoint: + type: object + properties: + remote-endpoint:
Can this and the properties below go into some generic binding instead of here?
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Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +14
-0+ description: | + For port@0, set to phandle of the connected panel/bridge's + input endpoint. For port@1, set to the MDP interface output. + See Documentation/devicetree/bindings/graph.txt for + device graph info. + + data-lanes: + description: | + This describes how the physical DSI data lanes are mapped + to the logical lanes on the given platform. The value contained in + index n describes what physical lane is mapped to the logical lane n + (DATAn, where n lies between 0 and 3). The clock lane position is fixed + and can't be changed. Hence, they aren't a part of the DT bindings. See + Documentation/devicetree/bindings/media/video-interfaces.txt for
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-0+ more info on the data-lanes property. + + For example: + data-lanes = <3 0 1 2>; + + The above mapping describes that the logical data lane DATA0 is mapped + to the physical data lane DATA3, logical DATA1 to physical DATA0, + logic DATA2 to phys DATA1 and logic DATA3 to phys DATA2. There are + only a limited number of physical to logical mappings possible. + oneOf:
That is a lot.
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Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +97
-0+ - items: + - const: 0 + - const: 1 + - const: 2 + - const: 3 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 0 + - items: + - const: 2 + - const: 3 + - const: 0 + - const: 1 + - items: + - const: 3 + - const: 0 + - const: 1 + - const: 2 + - items: + - const: 0 + - const: 3 + - const: 2 + - const: 1 + - items: + - const: 1 + - const: 0 + - const: 3 + - const: 2 + - items: + - const: 2 + - const: 1 + - const: 0 + - const: 3 + - items: + - const: 3 + - const: 2 + - const: 1 + - const: 0 + port@1: + type: object + description: | + Output endpoints of the controller. + properties: + reg: + const: 1 + + endpoint: + type: object + properties: + remote-endpoint: true + data-lanes: + oneOf: + - items: + - const: 0 + - const: 1 + - const: 2 + - const: 3 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 0 + - items: + - const: 2 + - const: 3 + - const: 0 + - const: 1 + - items: + - const: 3 + - const: 0 + - const: 1 + - const: 2 + - items: + - const: 0 + - const: 3 + - const: 2 + - const: 1 + - items: + - const: 1 + - const: 0 + - const: 3 + - const: 2 + - items: + - const: 2 + - const: 1 + - const: 0 + - const: 3 + - items: + - const: 3 + - const: 2 + - const: 1 + - const: 0 + +unevaluatedProperties: false +...Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +0
-0
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-0@@ -0,0 +1,119 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI controller dt properties.
Drop full stop?
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml line 16
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Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +9
-0+ +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Device tree bindings for DSI controller. + +allOf: + - $ref: dsi-common-controller.yaml#
That's neat, but now makes this harder to read?
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Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +6
-0+ +properties: + compatible: + const: qcom,mdss-dsi-ctrl + + reg:
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-0+ maxItems: 1 + + reg-names: + const: dsi_ctrl + + interrupts: + maxItems: 1 + + clocks: + maxItems: 6
items:
- description:
- description:
- description:
- description:
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-0+ + clock-names: + items: + - const: byte + - const: byte_intf + - const: pixel + - const: core + - const: iface + - const: bus
Indent seems wrong.
Quoted 190 lines
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +78
-0+ + phys: + maxItems: 1 + + phy-names: + const: dsi + + ports: true + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - phys + - phy-names + - ports + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,dispcc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + + mdss: mdss { + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + }; +...Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml new file +64
-0@@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI 10nm PHY dt properties. + +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Common Device tree bindings for DSI 10nm PHY. + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-10nm + - const: qcom,dsi-phy-10nm-8998 + + reg-names: + items: + - const: dsi_phy + - const: dsi_phy_lane + - const: dsi_pll + + clock-cells: + description: | + The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). + const: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + description: | + The following clocks are required. + items: + - const: iface + - const: ref + + vdds-supply: + description: | + Phandle to vdds regulator device node. + + qcom,dsi-phy-regulator-ldo-mode: + type: boolean + description: | + Boolean value indicating if the LDO mode PHY regulator is wanted (optional). + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - vdds-supply + +additionalProperties: true +...Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml new file +36
-0@@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI 14nm PHY dt properties. + +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Common Device tree bindings for DSI 14nm PHY. + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-14nm + - const: qcom,dsi-phy-14nm-660 + + reg-names: + items: + - const: dsi_phy + - const: dsi_phy_lane + - const: dsi_pll + + clock-cells: + description: | + The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). + const: 1 + + power-domains: + maxItems: 1 + + clocks:
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-0+ maxItems: 2 + + clock-names: + description: | + The following clocks are required. + items: + - const: iface + - const: ref + + qcom,dsi-phy-regulator-ldo-mode:
Please remove this property.
Quoted 40 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml new file +18
-0+ type: boolean + description: | + Boolean value indicating if the LDO mode PHY regulator is wanted (optional). + + vcca-supply: + description: | + Phandle to vcca regulator device node. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - vcca-supply + +additionalProperties: true +...Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml new file +16
-0@@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI 20nm PHY dt properties. + +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Common Device tree bindings for DSI 20nm PHY. + +properties: + compatible:
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-0+ oneOf: + - const: qcom,dsi-phy-20nm + + reg-names: + items: + - const: dsi_pll + - const: dsi_phy + - const: dsi_phy_regulator + + clock-cells:
Should be '#clock-cells'
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Quoted 4 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml new file +4
-0+ description: | + The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). + const: 1
i.e.
'#clock-cells':
const: 1
Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml line 40
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml new file +10
-0+ + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + description: | + The following clocks are required.
Please remove description.
Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml line 48
Quoted 8 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml new file +8
-0+ items: + - const: iface + - const: ref + + qcom,dsi-phy-regulator-ldo-mode: + type: boolean + description: | + Boolean value indicating if the LDO mode PHY regulator is wanted (optional).
Please remove this property.
Quoted 66 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml new file +20
-0+ + vcca-supply: + description: | + Phandle to vcca regulator device node. + + vddio-supply: + description: | + Phandle to vdd-io regulator device node. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - vddio-supply + - vcca-supply + +additionalProperties: true +...Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml new file +40
-0@@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI 28nm PHY dt properties. + +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Common Device tree bindings for DSI 28nm PHY. + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-28nm-hpm + - const: qcom,dsi-phy-28nm-lp + - const: qcom,dsi-phy-28nm-8960 + + reg-names: + items: + - const: dsi_pll + - const: dsi_phy + - const: dsi_phy_regulator + + clock-cells: + description: | + The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). + const: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names:
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml line 50
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml new file +10
-0+ description: | + The following clocks are required. + items: + - const: iface + - const: ref + + qcom,dsi-phy-regulator-ldo-mode: + type: boolean + description: | + Boolean value indicating if the LDO mode PHY regulator is wanted (optional).
Please remove this property.
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml line 54
Quoted 4 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml new file +4
-0+ + vddio-supply: + description: | + Phandle to vdd-io regulator device node.
Don't think we need | here, i.e just
vddio-supply:
description: vddIO supply for dsi controller.
Honestly it would be GREAT if this told us which PX_<N> pin on the SoC this is connected to so we don't have to dig through docs to figure out how the hardware block is connected to the power pins on the SoC. My understanding is the PX pins fan out to various hardware blocks inside the SoC, so 'vddio-supply' makes sense from the internal hardware block but at the edge of the SoC it is basically meaningless.
Quoted 26 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml new file +10
-0+ +required: + - compatible + - reg + - reg-names + - clocks + - vddio-supply + +additionalProperties: true +...Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +10
-0@@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI PHY dt properties. + +maintainers: + - Krishna Manikandan <[email protected]>
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml line 20
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +10
-0+ +description: | + Device tree bindings for DSI PHY. + +allOf: + - $ref: dsi-phy-10nm.yaml# + +properties: + compatible: + const: qcom,dsi-phy-10nm
This should be merged with dsi-phy-10nm? Nothing else references the dsi-phy-10nm.yaml binding so I'm confused why this is split from it.
Quoted 23 lines
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +23
-0+ + reg: + maxItems: 3 + + reg-names: + maxItems: 3 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: iface + - const: ref + + "#clock-cells": + const: 1 + + "#phy-cells": + const: 0 + +required: + - compatible
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml line 53
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +10
-0+ - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h>
This include is not used.
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml line 55
Quoted 2 lines
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +2
-0+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
This include is not used.
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml line 60
Quoted 5 lines
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +5
-0+ #include <dt-bindings/clock/qcom,rpmh.h> + + mdss: mdss { + #address-cells = <2>; + #size-cells = <2>;
Do we need this wrapper node? I guess it helps to know where to put this node but it's not enforced in the binding at all.
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml line 62
Quoted 2 lines
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +2
-0+ + dsi0_phy: dsi-phy@ae94400 {
Why not just 'phy@ae94400'?
Quoted 19 lines
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +19
-0+ compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + vdds-supply = <&vdda_mipi_dsi0_pll>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + }; + }; +...
Quoted 14 lines · Stephen Boyd
Quoting Krishna Manikandan (2020-12-10 23:09:44)
Quoted 4 lines
.../bindings/display/msm/dpu-sc7180.yaml | 235 +++++++++++++++++++ .../bindings/display/msm/dpu-sdm845.yaml | 216 ++++++++++++++++++ .../devicetree/bindings/display/msm/dpu.txt | 141 ------------ .../display/msm/dsi-common-controller.yaml | 235 +++++++++++++++++++Quoted 8 lines
.../bindings/display/msm/dsi-controller-main.yaml | 119 ++++++++++ .../bindings/display/msm/dsi-phy-10nm.yaml | 64 ++++++ .../bindings/display/msm/dsi-phy-14nm.yaml | 64 ++++++ .../bindings/display/msm/dsi-phy-20nm.yaml | 68 ++++++ .../bindings/display/msm/dsi-phy-28nm.yaml | 64 ++++++ .../devicetree/bindings/display/msm/dsi-phy.yaml | 81 +++++++ .../devicetree/bindings/display/msm/dsi.txt | 249 --------------------- 11 files changed, 1146 insertions(+), 390 deletions(-)
Quoted 3 lines
This is quite a bit to review. Any chance to split it up into different patches? Looks like that could be: dpu, phy, and dsi to make this a bit more reviewable.
Yes that would certainly be very helpful for review.
Also I noticed that phy binding seem quite similar with few additions, can we add a single binding document which documents .. or maybe check with Rob.. what is the guidance, single doc or multiple..?
Signature · 1 line
~Vinod
Hi Stephen,
Thank you for reviewing the patches. The latest patchsets have been uploaded in the below series. Please review the patches and provide your comments on them.
Series: https://patchwork.kernel.org/project/linux-arm-msm/list/?series=427607
Also, please find my comments on few of your queries on earlier patch below. All the other review comments are addressed in the latest patchset.
Quoted 156 lines · Stephen Boyd
Quoting Krishna Manikandan (2020-12-10 23:09:44)
Quoted 8 lines
.../bindings/display/msm/dpu-sc7180.yaml | 235 +++++++++++++++++++ .../bindings/display/msm/dpu-sdm845.yaml | 216 ++++++++++++++++++ .../devicetree/bindings/display/msm/dpu.txt | 141 ------------ .../display/msm/dsi-common-controller.yaml | 235 +++++++++++++++++++ .../bindings/display/msm/dsi-controller-main.yaml | 119 ++++++++++Quoted 8 lines
.../bindings/display/msm/dsi-phy-10nm.yaml | 64 ++++++ .../bindings/display/msm/dsi-phy-14nm.yaml | 64 ++++++ .../bindings/display/msm/dsi-phy-20nm.yaml | 68 ++++++ .../bindings/display/msm/dsi-phy-28nm.yaml | 64 ++++++ .../devicetree/bindings/display/msm/dsi-phy.yaml | 81 +++++++ .../devicetree/bindings/display/msm/dsi.txt | 249 --------------------- 11 files changed, 1146 insertions(+), 390 deletions(-)This is quite a bit to review. Any chance to split it up into different patches? Looks like that could be: dpu, phy, and dsi to make this a bit more reviewable.
Quoted 29 lines
create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy.yaml delete mode 100644
Documentation/devicetree/bindings/display/msm/dsi.txtDocumentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +0
-0Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 7
Quoted 7 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +7
-0@@ -0,0 +1,235 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DPU dt properties.Drop the full stop?
Quoted 9 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +6
-0+ +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Device tree bindings for MSM Mobile Display Subsytem(MDSS) thatencapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device treeDocumentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 20
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +6
-0+ bindings of MDSS and DPU are mentioned for SC7180 target. + +properties: + compatible: + items: + - const: qcom,sc7180-mdssAdd a newline here please.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 31
Quoted 11 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +11
-0+ reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + maxItems: 3items:
- const: "description"
...Quoted 30 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +30
-0+ + clock-names: + items: + - const: iface + - const: ahb + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + iommus: + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + interconnects: + description: | + Interconnect path specifier for MDSS according to +Quoted 4 lines
Documentation/devicetree/bindings/interconnect/interconnect.txt.
+ An entry should contain 2 paths corresponding to 2 AXI ports
representing
+ source and destination ports.Why such a long description?
Quoted 1 line
+ minItems: 1
Why not items: and then a const element with description?
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 69
Quoted 5 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +5
-0+ + interconnect-names: + description: | + MDSS will have 2 port names to differentiate between the + 2 interconnect paths defined with interconnect specifier.Drop description?
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 77
Quoted 8 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +8
-0+ items: + - const: mdp0-mem + + assigned-clocks: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1Are these properties necessary? Aren't they able to be applied to any node? Seems like they don't need to be called out here.
Quoted 5 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 80
Quoted 3 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +3
-0+ +patternProperties: + "^mdp@[0-9a-f]+$":Name should be 'display-controller'?
Display node name is mdp in the current dpu code
Quoted 80 lines
Quoted 23 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +22
-0+ type: object + description: Node containing the properties of DPU. + + properties: + compatible: + items: + - const: qcom,sc7180-dpu + + reg: + maxItems: 2 + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + maxItems: 6 + + clock-names: + description: | + Device clock names, must be in same order as clocksQuoted 2 lines
property.
+ The following clocks are required.Just drop this description and have items.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 113
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +10
-0+ items: + - const: bus + - const: iface + - const: rot + - const: lut + - const: core + - const: vsync + + interrupts: + maxItems: 1It's optional?
Quoted 19 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +5
-0+ + ports: + type: object + description: | + Contains the list of output ports from DPU device. Theseports
+ connect to interfaces that are external to the DPU
hardware,
+ such as DSI, DP etc. Each output port contains an endpoint
that
+ describes how it is connected to an external interface.
These
+ are described by the standard properties documented in
filesDocumentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +4
-0+ mentioned below. + + Documentation/devicetree/bindings/graph.txt +
Documentation/devicetree/bindings/media/video-interfaces.txtDocumentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 131
Quoted 5 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +5
-0+ + properties: + port@0: + type: object + description: DPU_INTF1 (DSI1)Add a newline please.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 140
Quoted 9 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +9
-0+ port@1: + type: object + description: DPU_INTF2 (DSI2) + + assigned-clocks: + maxItems: 4 + + assigned-clock-rates: + maxItems: 4These two properties can be dropped.
Quoted 7 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 145
Quoted 5 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +5
-0+ +required: + - compatible + - reg + - reg-namesreg-names shouldn't be required.
If reg-names are not defined, then probe will fail as io_remap uses register names during init in the current code. We can work on the source file changes to handle it for future chipsets
Quoted 7 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 148
Quoted 4 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +3
-0+ - power-domains + - clocks + - clock-namesSame for clock-names technically.
Quoted 16 lines
Quoted 4 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +4
-0+ - interrupts + - interrupt-controller + - iommus +Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 162
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +10
-0+additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sc7180.h> + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sdm845.h> + + soc: soc {Is this node needed? Seems like we can remove it.
In latest dt schema, there is a rule that we have to specify the address and size cells or else it will take default value of 1. This will result in error as display uses 2 address cells and 2 size cells.
Quoted 52 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 166
Quoted 5 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +4
-0+ #address-cells = <2>; + #size-cells = <2>; + + mdss: mdss@ae00000 {Node name should be something like 'subsystem@<reg>'.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 169
Quoted 3 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +3
-0+ compatible = "qcom,sc7180-mdss"; + reg = <0 0xae00000 0 0x1000>; + reg-names = "mdss";Please drop this useless reg-names.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 175
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +6
-0+ power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; +Drop newline?
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 179
Quoted 4 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +4
-0+ clock-names = "iface", "ahb", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>;Ok I guess.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 186
Quoted 7 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +7
-0+ + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; +Drop newline please.
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 192
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +6
-0+ interconnect-names = "mdp0-mem"; + + iommus = <&apps_smmu 0x800 0x2>; + + #address-cells = <2>; + #size-cells = <2>;Can this be much higher up?
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
Quoted 2 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +2
-0+ + mdp: mdp@ae01000 {
Quoted 7 lines
Node name needs some work. Drop label?
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 197
Quoted 3 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +3
-0+ compatible = "qcom,sc7180-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>;Wow size ends in 8!
These are register definition for 2 register ranges for mdp and vbif. Here, 2 cells are used to specify address and size cells.
Quoted 66 lines
Quoted 16 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +10
-0+ + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "rot", "lut","core",
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +3
-0+ "vsync"; + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc
DISP_CC_MDSS_VSYNC_CLK>,Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
Quoted 2 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +2
-0+ <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>;Is
ROT_CLKhere twice for some reason?Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml line 219
Quoted 7 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +7
-0+ assigned-clock-rates = <300000000>, + <19200000>, + <19200000>, + <19200000>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;Drop flags?
Quoted 35 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +9
-0+ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint =<
&dsi0_in>;Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +7
-0+ }; + }; + }; + }; + }; + }; +...Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +12
-0@@ -0,0 +1,216 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DPU dt properties. + +maintainers: + - Krishna Manikandan <[email protected]> + +description: |
Quoted 8 lines
Quoted 5 lines
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +1
-0+ Device tree bindings for MSM Mobile Display Subsytem(MDSS) thatencapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
+ bindings of MDSS and DPU are mentioned for SDM845 target.Is this substantially different from the previous binding? Can they just be merged together?
Sc7180 and sdm845 bindings have differences in some display properties.eg:clock
Quoted 475 lines
Quoted 419 lines
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +20
-0+ +properties: + compatible: + items: + - const: qcom,sdm845-mdss + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + description: | + Device clock names in the same order as mentioned in clocksproperty.
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +54
-0+ The required clocks are mentioned below. + items: + - const: iface + - const: bus + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + iommus: + maxItems: 2 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + assigned-clocks: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + +patternProperties: + "^mdp@[0-9a-f]+$": + type: object + description: Node containing the properties of DPU. + + properties: + compatible: + items: + - const: qcom,sdm845-dpu + reg: + maxItems: 2 + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + maxItems: 4 + + clock-names: + description: | + Device clock names, must be in same order as clocksproperty.
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +14
-0+ The following clocks are required. + items: + - const: iface + - const: bus + - const: core + - const: vsync + + interrupts: + maxItems: 1 + + ports: + type: object + description: | + Contains the list of output ports from DPU device. Theseports
+ connect to interfaces that are external to the DPU
hardware,
+ such as DSI, DP etc. Each output port contains an endpoint
that
+ describes how it is connected to an external interface.
These
+ are described by the standard properties documented in
filesDocumentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +4
-0+ mentioned below. + + Documentation/devicetree/bindings/graph.txt +
Documentation/devicetree/bindings/media/video-interfaces.txtDocumentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +77
-0+ + properties: + port@0: + type: object + description: DPU_INTF1 (DSI1) + port@1: + type: object + description: DPU_INTF2 (DSI2) + + assigned-clocks: + maxItems: 2 + + assigned-clock-rates: + maxItems: 2 + + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - clock-names + - interrupts + - interrupt-controller + - iommus + +additionalProperties: false + +examples: +- | + #include <dt-bindings/clock/qcom,dispcc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + + mdss: mdss@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + #address-cells = <2>; + #size-cells = <2>; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc
DISP_CC_MDSS_VSYNC_CLK>;Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +14
-0+ assigned-clock-rates = <300000000>, + <19200000>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint =<
&dsi0_in>;Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +7
-0+ }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint =<
&dsi1_in>;Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +7
-0+ }; + }; + }; + }; + }; + }; +...Documentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-5@@ -1,141 +0,0 @@ -Qualcomm Technologies, Inc. DPU KMS - -Description: - -Device tree bindings for MSM Mobile Display Subsytem(MDSS) thatencapsulates
Documentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-13-sub-blocks like DPU display controller, DSI and DP interfaces etc. -The DPU display controller is found in SDM845 SoC. - -MDSS: -Required properties: -- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss" -- reg: physical base address and length of contoller's registers. -- reg-names: register region names. The following region is required: - * "mdss" -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt -- clocks: list of clock specifiers for clocks needed by the device. -- clock-names: device clock names, must be in same order as clocksproperty.
Documentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-6- The following clocks are required: - * "iface" - * "bus" - * "core" -- interrupts: interrupt signal from MDSS. -- interrupt-controller: identifies the node as an interruptcontroller.
-- #interrupt-cells: specifies the number of cells needed to encode an interrupt
- source, should be 1.
-- iommus: phandle of iommu device node.
-- #address-cells: number of address cells for the MDSS children. Should be 1.
-- #size-cells: Should be 1.
-- ranges: parent bus address space is the same as the child bus address space.
-- interconnects : interconnect path specifier for MDSS according to
-Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
- 2 paths corresponding to 2 AXI ports.
-- interconnect-names : MDSS will have 2 port names to differentiate between theDocumentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-4- 2 interconnect paths defined with interconnect specifier. - -Optional properties: -- assigned-clocks: list of clock specifiers for clocks needing rateassignment
-- assigned-clock-rates: list of clock frequencies sorted in the same order asDocumentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-7- the assigned-clocks property. - -MDP: -Required properties: -- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu" -- reg: physical base address and length of controller's registers. -- reg-names : register region names. The following region isrequired:
Documentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-4- * "mdp" - * "vbif" -- clocks: list of clock specifiers for clocks needed by the device. -- clock-names: device clock names, must be in same order as clocksproperty.
Documentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-7- The following clocks are required. - * "bus" - * "iface" - * "core" - * "vsync" -- interrupts: interrupt line from DPU to MDSS. -- ports: contains the list of output ports from DPU device. Theseports connect
- to interfaces that are external to the DPU hardware, such as DSI, DP etc.Documentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-2- - Each output port contains an endpoint that describes how it isconnected to an
- external interface. These are described by the standard properties documentedDocumentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-9- here: - Documentation/devicetree/bindings/graph.txt - Documentation/devicetree/bindings/media/video-interfaces.txt - - Port 0 -> DPU_INTF1 (DSI1) - Port 1 -> DPU_INTF2 (DSI2) - -Optional properties: -- assigned-clocks: list of clock specifiers for clocks needing rateassignment
-- assigned-clock-rates: list of clock frequencies sorted in the same order asDocumentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-12- the assigned-clocks property. - -Example: - - mdss: mdss@ae00000 { - compatible = "qcom,sdm845-mdss"; - reg = <0xae00000 0x1000>; - reg-names = "mdss"; - - power-domains = <&clock_dispcc 0>; - - clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc
GCC_DISP_AXI_CLK>,Documentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-4- <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "core"; - - assigned-clocks = <&clock_dispcc
DISP_CC_MDSS_MDP_CLK>;Documentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-7- assigned-clock-rates = <300000000>; - - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - - interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos
SLAVE_EBI1>,
- <&rsc_hlosMASTER_MDP1&rsc_hlosSLAVE_EBI1>;Documentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-18- - interconnect-names = "mdp0-mem", "mdp1-mem"; - - iommus = <&apps_iommu 0>; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xae00000 0xb2008>; - - mdss_mdp: mdp@ae01000 { - compatible = "qcom,sdm845-dpu"; - reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, - <&clock_dispcc DISP_CC_MDSS_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, - <&clock_dispcc
DISP_CC_MDSS_VSYNC_CLK>;Documentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-3- clock-names = "iface", "bus", "core", "vsync"; - - assigned-clocks = <&clock_dispcc
DISP_CC_MDSS_MDP_CLK>,
- <&clock_dispccDISP_CC_MDSS_VSYNC_CLK>;
- assigned-clock-rates = <0 0 300000000
19200000>;Documentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-11- - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint =<
&dsi0_in>;Documentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-7- }; - }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint =<
&dsi1_in>;Documentation/devicetree/bindings/display/msm/dpu.txt deleted +0
-5- }; - }; - }; - }; - };(quoted diff) +0
-0
b/Documentation/devicetree/bindings/display/msm/dsi-common-controller.yamlDocumentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +4
-0@@ -0,0 +1,235 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id:http://devicetree.org/schemas/display/msm/dsi-common-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +18
-0+ +title: Description of Qualcomm Display DSI controller dt properties. + +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Common Device tree bindings for DSI controller. + +allOf: + - $ref: "../dsi-controller.yaml#" + +properties: + compatible: + items: + - const: qcom,mdss-dsi-ctrl + + vdd-supply:Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml line 33
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +10
-0+ description: Phandle to vdd regulator device node. + + vddio-supply: + description: Phandle to vdd-io regulator device node. + + vdda-supply: + description: Phandle to vdda regulator device node. + + phys: + description: Phandle to DSI PHY device node.Don't think we need descriptions on these.
Quoted 1 line
+ maxItems: 1
It's optional?
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml line 37
Quoted 3 lines
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +3
-0+ + phy-names: + description: Name of the corresponding PHY device.Doesn't seem like it's optional so just items: const?
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml line 44
Quoted 7 lines
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +7
-0+ maxItems: 1 + + syscon-sfpb: + description: A phandle to mmss_sfpb syscon node (only for DSIv2). + $ref: "/schemas/types.yaml#/definitions/phandle" + + # Optional Properties for dsi controllerWeird tab?
Quoted 12 lines
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +12
-0+ qcom,mdss-mdp-transfer-time-us: + description: | + Specifies the DSI transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + DSI link rate since anyways this would be the maximumDocumentation/devicetree/bindings/display/msm/dsi-common-controller.yaml line 66
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +10
-0+ transfer time that could be achieved. + If ping pong split is enabled, this time should not be higher + than two times the DSI link rate time. + This is an optional property. + default: 14000 + + qcom,dual-dsi-mode: + type: boolean + description: | + Boolean value indicating if the DSI controller is
Quoted 5 lines
"Boolean value" is redundant.
Quoted 1 line
+ driving a panel which needs 2 DSI links.
Shouldn't this be a property of the panel?
Currently we are defining this as part of dsi controller. We can work on the source file changes to define it as a panel property.
Quoted 760 lines
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml line 73
Quoted 7 lines
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +6
-0+ + qcom,master-dsi: + type: boolean + description: | + Boolean value indicating if the DSI controller is driving + the master link of the 2-DSI panel.Shouldn't this be a property of the panel?
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml line 79
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +6
-0+ + qcom,sync-dual-dsi: + type: boolean + description: | + Boolean value indicating if the DSI controller is driving a + 2-DSI panel whose 2 links need receive command simultaneously.Shouldn't this be a property of the panel?
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml line 91
Quoted 12 lines
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +12
-0+ + pinctrl-names: + description: The pin control state names. + items: + - const: default + - const: sleep + + pinctrl-0: + description: The default pinctrl state (active) + + pinctrl-1: + description: The sleep pinctrl state (suspend)These can be left out? Doesn't seem like they're non-standard.
Quoted 14 lines
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +5
-0+ + ports: + type: object + description: | + Contains DSI controller input and output ports as children,each
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +8
-0+ containing one endpoint subnode as defined in + Documentation/devicetree/bindings/graph.txt and + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + port@0: + type: object + description: |Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml line 114
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +10
-0+ Input endpoints of the controller. + + properties: + reg: + const: 0 + + endpoint: + type: object + properties: + remote-endpoint:Can this and the properties below go into some generic binding instead of here?
Quoted 28 lines
(quoted diff) +2
-0+ description: | + For port@0, set to phandle of the connectedpanel/bridge's
+ input endpoint. For port@1, set to the MDP
interface output.Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +6
-0+ See Documentation/devicetree/bindings/graph.txt for + device graph info. + + data-lanes: + description: | + This describes how the physical DSI data lanes aremapped
+ to the logical lanes on the given platform. The
value contained in
+ index n describes what physical lane is mapped to
the logical lane n
+ (DATAn, where n lies between 0 and 3). The clock
lane position is fixed
+ and can't be changed. Hence, they aren't a part of
the DT bindings. See
+Documentation/devicetree/bindings/media/video-interfaces.txtforDocumentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +6
-0+ more info on the data-lanes property. + + For example: + data-lanes = <3 0 1 2>; + + The above mapping describes that the logical dataQuoted 8 lines
lane DATA0 is mapped
+ to the physical data lane DATA3, logical DATA1 to
physical DATA0,
+ logic DATA2 to phys DATA1 and logic DATA3 to phys
DATA2. There are
+ only a limited number of physical to logical
mappings possible.
+ oneOf:That is a lot.
Quoted 110 lines
Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file +97
-0+ - items: + - const: 0 + - const: 1 + - const: 2 + - const: 3 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 0 + - items: + - const: 2 + - const: 3 + - const: 0 + - const: 1 + - items: + - const: 3 + - const: 0 + - const: 1 + - const: 2 + - items: + - const: 0 + - const: 3 + - const: 2 + - const: 1 + - items: + - const: 1 + - const: 0 + - const: 3 + - const: 2 + - items: + - const: 2 + - const: 1 + - const: 0 + - const: 3 + - items: + - const: 3 + - const: 2 + - const: 1 + - const: 0 + port@1: + type: object + description: | + Output endpoints of the controller. + properties: + reg: + const: 1 + + endpoint: + type: object + properties: + remote-endpoint: true + data-lanes: + oneOf: + - items: + - const: 0 + - const: 1 + - const: 2 + - const: 3 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 0 + - items: + - const: 2 + - const: 3 + - const: 0 + - const: 1 + - items: + - const: 3 + - const: 0 + - const: 1 + - const: 2 + - items: + - const: 0 + - const: 3 + - const: 2 + - const: 1 + - items: + - const: 1 + - const: 0 + - const: 3 + - const: 2 + - items: + - const: 2 + - const: 1 + - const: 0 + - const: 3 + - items: + - const: 3 + - const: 2 + - const: 1 + - const: 0 + +unevaluatedProperties: false +...(quoted diff) +0
-0
b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yamlDocumentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +4
-0@@ -0,0 +1,119 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id:http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#Review
Quoted 2 lines
(quoted diff) +2
-0+ +title: Description of Qualcomm Display DSI controller dt properties.Drop full stop?
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml line 16
Quoted 9 lines
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +9
-0+ +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Device tree bindings for DSI controller. + +allOf: + - $ref: dsi-common-controller.yaml#That's neat, but now makes this harder to read?
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +6
-0+ +properties: + compatible: + const: qcom,mdss-dsi-ctrl + + reg:Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml line 32
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +10
-0+ maxItems: 1 + + reg-names: + const: dsi_ctrl + + interrupts: + maxItems: 1 + + clocks: + maxItems: 6items:
- description:
- description:
- description:
- description:Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml line 41
Quoted 9 lines
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +9
-0+ + clock-names: + items: + - const: byte + - const: byte_intf + - const: pixel + - const: core + - const: iface + - const: busIndent seems wrong.
Quoted 192 lines
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +66
-0+ + phys: + maxItems: 1 + + phy-names: + const: dsi + + ports: true + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - phys + - phy-names + - ports + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,dispcc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + + mdss: mdss { + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint =<
&dpu_intf1_out>;Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +12
-0+ }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + }; +...Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml new file +53
-0@@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI 10nm PHY dt properties. + +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Common Device tree bindings for DSI 10nm PHY. + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-10nm + - const: qcom,dsi-phy-10nm-8998 + + reg-names: + items: + - const: dsi_phy + - const: dsi_phy_lane + - const: dsi_pll + + clock-cells: + description: | + The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). + const: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + description: | + The following clocks are required. + items: + - const: iface + - const: ref + + vdds-supply: + description: | + Phandle to vdds regulator device node. + + qcom,dsi-phy-regulator-ldo-mode: + type: boolean + description: | + Boolean value indicating if the LDO mode PHY regulator iswanted (optional).
Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml new file +11
-0+ +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - vdds-supply + +additionalProperties: true +...Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml new file +36
-0@@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI 14nm PHY dt properties. + +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Common Device tree bindings for DSI 14nm PHY. + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-14nm + - const: qcom,dsi-phy-14nm-660 + + reg-names: + items: + - const: dsi_phy + - const: dsi_phy_lane + - const: dsi_pll + + clock-cells: + description: | + The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). + const: 1 + + power-domains: + maxItems: 1 + + clocks:Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml line 46
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Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml new file +10
-0+ maxItems: 2 + + clock-names: + description: | + The following clocks are required. + items: + - const: iface + - const: ref + + qcom,dsi-phy-regulator-ldo-mode:Please remove this property.
Quoted 41 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml new file +3
-0+ type: boolean + description: | + Boolean value indicating if the LDO mode PHY regulator iswanted (optional).
Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml new file +15
-0+ + vcca-supply: + description: | + Phandle to vcca regulator device node. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - vcca-supply + +additionalProperties: true +...Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml new file +16
-0@@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI 20nm PHY dt properties. + +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Common Device tree bindings for DSI 20nm PHY. + +properties: + compatible:Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml line 26
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Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml new file +10
-0+ oneOf: + - const: qcom,dsi-phy-20nm + + reg-names: + items: + - const: dsi_pll + - const: dsi_phy + - const: dsi_phy_regulator + + clock-cells:Should be '#clock-cells'
Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml line 30
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Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml new file +4
-0+ description: | + The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). + const: 1i.e.
'#clock-cells':
const: 1Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml line 40
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Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml new file +10
-0+ + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + description: | + The following clocks are required.Please remove description.
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Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml new file +8
-0+ items: + - const: iface + - const: ref + + qcom,dsi-phy-regulator-ldo-mode: + type: boolean + description: | + Boolean value indicating if the LDO mode PHY regulator iswanted (optional).
Please remove this property.
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Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml new file +20
-0+ + vcca-supply: + description: | + Phandle to vcca regulator device node. + + vddio-supply: + description: | + Phandle to vdd-io regulator device node. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - vddio-supply + - vcca-supply + +additionalProperties: true +...Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml new file +50
-0@@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI 28nm PHY dt properties. + +maintainers: + - Krishna Manikandan <[email protected]> + +description: | + Common Device tree bindings for DSI 28nm PHY. + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-28nm-hpm + - const: qcom,dsi-phy-28nm-lp + - const: qcom,dsi-phy-28nm-8960 + + reg-names: + items: + - const: dsi_pll + - const: dsi_phy + - const: dsi_phy_regulator + + clock-cells: + description: | + The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). + const: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + description: | + The following clocks are required. + items: + - const: iface + - const: ref + + qcom,dsi-phy-regulator-ldo-mode: + type: boolean + description: | + Boolean value indicating if the LDO mode PHY regulator isQuoted 1 line
wanted (optional).
Please remove this property.
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
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Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml new file +4
-0+ + vddio-supply: + description: | + Phandle to vdd-io regulator device node.Don't think we need | here, i.e just
vddio-supply:
description: vddIO supply for dsi controller.Honestly it would be GREAT if this told us which PX_<N> pin on the SoC this is connected to so we don't have to dig through docs to figure out how the hardware block is connected to the power pins on the SoC. My understanding is the PX pins fan out to various hardware blocks inside the SoC, so 'vddio-supply' makes sense from the internal hardware block but at the edge of the SoC it is basically meaningless.
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Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml new file +10
-0+ +required: + - compatible + - reg + - reg-names + - clocks + - vddio-supply + +additionalProperties: true +...Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +10
-0@@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI PHY dt properties. + +maintainers: + - Krishna Manikandan <[email protected]>Documentation/devicetree/bindings/display/msm/dsi-phy.yaml line 20
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Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +10
-0+ +description: | + Device tree bindings for DSI PHY. + +allOf: + - $ref: dsi-phy-10nm.yaml# + +properties: + compatible: + const: qcom,dsi-phy-10nmThis should be merged with dsi-phy-10nm? Nothing else references the
dsi-phy-10nm.yamlbinding so I'm confused why this is split from it.Quoted 23 lines
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +23
-0+ + reg: + maxItems: 3 + + reg-names: + maxItems: 3 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: iface + - const: ref + + "#clock-cells": + const: 1 + + "#phy-cells": + const: 0 + +required: + - compatibleDocumentation/devicetree/bindings/display/msm/dsi-phy.yaml line 53
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Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +10
-0+ - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h>This include is not used.
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml line 55
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Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +2
-0+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>This include is not used.
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml line 60
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Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +5
-0+ #include <dt-bindings/clock/qcom,rpmh.h> + + mdss: mdss { + #address-cells = <2>; + #size-cells = <2>;Do we need this wrapper node? I guess it helps to know where to put this node but it's not enforced in the binding at all.
Documentation/devicetree/bindings/display/msm/dsi-phy.yaml line 62
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Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +2
-0+ + dsi0_phy: dsi-phy@ae94400 {Why not just 'phy@ae94400'?
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Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +11
-0+ compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; +
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Documentation/devicetree/bindings/display/msm/dsi-phy.yaml line 81
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Documentation/devicetree/bindings/display/msm/dsi-phy.yaml new file +8
-0+ vdds-supply = <&vdda_mipi_dsi0_pll>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + }; + }; +...
Regards,
Krishna