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arm: aspeed: zaius: Disable LPC reset for UART1

PATCH In review Xo Wang 3 participants 4 messages Feb 1, 2017 – Feb 3, 2017

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Arm (32-bit) Arm sub-architectures Arm/Aspeed machine support
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Xo Wang

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#0 lore raw

PATCH v3 1/1 arm: aspeed: zaius: Disable LPC reset for UART1

Currently, UART1 on Zaius BMC is unusable until brought out of reset by powering the host on. In that default reset state, ttyS0 can still be opened and UART1 silently drops bytes, which is not obviously expected behavior.

Clear the LPC block control bit that enables LPCRST# as a reset source for UART1, making UART1 immediately useful in that it won't discard bytes.

Signed-off-by Xo Wang <[email protected]>
---
 arch/arm/mach-aspeed/aspeed.c | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm/mach-aspeed/aspeed.c +8 -0
index 4bd3680d742d..b7022eaa7b5d 100644
@@ -185,6 +185,14 @@ static void __init do_zaius_setup(void)
 
 	/* Set SPI1 CE0 decoding window to 0x30000000 */
 	writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30));
+
+	/* Disable default behavior of UART1 being held in reset by LPCRST#.
+	 * By releasing UART1 from being controlled by LPC reset, it becomes
+	 * immediately available regardless of the host being up.
+	 * */
+	reg = readl(AST_IO(AST_BASE_LPC | 0x98));
+	/* Clear "Enable UART1 reset source from LPC" */
+	writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98));
 }
 
 static void __init do_witherspoon_setup(void)
Signature · 1 line
2.11.0.483.g087da7b7c-goog
maintainer
#1 lore raw
Quoted 10 lines · Xo Wang via openbmc

Currently, UART1 on Zaius BMC is unusable until brought out of reset by powering the host on. In that default reset state, ttyS0 can still be opened and UART1 silently drops bytes, which is not obviously expected behavior.

Clear the LPC block control bit that enables LPCRST# as a reset source for UART1, making UART1 immediately useful in that it won't discard bytes.

Signed-off-by Xo Wang <[email protected]>

Andrew, Rick, are you guys happy with this now? Can I get an ack or review tag?

Cheers,

Joel

Quoted 30 lines
---
 arch/arm/mach-aspeed/aspeed.c | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm/mach-aspeed/aspeed.c +8 -1
index 4bd3680d742d..b7022eaa7b5d 100644
@@ -185,6 +185,14 @@ static void __init do_zaius_setup(void)
 
        /* Set SPI1 CE0 decoding window to 0x30000000 */
        writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30));
+
+       /* Disable default behavior of UART1 being held in reset by LPCRST#.
+        * By releasing UART1 from being controlled by LPC reset, it becomes
+        * immediately available regardless of the host being up.
+        * */
+       reg = readl(AST_IO(AST_BASE_LPC | 0x98));
+       /* Clear "Enable UART1 reset source from LPC" */
+       writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98));
 }
 
 static void __init do_witherspoon_setup(void)
--

2.11.0.483.g087da7b7c-goog

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Reviewed-by on v3 1/1
#2 lore raw
In reply to Xo Wang
Quoted 26 lines · Xo Wang

Currently, UART1 on Zaius BMC is unusable until brought out of reset by powering the host on. In that default reset state, ttyS0 can still be opened and UART1 silently drops bytes, which is not obviously expected behavior.

Clear the LPC block control bit that enables LPCRST# as a reset source for UART1, making UART1 immediately useful in that it won't discard bytes.

Quoted 1 line
Signed-off-by Xo Wang <[email protected]>

---
 arch/arm/mach-aspeed/aspeed.c | 8 ++++++++

 1 file changed, 8 insertions(+)
arch/arm/mach-aspeed/aspeed.c +0 -0
index 4bd3680d742d..b7022eaa7b5d 100644
@@ -185,6 +185,14 @@ static void __init do_zaius_setup(void)

Quoted 2 lines

  /* Set SPI1 CE0 decoding window to 0x30000000 */ writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30));

+

Quoted 3 lines
arch/arm/mach-aspeed/aspeed.c +3 -0
+	/* Disable default behavior of UART1 being held in reset by LPCRST#.
+	 * By releasing UART1 from being controlled by LPC reset, it becomes
+	 * immediately available regardless of the host being up.

arch/arm/mach-aspeed/aspeed.c static void __init do_zaius_setup(void) · line 192

Quoted 1 line
arch/arm/mach-aspeed/aspeed.c +1 -0
+	 * */

Joel: Want to clean up the formatting here when you apply it? If so:

Reviewed-by Andrew Jeffery <[email protected]>
Quoted 6 lines
arch/arm/mach-aspeed/aspeed.c +1 -0
+	reg = readl(AST_IO(AST_BASE_LPC | 0x98));

arch/arm/mach-aspeed/aspeed.c static void __init do_zaius_setup(void) · line 195

Quoted 2 lines
arch/arm/mach-aspeed/aspeed.c +2 -0
+	/* Clear "Enable UART1 reset source from LPC" */
+	writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98));

 }

 static void __init do_witherspoon_setup(void)

maintainer
#3 lore raw
Quoted 24 lines · Andrew Jeffery
Quoted 23 lines · Xo Wang

Currently, UART1 on Zaius BMC is unusable until brought out of reset by powering the host on. In that default reset state, ttyS0 can still be opened and UART1 silently drops bytes, which is not obviously expected behavior.

Clear the LPC block control bit that enables LPCRST# as a reset source for UART1, making UART1 immediately useful in that it won't discard bytes.

Quoted 1 line
Signed-off-by Xo Wang <[email protected]>
---
 arch/arm/mach-aspeed/aspeed.c | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm/mach-aspeed/aspeed.c +0 -0
index 4bd3680d742d..b7022eaa7b5d 100644
@@ -185,6 +185,14 @@ static void __init do_zaius_setup(void)
Quoted 2 lines
    /* Set SPI1 CE0 decoding window to 0x30000000 */
    writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30));

+

Quoted 8 lines
Quoted 4 lines

arch/arm/mach-aspeed/aspeed.c static void __init do_zaius_setup(void) · line 191

Quoted 3 lines
arch/arm/mach-aspeed/aspeed.c +3 -0
+   /* Disable default behavior of UART1 being held in reset by LPCRST#.
+    * By releasing UART1 from being controlled by LPC reset, it becomes
+    * immediately available regardless of the host being up.

+ * */

Joel: Want to clean up the formatting here when you apply it? If so:

Reviewed-by Andrew Jeffery <[email protected]>

Thanks. I fixed the formatting of the comment when I applied. This is in dev-4.7 now.

Cheers,

Joel