arm: dts: aspeed: Add missing clock sources for barreleye

PATCH In review Eddie James 3 participants 4 messages May 26, 2017 – May 31, 2017

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Eddie James

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2017-05-26 16:10 UTC #0 lore raw

PATCH v4 1/1 arm: dts: aspeed: Add missing clock sources for barreleye

From: "Edward A. James" <[email protected]>

Reorganize flash controllers into the ast2400 config and edit all the ast2400 machine configs. Barreleye wasn't booting with the new aspeed-smc driver.

Signed-off-by Edward A. James <[email protected]>

---
 arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts | 44 ++++++++-------------
 arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts | 37 ++++++------------
 arch/arm/boot/dts/aspeed-bmc-opp-garrison.dts  | 47 +++++++---------------
 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts  | 54 +++++++++-----------------
 arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts   | 38 ++++++------------
 arch/arm/boot/dts/aspeed-g4.dtsi               | 34 ++++++++++++++++
 6 files changed, 106 insertions(+), 148 deletions(-)

arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +16 ~~-28~~

index be1f2d1..6c4221c 100644
@@ -31,34 +31,6 @@
 		};
 	};
 
-	ahb {
-		bmc_pnor: fmc@1e620000 {
-			reg = < 0x1e620000 0x94
-				0x20000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-#include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
-
-		host_pnor: spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-spi";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-			};
-		};
-	};
-
 	leds {
 		compatible = "gpio-leds";

@@ -76,6 +48,22 @@
 	};
 };
 
+&bmc_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+#include "aspeed-bmc-opp-flash-layout.dtsi"
+	};
+};
+
+&host_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		label = "pnor";
+	};
+};
+
 &pinctrl {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default

arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts +12 ~~-25~~

index fe63621..dffe1cd 100644
@@ -50,34 +50,21 @@
 			gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
 		};
 	};
+};
 
-	ahb {
-		fmc@1e620000 {
-			reg = < 0x1e620000 0x94
-				0x20000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
+&bmc_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
 #include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
+	};
+};
 
-		spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-spi";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-			};
-		};
+&host_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		label = "pnor";
 	};
 };

arch/arm/boot/dts/aspeed-bmc-opp-garrison.dts +14 ~~-33~~

56 lines not on this page · raw message

arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +18 ~~-36~~

66 lines not on this page · raw message

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +12 ~~-26~~

index 7132460..e55685d 100644
@@ -30,35 +30,21 @@
 			reg = <0x47800000 0x00800000>; /* 8MB */
 		};
 	};
+};
 
-	ahb {
-		bmc_pnor: fmc@1e620000 {
-			reg = < 0x1e620000 0x94
-				0x20000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-			aspeed,fmc-has-dma;
-			interrupts = <19>;
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
+&bmc_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
 #include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
+	};
+};
 
-		host_pnor: spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x01000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-smc";
-			flash {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-			};
-		};
+&host_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		label = "pnor";
 	};
 };

arch/arm/boot/dts/aspeed-g4.dtsi +34 -0

index d8827d5..9fb7889 100644
@@ -44,6 +44,40 @@
 		#size-cells = <1>;
 		ranges;
 
+		bmc_pnor: fmc@1e620000 {
+			reg = < 0x1e620000 0x94
+				0x20000000 0x02000000 >;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "aspeed,ast2400-fmc";
+			status = "disabled";
+			aspeed,fmc-has-dma;
+			interrupts = <19>;
+			clocks = <&clk_ahb>;
+			clock-names = "ahb";
+			flash@0 {
+				reg = < 0 >;
+				compatible = "jedec,spi-nor" ;
+				status = "disabled";
+			};
+		};
+
+		host_pnor: spi@1e630000 {
+			reg = < 0x1e630000 0x18
+				0x30000000 0x02000000 >;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "aspeed,ast2400-spi";
+			status = "disabled";
+			clocks = <&clk_ahb>;
+			clock-names = "ahb";
+			flash@0 {
+				reg = < 0 >;
+				compatible = "jedec,spi-nor" ;
+				status = "disabled";
+			};
+		};
+
 		vic: interrupt-controller@1e6c0080 {
 			compatible = "aspeed,ast2400-vic";
 			interrupt-controller;

Signature · 1 line

1.8.3.1

Cédric Le Goater

2017-05-29 12:16 UTC #1 lore raw

Hello Edward,

Quoted 5 lines · Eddie James

From: "Edward A. James" <[email protected]>
Reorganize flash controllers into the ast2400 config and edit all the ast2400 machine configs. Barreleye wasn't booting with the new aspeed-smc driver.

There are a couple of "m25p,fast-read" properties missing below. Is that on purpose ?

Thanks,

Quoted 50 lines

Signed-off-by Edward A. James <[email protected]>

---
 arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts | 44 ++++++++-------------
 arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts | 37 ++++++------------
 arch/arm/boot/dts/aspeed-bmc-opp-garrison.dts  | 47 +++++++---------------
 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts  | 54 +++++++++-----------------
 arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts   | 38 ++++++------------
 arch/arm/boot/dts/aspeed-g4.dtsi               | 34 ++++++++++++++++
 6 files changed, 106 insertions(+), 148 deletions(-)

arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +0 ~~-28~~

index be1f2d1..6c4221c 100644
@@ -31,34 +31,6 @@
 		};
 	};
 
-	ahb {
-		bmc_pnor: fmc@1e620000 {
-			reg = < 0x1e620000 0x94
-				0x20000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-#include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
-
-		host_pnor: spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-spi";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-			};
-		};
-	};
-
 	leds {
 		compatible = "gpio-leds";

arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts line 52

Quoted 5 lines

arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +2 -0
@@ -76,6 +48,22 @@
 	};
 };
 
+&bmc_pnor {
+	status = "okay";

no m25p,fast-read; ?

arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts line 60

Quoted 8 lines

arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +8 -0

+	flash@0 {
+		status = "okay";
+#include "aspeed-bmc-opp-flash-layout.dtsi"
+	};
+};
+
+&host_pnor {
+	status = "okay";

no m25p,fast-read; ?

Quoted 22 lines

arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +6 -0

+	flash@0 {
+		status = "okay";
+		label = "pnor";
+	};
+};
+
 &pinctrl {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default

arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts +1 -3

index fe63621..dffe1cd 100644
@@ -50,34 +50,21 @@
 			gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
 		};
 	};
+};
 
-	ahb {
-		fmc@1e620000 {
-			reg = < 0x1e620000 0x94

arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts line 56

Quoted 10 lines

arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts +2 -8

-				0x20000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
+&bmc_pnor {
+	status = "okay";

no m25p,fast-read; ?

Quoted 12 lines

arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts +4 -6

+	flash@0 {
+		status = "okay";
 #include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
+	};
+};
 
-		spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x02000000 >;
-			#address-cells = <1>;

arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts line 64

Quoted 10 lines

arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts +2 -8

-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-spi";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-			};
-		};
+&host_pnor {
+	status = "okay";

no m25p,fast-read; ?

Quoted 153 lines

arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts +3 -0

+	flash@0 {
+		status = "okay";
+		label = "pnor";
 	};
 };

arch/arm/boot/dts/aspeed-bmc-opp-garrison.dts +14 ~~-33~~

index 121612a..c6c5e14 100644
@@ -30,42 +30,23 @@
 			reg = <0x5f000000 0x01000000>; /* 16MB */
 		};
 	};
+};
 
-	ahb {
-
-		bmc_pnor: fmc@1e620000 {
-			reg = < 0x1e620000 0x94
-				0x20000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-			aspeed,fmc-has-dma;
-			interrupts = <19>;
-			clocks = <&clk_ahb>;
-			clock-names = "ahb";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				m25p,fast-read;
+&bmc_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
 #include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
+	};
+};
 
-		host_pnor: spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-spi";
-			clocks = <&clk_ahb>;
-			clock-names = "ahb";
-			flash {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-				m25p,fast-read;
-			};
-		};
+&host_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		label = "pnor";
+		m25p,fast-read;
 	};
 };

arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +18 ~~-36~~

index b4faa1d..f343aa4 100644
@@ -47,42 +47,6 @@
                 };
         };
 
-	ahb {
-		bmc_pnor: fmc@1e620000 {
-			reg = < 0x1e620000 0x94
-				0x20000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-			aspeed,fmc-has-dma;
-			interrupts = <19>;
-			clocks = <&clk_ahb>;
-			clock-names = "ahb";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				m25p,fast-read;
-#include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
-
-		host_pnor: spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-spi";
-			clocks = <&clk_ahb>;
-			clock-names = "ahb";
-			flash {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-				m25p,fast-read;
-			};
-		};
-	};
-
 	gpio-fsi {
 		compatible = "fsi-master-gpio", "fsi-master";

@@ -94,6 +58,24 @@
 	};
 };
 
+&bmc_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+#include "aspeed-bmc-opp-flash-layout.dtsi"
+	};
+};
+
+&host_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		label = "pnor";
+		m25p,fast-read;
+	};
+};
+
 &pinctrl {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +1 -4

index 7132460..e55685d 100644
@@ -30,35 +30,21 @@
 			reg = <0x47800000 0x00800000>; /* 8MB */
 		};
 	};
+};
 
-	ahb {
-		bmc_pnor: fmc@1e620000 {
-			reg = < 0x1e620000 0x94
-				0x20000000 0x02000000 >;

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts line 36

Quoted 10 lines

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +2 -8

-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-			aspeed,fmc-has-dma;
-			interrupts = <19>;
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
+&bmc_pnor {
+	status = "okay";

no m25p,fast-read; ?

Quoted 12 lines

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +4 -6

+	flash@0 {
+		status = "okay";
 #include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
+	};
+};
 
-		host_pnor: spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x01000000 >;
-			#address-cells = <1>;

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts line 44

Quoted 10 lines

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +2 -8

-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-smc";
-			flash {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-			};
-		};
+&host_pnor {
+	status = "okay";

no m25p,fast-read; ?

Quoted 52 lines

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +3 -0

+	flash@0 {
+		status = "okay";
+		label = "pnor";
 	};
 };

arch/arm/boot/dts/aspeed-g4.dtsi +34 -0

index d8827d5..9fb7889 100644
@@ -44,6 +44,40 @@
 		#size-cells = <1>;
 		ranges;
 
+		bmc_pnor: fmc@1e620000 {
+			reg = < 0x1e620000 0x94
+				0x20000000 0x02000000 >;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "aspeed,ast2400-fmc";
+			status = "disabled";
+			aspeed,fmc-has-dma;
+			interrupts = <19>;
+			clocks = <&clk_ahb>;
+			clock-names = "ahb";
+			flash@0 {
+				reg = < 0 >;
+				compatible = "jedec,spi-nor" ;
+				status = "disabled";
+			};
+		};
+
+		host_pnor: spi@1e630000 {
+			reg = < 0x1e630000 0x18
+				0x30000000 0x02000000 >;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "aspeed,ast2400-spi";
+			status = "disabled";
+			clocks = <&clk_ahb>;
+			clock-names = "ahb";
+			flash@0 {
+				reg = < 0 >;
+				compatible = "jedec,spi-nor" ;
+				status = "disabled";
+			};
+		};
+
 		vic: interrupt-controller@1e6c0080 {
 			compatible = "aspeed,ast2400-vic";
 			interrupt-controller;

Eddie James

author

2017-05-30 13:35 UTC #2 lore raw

Quoted 10 lines · Cédric Le Goater

Hello Edward,
Quoted 5 lines · Eddie James
From: "Edward A. James" <[email protected]>
Reorganize flash controllers into the ast2400 config and edit all the ast2400 machine configs. Barreleye wasn't booting with the new aspeed-smc driver.
There are a couple of "m25p,fast-read" properties missing below. Is that on purpose ?

Yes, I copied the properties (or lack thereof) exactly from the existing flash entries for each individual system. I'm not sure if it was the original intention to not have those properties...

Thanks,
Eddie

Quoted 377 lines

Thanks,

Quoted 50 lines

Signed-off-by Edward A. James <[email protected]>

---
  arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts | 44 ++++++++-------------
  arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts | 37 ++++++------------
  arch/arm/boot/dts/aspeed-bmc-opp-garrison.dts  | 47 +++++++---------------
  arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts  | 54 +++++++++-----------------
  arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts   | 38 ++++++------------
  arch/arm/boot/dts/aspeed-g4.dtsi               | 34 ++++++++++++++++
  6 files changed, 106 insertions(+), 148 deletions(-)

arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +0 ~~-28~~

index be1f2d1..6c4221c 100644
@@ -31,34 +31,6 @@
  		};
  	};
 
-	ahb {
-		bmc_pnor: fmc@1e620000 {
-			reg = < 0x1e620000 0x94
-				0x20000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-#include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
-
-		host_pnor: spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-spi";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-			};
-		};
-	};
-
  	leds {
  		compatible = "gpio-leds";

arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts line 52

Quoted 5 lines

arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +2 -0
@@ -76,6 +48,22 @@
  	};
  };
 
+&bmc_pnor {
+	status = "okay";

no m25p,fast-read; ?

arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts line 60

Quoted 8 lines

arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +8 -0

+	flash@0 {
+		status = "okay";
+#include "aspeed-bmc-opp-flash-layout.dtsi"
+	};
+};
+
+&host_pnor {
+	status = "okay";

no m25p,fast-read; ?

Quoted 22 lines

arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +6 -0

+	flash@0 {
+		status = "okay";
+		label = "pnor";
+	};
+};
+
  &pinctrl {
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default

arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts +1 -3

index fe63621..dffe1cd 100644
@@ -50,34 +50,21 @@
  			gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
  		};
  	};
+};
 
-	ahb {
-		fmc@1e620000 {
-			reg = < 0x1e620000 0x94

arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts line 56

Quoted 10 lines

arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts +2 -8

-				0x20000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
+&bmc_pnor {
+	status = "okay";

no m25p,fast-read; ?

Quoted 12 lines

arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts +4 -6

+	flash@0 {
+		status = "okay";
  #include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
+	};
+};
 
-		spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x02000000 >;
-			#address-cells = <1>;

arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts line 64

Quoted 10 lines

arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts +2 -8

-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-spi";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-			};
-		};
+&host_pnor {
+	status = "okay";

no m25p,fast-read; ?

Quoted 153 lines

arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts +3 -0

+	flash@0 {
+		status = "okay";
+		label = "pnor";
  	};
  };

arch/arm/boot/dts/aspeed-bmc-opp-garrison.dts +14 ~~-33~~

index 121612a..c6c5e14 100644
@@ -30,42 +30,23 @@
  			reg = <0x5f000000 0x01000000>; /* 16MB */
  		};
  	};
+};
 
-	ahb {
-
-		bmc_pnor: fmc@1e620000 {
-			reg = < 0x1e620000 0x94
-				0x20000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-			aspeed,fmc-has-dma;
-			interrupts = <19>;
-			clocks = <&clk_ahb>;
-			clock-names = "ahb";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				m25p,fast-read;
+&bmc_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
  #include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
+	};
+};
 
-		host_pnor: spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-spi";
-			clocks = <&clk_ahb>;
-			clock-names = "ahb";
-			flash {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-				m25p,fast-read;
-			};
-		};
+&host_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		label = "pnor";
+		m25p,fast-read;
  	};
  };

arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +18 ~~-36~~

index b4faa1d..f343aa4 100644
@@ -47,42 +47,6 @@
                  };
          };
 
-	ahb {
-		bmc_pnor: fmc@1e620000 {
-			reg = < 0x1e620000 0x94
-				0x20000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-			aspeed,fmc-has-dma;
-			interrupts = <19>;
-			clocks = <&clk_ahb>;
-			clock-names = "ahb";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				m25p,fast-read;
-#include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
-
-		host_pnor: spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-spi";
-			clocks = <&clk_ahb>;
-			clock-names = "ahb";
-			flash {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-				m25p,fast-read;
-			};
-		};
-	};
-
  	gpio-fsi {
  		compatible = "fsi-master-gpio", "fsi-master";

@@ -94,6 +58,24 @@
  	};
  };
 
+&bmc_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+#include "aspeed-bmc-opp-flash-layout.dtsi"
+	};
+};
+
+&host_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		label = "pnor";
+		m25p,fast-read;
+	};
+};
+
  &pinctrl {
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +1 -4

index 7132460..e55685d 100644
@@ -30,35 +30,21 @@
  			reg = <0x47800000 0x00800000>; /* 8MB */
  		};
  	};
+};
 
-	ahb {
-		bmc_pnor: fmc@1e620000 {
-			reg = < 0x1e620000 0x94
-				0x20000000 0x02000000 >;

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts line 36

Quoted 10 lines

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +2 -8

-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-			aspeed,fmc-has-dma;
-			interrupts = <19>;
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
+&bmc_pnor {
+	status = "okay";

no m25p,fast-read; ?

Quoted 12 lines

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +4 -6

+	flash@0 {
+		status = "okay";
  #include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
+	};
+};
 
-		host_pnor: spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x01000000 >;
-			#address-cells = <1>;

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts line 44

Quoted 10 lines

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +2 -8

-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-smc";
-			flash {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-			};
-		};
+&host_pnor {
+	status = "okay";

no m25p,fast-read; ?

Quoted 52 lines

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +3 -0

+	flash@0 {
+		status = "okay";
+		label = "pnor";
  	};
  };

arch/arm/boot/dts/aspeed-g4.dtsi +34 -0

index d8827d5..9fb7889 100644
@@ -44,6 +44,40 @@
  		#size-cells = <1>;
  		ranges;
 
+		bmc_pnor: fmc@1e620000 {
+			reg = < 0x1e620000 0x94
+				0x20000000 0x02000000 >;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "aspeed,ast2400-fmc";
+			status = "disabled";
+			aspeed,fmc-has-dma;
+			interrupts = <19>;
+			clocks = <&clk_ahb>;
+			clock-names = "ahb";
+			flash@0 {
+				reg = < 0 >;
+				compatible = "jedec,spi-nor" ;
+				status = "disabled";
+			};
+		};
+
+		host_pnor: spi@1e630000 {
+			reg = < 0x1e630000 0x18
+				0x30000000 0x02000000 >;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "aspeed,ast2400-spi";
+			status = "disabled";
+			clocks = <&clk_ahb>;
+			clock-names = "ahb";
+			flash@0 {
+				reg = < 0 >;
+				compatible = "jedec,spi-nor" ;
+				status = "disabled";
+			};
+		};
+
  		vic: interrupt-controller@1e6c0080 {
  			compatible = "aspeed,ast2400-vic";
  			interrupt-controller;

Joel Stanley

maintainer

2017-05-31 12:48 UTC #3 lore raw

Quoted 13 lines · Eddie James

Quoted 11 lines · Cédric Le Goater
Hello Edward,
Quoted 6 lines · Eddie James
From: "Edward A. James" <[email protected]>
Reorganize flash controllers into the ast2400 config and edit all the ast2400 machine configs. Barreleye wasn't booting with the new aspeed-smc driver.

Quoted 7 lines

Quoted 2 lines
There are a couple of "m25p,fast-read" properties missing below. Is that on purpose ?
Yes, I copied the properties (or lack thereof) exactly from the existing flash entries for each individual system. I'm not sure if it was the original intention to not have those properties...

Can you please re-spin with the properties added so Cedric can give it one last check over before I merge it?

Cheers,

Joel