arm: dts: aspeed: Add missing clock sources for barreleye
Subsystems (2)
PATCH v2 1/1 arm: dts: aspeed: Add missing clock sources for barreleye
From: "Edward A. James" <[email protected]>
Reorganize flash controllers into the ast2400 config. Barreleye wasn't booting with the new aspeed-smc driver.
Signed-off-by Edward A. James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts | 44 ++++++++-------------- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 52 ++++++++------------------ arch/arm/boot/dts/aspeed-g4.dtsi | 34 +++++++++++++++++ 3 files changed, 66 insertions(+), 64 deletions(-)
arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +16 -28
@@ -31,34 +31,6 @@ }; }; - ahb { - bmc_pnor: fmc@1e620000 { - reg = < 0x1e620000 0x94 - 0x20000000 0x02000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2400-fmc"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor" ; -#include "aspeed-bmc-opp-flash-layout.dtsi" - }; - }; - - host_pnor: spi@1e630000 { - reg = < 0x1e630000 0x18 - 0x30000000 0x02000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2400-spi"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor" ; - label = "pnor"; - }; - }; - }; - leds { compatible = "gpio-leds";
@@ -76,6 +48,22 @@ }; }; +&bmc_pnor { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; +#include "aspeed-bmc-opp-flash-layout.dtsi" + }; +}; + +&host_pnor { + flash@0 { + status = "okay"; + m25p,fast-read; + }; +}; + &pinctrl { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +16 -36
64 lines not on this page · raw message
arch/arm/boot/dts/aspeed-g4.dtsi +34 -0
@@ -44,6 +44,40 @@ #size-cells = <1>; ranges; + bmc_pnor: fmc@1e620000 { + reg = < 0x1e620000 0x94 + 0x20000000 0x02000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2400-fmc"; + status = "disabled"; + aspeed,fmc-has-dma; + interrupts = <19>; + clocks = <&clk_ahb>; + clock-names = "ahb"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor" ; + status = "disabled"; + }; + }; + + host_pnor: spi@1e630000 { + reg = < 0x1e630000 0x18 + 0x30000000 0x02000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2400-spi"; + status = "disabled"; + clocks = <&clk_ahb>; + clock-names = "ahb"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor" ; + status = "disabled"; + }; + }; + vic: interrupt-controller@1e6c0080 { compatible = "aspeed,ast2400-vic"; interrupt-controller;
Signature · 1 line
1.8.3.1
Joel Stanley
maintainerQuoted 4 lines · Eddie James
From: "Edward A. James" <[email protected]>
Reorganize flash controllers into the ast2400 config. Barreleye wasn't booting with the new aspeed-smc driver.
Your commit message mentions Barreleye, but you're also updating Palmetto.
Can you please update all of the ast2400 platforms?
Also cc Cedric on your next version so he can check that we're doing the correct thing.
Quoted 188 lines
Signed-off-by Edward A. James <[email protected]>--- arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts | 44 ++++++++-------------- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 52 ++++++++------------------ arch/arm/boot/dts/aspeed-g4.dtsi | 34 +++++++++++++++++ 3 files changed, 66 insertions(+), 64 deletions(-)arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +16
-28@@ -31,34 +31,6 @@ }; }; - ahb { - bmc_pnor: fmc@1e620000 { - reg = < 0x1e620000 0x94 - 0x20000000 0x02000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2400-fmc"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor" ; -#include "aspeed-bmc-opp-flash-layout.dtsi" - }; - }; - - host_pnor: spi@1e630000 { - reg = < 0x1e630000 0x18 - 0x30000000 0x02000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2400-spi"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor" ; - label = "pnor"; - }; - }; - }; - leds { compatible = "gpio-leds";@@ -76,6 +48,22 @@ }; }; +&bmc_pnor { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; +#include "aspeed-bmc-opp-flash-layout.dtsi" + }; +}; + +&host_pnor { + flash@0 { + status = "okay"; + m25p,fast-read; + }; +}; + &pinctrl { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_defaultarch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +16
-36@@ -47,42 +47,6 @@ }; }; - ahb { - bmc_pnor: fmc@1e620000 { - reg = < 0x1e620000 0x94 - 0x20000000 0x02000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2400-fmc"; - aspeed,fmc-has-dma; - interrupts = <19>; - clocks = <&clk_ahb>; - clock-names = "ahb"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor" ; - m25p,fast-read; -#include "aspeed-bmc-opp-flash-layout.dtsi" - }; - }; - - host_pnor: spi@1e630000 { - reg = < 0x1e630000 0x18 - 0x30000000 0x02000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2400-spi"; - clocks = <&clk_ahb>; - clock-names = "ahb"; - flash { - reg = < 0 >; - compatible = "jedec,spi-nor" ; - label = "pnor"; - m25p,fast-read; - }; - }; - }; - gpio-fsi { compatible = "fsi-master-gpio", "fsi-master";@@ -94,6 +58,22 @@ }; }; +&bmc_pnor { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; +#include "aspeed-bmc-opp-flash-layout.dtsi" + }; +}; + +&host_pnor { + flash@0 { + status = "okay"; + m25p,fast-read; + }; +}; + &pinctrl { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_defaultarch/arm/boot/dts/aspeed-g4.dtsi +34
-1@@ -44,6 +44,40 @@ #size-cells = <1>; ranges; + bmc_pnor: fmc@1e620000 { + reg = < 0x1e620000 0x94 + 0x20000000 0x02000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2400-fmc"; + status = "disabled"; + aspeed,fmc-has-dma; + interrupts = <19>; + clocks = <&clk_ahb>; + clock-names = "ahb"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor" ; + status = "disabled"; + }; + }; + + host_pnor: spi@1e630000 { + reg = < 0x1e630000 0x18 + 0x30000000 0x02000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2400-spi"; + status = "disabled"; + clocks = <&clk_ahb>; + clock-names = "ahb"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor" ; + status = "disabled"; + }; + }; + vic: interrupt-controller@1e6c0080 { compatible = "aspeed,ast2400-vic"; interrupt-controller; --1.8.3.1
Quoted 6 lines · Joel Stanley
Quoted 4 lines · Eddie James
From: "Edward A. James" <[email protected]>
Reorganize flash controllers into the ast2400 config. Barreleye wasn't booting with the new aspeed-smc driver.
Quoted 6 lines
Your commit message mentions Barreleye, but you're also updating Palmetto.
Can you please update all of the ast2400 platforms?
Also cc Cedric on your next version so he can check that we're doing the correct thing.
Joel,
I would also like to add CONFIG_VMSPLIT_2G on the G4 to define correctly the SMC controller flash mapping window on the AHB Bus. It is limited to 32MB currently
Do you think we can take these ?
http://patchwork.ozlabs.org/patch/752285/ http://patchwork.ozlabs.org/patch/752287/
C.
Quoted 187 lines
Quoted 187 lines
Signed-off-by Edward A. James <[email protected]>--- arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts | 44 ++++++++-------------- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 52 ++++++++------------------ arch/arm/boot/dts/aspeed-g4.dtsi | 34 +++++++++++++++++ 3 files changed, 66 insertions(+), 64 deletions(-)arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +16
-28@@ -31,34 +31,6 @@ }; }; - ahb { - bmc_pnor: fmc@1e620000 { - reg = < 0x1e620000 0x94 - 0x20000000 0x02000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2400-fmc"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor" ; -#include "aspeed-bmc-opp-flash-layout.dtsi" - }; - }; - - host_pnor: spi@1e630000 { - reg = < 0x1e630000 0x18 - 0x30000000 0x02000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2400-spi"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor" ; - label = "pnor"; - }; - }; - }; - leds { compatible = "gpio-leds";@@ -76,6 +48,22 @@ }; }; +&bmc_pnor { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; +#include "aspeed-bmc-opp-flash-layout.dtsi" + }; +}; + +&host_pnor { + flash@0 { + status = "okay"; + m25p,fast-read; + }; +}; + &pinctrl { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_defaultarch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +16
-36@@ -47,42 +47,6 @@ }; }; - ahb { - bmc_pnor: fmc@1e620000 { - reg = < 0x1e620000 0x94 - 0x20000000 0x02000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2400-fmc"; - aspeed,fmc-has-dma; - interrupts = <19>; - clocks = <&clk_ahb>; - clock-names = "ahb"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor" ; - m25p,fast-read; -#include "aspeed-bmc-opp-flash-layout.dtsi" - }; - }; - - host_pnor: spi@1e630000 { - reg = < 0x1e630000 0x18 - 0x30000000 0x02000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2400-spi"; - clocks = <&clk_ahb>; - clock-names = "ahb"; - flash { - reg = < 0 >; - compatible = "jedec,spi-nor" ; - label = "pnor"; - m25p,fast-read; - }; - }; - }; - gpio-fsi { compatible = "fsi-master-gpio", "fsi-master";@@ -94,6 +58,22 @@ }; }; +&bmc_pnor { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; +#include "aspeed-bmc-opp-flash-layout.dtsi" + }; +}; + +&host_pnor { + flash@0 { + status = "okay"; + m25p,fast-read; + }; +}; + &pinctrl { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_defaultarch/arm/boot/dts/aspeed-g4.dtsi +34
-1@@ -44,6 +44,40 @@ #size-cells = <1>; ranges; + bmc_pnor: fmc@1e620000 { + reg = < 0x1e620000 0x94 + 0x20000000 0x02000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2400-fmc"; + status = "disabled"; + aspeed,fmc-has-dma; + interrupts = <19>; + clocks = <&clk_ahb>; + clock-names = "ahb"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor" ; + status = "disabled"; + }; + }; + + host_pnor: spi@1e630000 { + reg = < 0x1e630000 0x18 + 0x30000000 0x02000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2400-spi"; + status = "disabled"; + clocks = <&clk_ahb>; + clock-names = "ahb"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor" ; + status = "disabled"; + }; + }; + vic: interrupt-controller@1e6c0080 { compatible = "aspeed,ast2400-vic"; interrupt-controller; --1.8.3.1
Joel Stanley
maintainerQuoted 11 lines · Cédric Le Goater
Quoted 10 lines · Joel Stanley
Quoted 4 lines · Eddie James
From: "Edward A. James" <[email protected]>
Reorganize flash controllers into the ast2400 config. Barreleye wasn't booting with the new aspeed-smc driver.
Your commit message mentions Barreleye, but you're also updating Palmetto.
Can you please update all of the ast2400 platforms?
Quoted 8 lines
Quoted 2 lines
Also cc Cedric on your next version so he can check that we're doing the correct thing.
Joel,
I would also like to add
CONFIG_VMSPLIT_2Gon the G4 to define correctly the SMC controller flash mapping window on the AHB Bus. It is limited to 32MB currently
Yes, we should do that, I agree.
Quoted 4 lines
Do you think we can take these ?
http://patchwork.ozlabs.org/patch/752285/
"ARM: dts: aspeed-g4: fix AHB window size of the SMC controllers"
This one did not apply, as the device tree we have in dev-4.10 is ancient compared to upstream. I think Eddie's series that converts the machines over to match the ast2500 should help.
I will apply it once I have applied Eddie's v5 (as v4 needs some fixes for missing fast-read properties).
Quoted 1 line
http://patchwork.ozlabs.org/patch/752287/
I applied this one.
Apologies for not applying them earlier. I had assumed they were intended for the upstream tree. I have applied both of them to my staging tree for upstream as well.
Cheers,
Joel