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arm: dts: aspeed: Add missing clock sources for barreleye

PATCH Superseded Eddie James 1 participant 1 message May 26, 2017

Subsystems (2)
Device tree bindings Arm/Aspeed machine support

v3 of 4 Superseded Latest is v4 →

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Eddie James

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PATCH v3 1/1 arm: dts: aspeed: Add missing clock sources for barreleye

From: "Edward A. James" <[email protected]>

Reorganize flash controllers into the ast2400 config and edit all the ast2400 machine configs. Barreleye wasn't booting with the new aspeed-smc driver.

Signed-off-by Edward A. James <[email protected]>
---
 arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts | 44 ++++++++--------------
 arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts | 37 ++++++------------
 arch/arm/boot/dts/aspeed-bmc-opp-garrison.dts  | 45 ++++++----------------
 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts  | 52 ++++++++------------------
 arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts   | 38 ++++++-------------
 arch/arm/boot/dts/aspeed-g4.dtsi               | 34 +++++++++++++++++
 6 files changed, 102 insertions(+), 148 deletions(-)
arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +16 -28
index be1f2d1..7a616bb 100644
@@ -31,34 +31,6 @@
 		};
 	};
 
-	ahb {
-		bmc_pnor: fmc@1e620000 {
-			reg = < 0x1e620000 0x94
-				0x20000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-#include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
-
-		host_pnor: spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-spi";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-			};
-		};
-	};
-
 	leds {
 		compatible = "gpio-leds";
 

@@ -76,6 +48,22 @@
 	};
 };
 
+&bmc_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+#include "aspeed-bmc-opp-flash-layout.dtsi"
+	};
+};
+
+&host_pnor {
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+	};
+};
+
 &pinctrl {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default
arch/arm/boot/dts/aspeed-bmc-opp-firestone.dts +12 -25
index fe63621..46684db 100644
@@ -50,34 +50,21 @@
 			gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
 		};
 	};
+};
 
-	ahb {
-		fmc@1e620000 {
-			reg = < 0x1e620000 0x94
-				0x20000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
+&bmc_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
 #include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
+	};
+};
 
-		spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-spi";
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-			};
-		};
+&host_pnor {
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
 	};
 };
arch/arm/boot/dts/aspeed-bmc-opp-garrison.dts +12 -33

54 lines not on this page · raw message

arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +16 -36

64 lines not on this page · raw message

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +12 -26
index 7132460..5cd7029 100644
@@ -30,35 +30,21 @@
 			reg = <0x47800000 0x00800000>; /* 8MB */
 		};
 	};
+};
 
-	ahb {
-		bmc_pnor: fmc@1e620000 {
-			reg = < 0x1e620000 0x94
-				0x20000000 0x02000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-fmc";
-			aspeed,fmc-has-dma;
-			interrupts = <19>;
-			flash@0 {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
+&bmc_pnor {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
 #include "aspeed-bmc-opp-flash-layout.dtsi"
-			};
-		};
+	};
+};
 
-		host_pnor: spi@1e630000 {
-			reg = < 0x1e630000 0x18
-				0x30000000 0x01000000 >;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "aspeed,ast2400-smc";
-			flash {
-				reg = < 0 >;
-				compatible = "jedec,spi-nor" ;
-				label = "pnor";
-			};
-		};
+&host_pnor {
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
 	};
 };
arch/arm/boot/dts/aspeed-g4.dtsi +34 -0
index d8827d5..9fb7889 100644
@@ -44,6 +44,40 @@
 		#size-cells = <1>;
 		ranges;
 
+		bmc_pnor: fmc@1e620000 {
+			reg = < 0x1e620000 0x94
+				0x20000000 0x02000000 >;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "aspeed,ast2400-fmc";
+			status = "disabled";
+			aspeed,fmc-has-dma;
+			interrupts = <19>;
+			clocks = <&clk_ahb>;
+			clock-names = "ahb";
+			flash@0 {
+				reg = < 0 >;
+				compatible = "jedec,spi-nor" ;
+				status = "disabled";
+			};
+		};
+
+		host_pnor: spi@1e630000 {
+			reg = < 0x1e630000 0x18
+				0x30000000 0x02000000 >;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "aspeed,ast2400-spi";
+			status = "disabled";
+			clocks = <&clk_ahb>;
+			clock-names = "ahb";
+			flash@0 {
+				reg = < 0 >;
+				compatible = "jedec,spi-nor" ;
+				status = "disabled";
+			};
+		};
+
 		vic: interrupt-controller@1e6c0080 {
 			compatible = "aspeed,ast2400-vic";
 			interrupt-controller;
Signature · 1 line
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