Add support for LPASS clock controller for SDM845
v9 cover Add support for LPASS clock controller for SDM845
[v9]
* Update GCC documentation binding with the protected-clocks list.
* Update the GCC code to add the GCC lpass clocks.
* This depends on the acceptance of
https://lore.kernel.org/lkml/[email protected]/
[v8]
* Add CLK_IS_CRITICAL for GCC lpass clocks for lpass clocks access to go through always.
[v7]
* Cleanup header file inclusions.
* Move the comments along with the flags.
* Update the commit with details for CLK_IGNORE_UNUSED.
[v6]
* Update the logic to register the lpass clocks when the device tree property is not present.
* Add the CLK_IGNORE_UNUSED flag for the lpass clocks to not gate the clocks at late_init.
[v5]
* Address the comments in device tree binding to update the reg-names, update the unit address in lpass clock node example and also add reg property for the gcc clock node.
* Update the lpass driver to take care of the reg-names.
[v4]
* Update the description in GCC Documentation binding for 'qcom,lpass-protected'.
* Remove 'qcom,lpass-protected' from LPASS Documentation binding.
* Update KConfig to use Low Power Audio Subsystem.
* Add module_exit() and also update return value for devm_ioremap_resource failure.
[v3]
* Add a device tree property to identify lpass protected GCC clocks.
* Update the GCC driver code to register the lpass clocks when the flag is defined.
* Add comment for clocks using the BRANCH_HALT_SKIP flag.
* Use platform APIs instead of of_address_to_resource.
* Replace devm_ioremap with devm_ioremap_resource.
* Use fixed index for 'lpass_cc' & 'lpass_qdsp6ss' in probe.
[v2]
* Make gcc_lpass_sway_clk static.
* Remove using child nodes and use reg-names to differentiate various domains of LPASS CC.
Add support for the lpass clock controller found on SDM845 based devices. This would allow lpass peripheral loader drivers to control the clocks to bring the subsystem out of reset.
Taniya Das (2):
dt-bindings: clock: Introduce QCOM LPASS clock bindings
clk: qcom: Add lpass clock controller driver for SDM845
.../devicetree/bindings/clock/qcom,gcc.txt | 16 ++ .../devicetree/bindings/clock/qcom,lpasscc.txt | 26 +++ drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sdm845.c | 30 ++++ drivers/clk/qcom/lpasscc-sdm845.c | 192 +++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sdm845.h | 2 + include/dt-bindings/clock/qcom,lpass-sdm845.h | 16 ++ 8 files changed, 292 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,lpasscc.txt create mode 100644 drivers/clk/qcom/lpasscc-sdm845.c create mode 100644 include/dt-bindings/clock/qcom,lpass-sdm845.h
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
PATCH v9 1/2 dt-bindings: clock: Introduce QCOM LPASS clock bindings
Add device tree bindings for Low Power Audio subsystem clock controller for Qualcomm Technology Inc's SDM845 SoCs.
--- .../devicetree/bindings/clock/qcom,gcc.txt | 16 +++++++++++++ .../devicetree/bindings/clock/qcom,lpasscc.txt | 26 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sdm845.h | 2 ++ include/dt-bindings/clock/qcom,lpass-sdm845.h | 16 +++++++++++++ 4 files changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,lpasscc.txt create mode 100644 include/dt-bindings/clock/qcom,lpass-sdm845.h
Documentation/devicetree/bindings/clock/qcom,gcc.txt +16 -0
@@ -35,6 +35,8 @@ be part of GCC and hence the TSENS properties can also be part of the GCC/clock-controller node. For more details on the TSENS properties please refer Documentation/devicetree/bindings/thermal/qcom-tsens.txt +- protected-clocks : Protected clock specifier list as per common clock + binding. Example: clock-controller@900000 {
@@ -55,3 +57,17 @@ Example of GCC with TSENS properties: #reset-cells = <1>; #thermal-sensor-cells = <1>; }; + +Example of GCC with protected-clocks properties: + clock-controller@100000 { + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + protected-clocks = <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <GCC_LPASS_Q6_AXI_CLK>, + <GCC_LPASS_SWAY_CLK>; + };
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +26 -0
@@ -0,0 +1,26 @@ +Qualcomm LPASS Clock Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,sdm845-lpasscc" +- #clock-cells : from common clock binding, shall contain 1. +- reg : shall contain base register address and size, + in the order + Index-0 maps to LPASS_CC register region + Index-1 maps to LPASS_QDSP6SS register region + +Optional properties : +- reg-names : register names of LPASS domain + "cc", "qdsp6ss". + +Example: + +The below node has to be defined in the cases where the LPASS peripheral loader +would bring the subsystem out of reset. + + lpasscc: clock-controller@17014000 { + compatible = "qcom,sdm845-lpasscc"; + reg = <0x17014000 0x1f004>, <0x17300000 0x200>; + reg-names = "cc", "qdsp6ss"; + #clock-cells = <1>; + };
include/dt-bindings/clock/qcom,gcc-sdm845.h +2 -0
@@ -197,6 +197,8 @@#define GCC_QSPI_CORE_CLK_SRC 187#define GCC_QSPI_CORE_CLK 188#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 +#define GCC_LPASS_Q6_AXI_CLK 190 +#define GCC_LPASS_SWAY_CLK 191/* GCC Resets */ #define GCC_MMSS_BCR 0
include/dt-bindings/clock/qcom,lpass-sdm845.h new file +16 -0
@@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2018, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H +#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H + +#define LPASS_AUDIO_WRAPPER_AON_CLK 0 +#define LPASS_Q6SS_AHBM_AON_CLK 1 +#define LPASS_Q6SS_AHBS_AON_CLK 2 +#define LPASS_QDSP6SS_XO_CLK 3 +#define LPASS_QDSP6SS_SLEEP_CLK 4 +#define LPASS_QDSP6SS_CORE_CLK 5 + +#endif
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Rob Herring
maintainerRe: [PATCH v9 1/2] dt-bindings: clock: Introduce QCOM LPASS clock bindings
Quoted 6 lines · Taniya Das
Add device tree bindings for Low Power Audio subsystem clock controller for Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by Taniya Das <[email protected]>--- .../devicetree/bindings/clock/qcom,gcc.txt | 16 +++++++++++++
Seems like a separate change?
Quoted 44 lines
.../devicetree/bindings/clock/qcom,lpasscc.txt | 26 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sdm845.h | 2 ++ include/dt-bindings/clock/qcom,lpass-sdm845.h | 16 +++++++++++++ 4 files changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,lpasscc.txt create mode 100644 include/dt-bindings/clock/qcom,lpass-sdm845.hDocumentation/devicetree/bindings/clock/qcom,gcc.txt +16
-0@@ -35,6 +35,8 @@ be part of GCC and hence the TSENS properties can also be part of the GCC/clock-controller node. For more details on the TSENS properties please refer Documentation/devicetree/bindings/thermal/qcom-tsens.txt +- protected-clocks : Protected clock specifier list as per common clock + binding. Example: clock-controller@900000 {@@ -55,3 +57,17 @@ Example of GCC with TSENS properties: #reset-cells = <1>; #thermal-sensor-cells = <1>; }; + +Example of GCC with protected-clocks properties: + clock-controller@100000 { + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + protected-clocks = <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <GCC_LPASS_Q6_AXI_CLK>, + <GCC_LPASS_SWAY_CLK>; + };Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +0
-0
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt line 10
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +10
-0@@ -0,0 +1,26 @@ +Qualcomm LPASS Clock Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,sdm845-lpasscc" +- #clock-cells : from common clock binding, shall contain 1. +- reg : shall contain base register address and size, + in the order + Index-0 maps to LPASS_CC register region + Index-1 maps to LPASS_QDSP6SS register region
No input clocks?
Quoted 55 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +16
-0+ +Optional properties : +- reg-names : register names of LPASS domain + "cc", "qdsp6ss". + +Example: + +The below node has to be defined in the cases where the LPASS peripheral loader +would bring the subsystem out of reset. + + lpasscc: clock-controller@17014000 { + compatible = "qcom,sdm845-lpasscc"; + reg = <0x17014000 0x1f004>, <0x17300000 0x200>; + reg-names = "cc", "qdsp6ss"; + #clock-cells = <1>; + };include/dt-bindings/clock/qcom,gcc-sdm845.h +2
-0@@ -197,6 +197,8 @@#define GCC_QSPI_CORE_CLK_SRC 187#define GCC_QSPI_CORE_CLK 188#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 +#define GCC_LPASS_Q6_AXI_CLK 190 +#define GCC_LPASS_SWAY_CLK 191/* GCC Resets */ #define GCC_MMSS_BCR 0include/dt-bindings/clock/qcom,lpass-sdm845.h new file +16
-1@@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2018, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H +#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H + +#define LPASS_AUDIO_WRAPPER_AON_CLK 0 +#define LPASS_Q6SS_AHBM_AON_CLK 1 +#define LPASS_Q6SS_AHBS_AON_CLK 2 +#define LPASS_QDSP6SS_XO_CLK 3 +#define LPASS_QDSP6SS_SLEEP_CLK 4 +#define LPASS_QDSP6SS_CORE_CLK 5 + +#endif --Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Re: [PATCH v9 1/2] dt-bindings: clock: Introduce QCOM LPASS clock bindings
Hello Rob,
Quoted 10 lines · Rob Herring
Quoted 6 lines · Taniya Das
Add device tree bindings for Low Power Audio subsystem clock controller for Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by Taniya Das <[email protected]>--- .../devicetree/bindings/clock/qcom,gcc.txt | 16 +++++++++++++Seems like a separate change?
Sure, would spilt it in the next patch.
Quoted 48 lines
Quoted 48 lines
.../devicetree/bindings/clock/qcom,lpasscc.txt | 26 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sdm845.h | 2 ++ include/dt-bindings/clock/qcom,lpass-sdm845.h | 16 +++++++++++++ 4 files changed, 60 insertions(+)create mode 100644
Documentation/devicetree/bindings/clock/qcom,lpasscc.txtcreate mode 100644include/dt-bindings/clock/qcom,lpass-sdm845.hDocumentation/devicetree/bindings/clock/qcom,gcc.txt +16
-0@@ -35,6 +35,8 @@ be part of GCC and hence the TSENS properties can also be part of the GCC/clock-controller node. For more details on the TSENS properties please refer Documentation/devicetree/bindings/thermal/qcom-tsens.txt +- protected-clocks : Protected clock specifier list as per common clock + binding. Example: clock-controller@900000 {@@ -55,3 +57,17 @@ Example of GCC with TSENS properties: #reset-cells = <1>; #thermal-sensor-cells = <1>; }; + +Example of GCC with protected-clocks properties: + clock-controller@100000 { + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + protected-clocks = <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <GCC_LPASS_Q6_AXI_CLK>, + <GCC_LPASS_SWAY_CLK>; + };Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +4
-0@@ -0,0 +1,26 @@ +Qualcomm LPASS Clock Controller Binding +----------------------------------------------- + +Required properties :
Quoted 9 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt line 10
Quoted 6 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +6
-0+- compatible : shall contain "qcom,sdm845-lpasscc" +- #clock-cells : from common clock binding, shall contain 1. +- reg : shall contain base register address and size, + in the order + Index-0 maps to LPASS_CC register region + Index-1 maps to LPASS_QDSP6SS register regionNo input clocks?
There are no input clocks required.
Quoted 55 lines
Quoted 55 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +16
-0+ +Optional properties : +- reg-names : register names of LPASS domain + "cc", "qdsp6ss". + +Example: + +The below node has to be defined in the cases where the LPASS peripheral loader +would bring the subsystem out of reset. + + lpasscc: clock-controller@17014000 { + compatible = "qcom,sdm845-lpasscc"; + reg = <0x17014000 0x1f004>, <0x17300000 0x200>; + reg-names = "cc", "qdsp6ss"; + #clock-cells = <1>; + };include/dt-bindings/clock/qcom,gcc-sdm845.h +2
-0@@ -197,6 +197,8 @@#define GCC_QSPI_CORE_CLK_SRC 187#define GCC_QSPI_CORE_CLK 188#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 +#define GCC_LPASS_Q6_AXI_CLK 190 +#define GCC_LPASS_SWAY_CLK 191/* GCC Resets */ #define GCC_MMSS_BCR 0include/dt-bindings/clock/qcom,lpass-sdm845.h new file +16
-1@@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2018, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H +#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H + +#define LPASS_AUDIO_WRAPPER_AON_CLK 0 +#define LPASS_Q6SS_AHBM_AON_CLK 1 +#define LPASS_Q6SS_AHBS_AON_CLK 2 +#define LPASS_QDSP6SS_XO_CLK 3 +#define LPASS_QDSP6SS_SLEEP_CLK 4 +#define LPASS_QDSP6SS_CORE_CLK 5 + +#endif --Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Signature · 4 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --
PATCH v9 2/2 clk: qcom: Add lpass clock controller driver for SDM845
In reply to Taniya DasAdd support for the lpass clock controller found on SDM845 based devices. This would allow lpass peripheral loader drivers to control the clocks to bring the subsystem out of reset.
LPASS clocks present on the global clock controller would be registered with the clock framework based on the protected-clock flag. Also do not gate these clocks if they are left unused, as the lpass clocks require the global clock controller lpass clocks to be enabled before they are accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock access.
--- drivers/clk/qcom/Kconfig | 9 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sdm845.c | 30 ++++++ drivers/clk/qcom/lpasscc-sdm845.c | 192 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 232 insertions(+) create mode 100644 drivers/clk/qcom/lpasscc-sdm845.c
drivers/clk/qcom/Kconfig +9 -0
@@ -293,6 +293,15 @@ config SDM_DISPCC_845 Say Y if you want to support display devices and functionality such as splash screen. +config SDM_LPASSCC_845 + tristate "SDM845 Low Power Audio Subsystem (LPAAS) Clock Controller" + depends on COMMON_CLK_QCOM + select SDM_GCC_845 + help + Support for the LPASS clock controller on SDM845 devices. + Say Y if you want to use the LPASS branch clocks of the LPASS clock + controller to reset the LPASS subsystem. + config SPMI_PMIC_CLKDIV tristate "SPMI PMIC clkdiv Support" depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
drivers/clk/qcom/Makefile +1 -0
@@ -46,6 +46,7 @@ obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o +obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
drivers/clk/qcom/gcc-sdm845.c +30 -0
@@ -3153,6 +3153,34 @@ enum { }, }; +static struct clk_branch gcc_lpass_q6_axi_clk = { + .halt_reg =0x47000 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x47000 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_lpass_q6_axi_clk" , + .flags =CLK_IS_CRITICAL , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_sway_clk = { + .halt_reg =0x47008 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x47008 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_lpass_sway_clk" , + .flags =CLK_IS_CRITICAL , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct gdsc pcie_0_gdsc = { .gdscr =0x6b004 , .pd = {
@@ -3453,6 +3481,8 @@ enum { [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, + [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, + [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr, };static const struct qcom_reset_map gcc_sdm845_resets[] = {
drivers/clk/qcom/lpasscc-sdm845.c new file +192 -0
192 lines not on this page · raw message
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Stephen Boyd
maintainerRe: [PATCH v9 2/2] clk: qcom: Add lpass clock controller driver for SDM845
Quoting Taniya Das (2018-11-09 17:44:16)
Quoted 40 lines
drivers/clk/qcom/gcc-sdm845.c +28
-0@@ -3153,6 +3153,34 @@ enum { }, }; +static struct clk_branch gcc_lpass_q6_axi_clk = { + .halt_reg =0x47000 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x47000 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_lpass_q6_axi_clk" , + .flags =CLK_IS_CRITICAL , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_sway_clk = { + .halt_reg =0x47008 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x47008 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_lpass_sway_clk" , + .flags =CLK_IS_CRITICAL , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct gdsc pcie_0_gdsc = { .gdscr =0x6b004 , .pd = {
drivers/clk/qcom/gcc-sdm845.c enum { · line 3485
Quoted 5 lines
drivers/clk/qcom/gcc-sdm845.c +2
-0@@ -3453,6 +3481,8 @@ enum { [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, + [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, + [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
Sigh, more coordination with sdm845 mtp problems here due to the clks being protected by firmware. I guess I can just merge this and the mtp dts bits will land in Andy's tree during the same merge window? Or I may need to take the dts bits for this into clk tree so that the broken time is only between two commits.
Quoted 9 lines
drivers/clk/qcom/gcc-sdm845.c +0
-0};static const struct qcom_reset_map gcc_sdm845_resets[] = {drivers/clk/qcom/lpasscc-sdm845.c new file +0
-0@@ -0,0 +1,192 @@
[...]
drivers/clk/qcom/lpasscc-sdm845.c line 152
Quoted 6 lines
drivers/clk/qcom/lpasscc-sdm845.c new file +6
-0+ +static const struct of_device_id lpass_cc_sdm845_match_table[] = { + { .compatible ="qcom,sdm845-lpasscc" }, + { } +}; +MODULE_DEVICE_TABLE (of, lpass_cc_sdm845_match_table);
Move this down to the before the driver structure please.
Quoted 30 lines
drivers/clk/qcom/lpasscc-sdm845.c new file +30
-0+ +static int lpass_cc_sdm845_probe (struct platform_device *pdev) +{ +const struct qcom_cc_desc *desc; +int ret; + + lpass_regmap_config.name ="cc" ; + desc = &lpass_cc_sdm845_desc; + + ret =lpass_clocks_sdm845_probe (pdev,0 , desc); +if (ret) +return ret; + + lpass_regmap_config.name ="qdsp6ss" ; + desc = &lpass_qdsp6ss_sdm845_desc; + +return lpass_clocks_sdm845_probe (pdev,1 , desc); +} + +static struct platform_driver lpass_cc_sdm845_driver = { + .probe = lpass_cc_sdm845_probe, + .driver = { + .name ="sdm845-lpasscc" , + .of_match_table = lpass_cc_sdm845_match_table, + }, +}; + +static int __init lpass_cc_sdm845_init (void ) +{ +return platform_driver_register (&lpass_cc_sdm845_driver);
drivers/clk/qcom/lpasscc-sdm845.c line 192
Quoted 10 lines
drivers/clk/qcom/lpasscc-sdm845.c new file +10
-0+} +subsys_initcall (lpass_cc_sdm845_init); + +static void __exit lpass_cc_sdm845_exit(void) +{ +platform_driver_unregister (&lpass_cc_sdm845_driver); +} +module_exit (lpass_cc_sdm845_exit); + +MODULE_LICENSE ("GPL v2" );
MODULE_DESCRIPTION?
Re: [PATCH v9 2/2] clk: qcom: Add lpass clock controller driver for SDM845
Hello Stephen,
Quoted 63 lines · Stephen Boyd
Quoting Taniya Das (2018-11-09 17:44:16)
Quoted 40 lines
drivers/clk/qcom/gcc-sdm845.c +28
-0@@ -3153,6 +3153,34 @@ enum { }, }; +static struct clk_branch gcc_lpass_q6_axi_clk = { + .halt_reg =0x47000 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x47000 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_lpass_q6_axi_clk" , + .flags =CLK_IS_CRITICAL , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_sway_clk = { + .halt_reg =0x47008 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x47008 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_lpass_sway_clk" , + .flags =CLK_IS_CRITICAL , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct gdsc pcie_0_gdsc = { .gdscr =0x6b004 , .pd = {drivers/clk/qcom/gcc-sdm845.c enum { · line 3485
Quoted 5 lines
drivers/clk/qcom/gcc-sdm845.c +2
-0@@ -3453,6 +3481,8 @@ enum { [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, + [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, + [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,Sigh, more coordination with sdm845 mtp problems here due to the clks being protected by firmware. I guess I can just merge this and the mtp dts bits will land in Andy's tree during the same merge window? Or I may need to take the dts bits for this into clk tree so that the broken time is only between two commits.
Quoted 9 lines
drivers/clk/qcom/gcc-sdm845.c +0
-0};static const struct qcom_reset_map gcc_sdm845_resets[] = {drivers/clk/qcom/lpasscc-sdm845.c new file +0
-0@@ -0,0 +1,192 @@[...]
Quoted 9 lines
drivers/clk/qcom/lpasscc-sdm845.c line 152
Quoted 6 lines
drivers/clk/qcom/lpasscc-sdm845.c new file +6
-0+ +static const struct of_device_id lpass_cc_sdm845_match_table[] = { + { .compatible ="qcom,sdm845-lpasscc" }, + { } +}; +MODULE_DEVICE_TABLE (of, lpass_cc_sdm845_match_table);Move this down to the before the driver structure please.
Would do it in the next patch.
Quoted 34 lines
Quoted 34 lines
drivers/clk/qcom/lpasscc-sdm845.c new file +34
-0+ +static int lpass_cc_sdm845_probe (struct platform_device *pdev) +{ +const struct qcom_cc_desc *desc; +int ret; + + lpass_regmap_config.name ="cc" ; + desc = &lpass_cc_sdm845_desc; + + ret =lpass_clocks_sdm845_probe (pdev,0 , desc); +if (ret) +return ret; + + lpass_regmap_config.name ="qdsp6ss" ; + desc = &lpass_qdsp6ss_sdm845_desc; + +return lpass_clocks_sdm845_probe (pdev,1 , desc); +} + +static struct platform_driver lpass_cc_sdm845_driver = { + .probe = lpass_cc_sdm845_probe, + .driver = { + .name ="sdm845-lpasscc" , + .of_match_table = lpass_cc_sdm845_match_table, + }, +}; + +static int __init lpass_cc_sdm845_init (void ) +{ +return platform_driver_register (&lpass_cc_sdm845_driver); +} +subsys_initcall (lpass_cc_sdm845_init); + +static void __exit lpass_cc_sdm845_exit(void)
Quoted 9 lines
drivers/clk/qcom/lpasscc-sdm845.c line 192
Quoted 6 lines
drivers/clk/qcom/lpasscc-sdm845.c new file +6
-0+{ +platform_driver_unregister (&lpass_cc_sdm845_driver); +} +module_exit (lpass_cc_sdm845_exit); + +MODULE_LICENSE ("GPL v2" );
MODULE_DESCRIPTION?
Would add it in the next patch.
Signature · 4 lines
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