Expose new features for intel processor

This instruction gives software a way to force the processor to complete all modifications to flags, registers and memory from previous instructions and drain all buffered writes to memory before the next instruction is fetched and executed.

The same effect can be obtained using the cpuid instruction. However, cpuid causes modification on the eax, ebx, ecx, and ecx regiters; it also causes a VM exit.

A processor supports SERIALIZE instruction if CPUID.0x0x.0x0:EDX[14] is present. The CPU feature flag is shown as "serialize" in /proc/cpuinfo.

Detailed information on the instructions and CPUID feature flag SERIALIZE can be found in the latest Intel Architecture Instruction Set Extensions and Future Features Programming Reference and Intel 64 and IA-32 Architectures Software Developer's Manual.

Quoted 13 lines · Cathy Zhang

This instruction gives software a way to force the processor to complete all modifications to flags, registers and memory from previous instructions and drain all buffered writes to memory before the next instruction is fetched and executed.

The same effect can be obtained using the cpuid instruction. However, cpuid causes modification on the eax, ebx, ecx, and ecx regiters; it also causes a VM exit.

A processor supports SERIALIZE instruction if CPUID.0x0x.0x0:EDX[14] is present. The CPU feature flag is shown as "serialize" in /proc/cpuinfo.

Quoted 4 lines

Detailed information on the instructions and CPUID feature flag SERIALIZE can be found in the latest Intel Architecture Instruction Set Extensions and Future Features Programming Reference and Intel 64 and IA-32 Architectures Software Developer's Manual.

Can you also wire this up so sync_core() uses it?

Quoted 19 lines · Andy Lutomirski

Quoted 17 lines · Cathy Zhang

This instruction gives software a way to force the processor to complete all modifications to flags, registers and memory from previous instructions and drain all buffered writes to memory before the next instruction is fetched and executed.

The same effect can be obtained using the cpuid instruction. However, cpuid causes modification on the eax, ebx, ecx, and ecx regiters; it also causes a VM exit.

A processor supports SERIALIZE instruction if CPUID.0x0x.0x0:EDX[14] is present. The CPU feature flag is shown as "serialize" in /proc/cpuinfo.

Detailed information on the instructions and CPUID feature flag SERIALIZE can be found in the latest Intel Architecture Instruction Set Extensions and Future Features Programming Reference and Intel 64 and IA-32 Architectures Software Developer's Manual.

Quoted 1 line

Can you also wire this up so sync_core() uses it?

I am cc'ing Fenghua, who has volunteered to work on this. Addind support for SERIALIZE in sync_core() should not block merging these patches, correct?

Quoted 20 lines · Ricardo Neri

Quoted 19 lines · Andy Lutomirski

Quoted 17 lines · Cathy Zhang

This instruction gives software a way to force the processor to complete all modifications to flags, registers and memory from previous instructions and drain all buffered writes to memory before the next instruction is fetched and executed.

The same effect can be obtained using the cpuid instruction. However, cpuid causes modification on the eax, ebx, ecx, and ecx regiters; it also causes a VM exit.

A processor supports SERIALIZE instruction if CPUID.0x0x.0x0:EDX[14] is present. The CPU feature flag is shown as "serialize" in /proc/cpuinfo.

Detailed information on the instructions and CPUID feature flag SERIALIZE can be found in the latest Intel Architecture Instruction Set Extensions and Future Features Programming Reference and Intel 64 and IA-32 Architectures Software Developer's Manual.

Quoted 5 lines

Quoted 1 line

Can you also wire this up so sync_core() uses it?

I am cc'ing Fenghua, who has volunteered to work on this. Addind support for SERIALIZE in sync_core() should not block merging these patches, correct?

Come on. We are not serving KVM first before making this usable on bare metal.

Quoted 3 lines

I am cc'ing Fenghua, who has volunteered to work on this. Addind support for SERIALIZE in sync_core() should not block merging these patches, correct?

Come on. We are not serving KVM first before making this usable on bare metal.

Intel TSX suspend load tracking instructions aim to give a way to choose which memory accesses do not need to be tracked in the TSX read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK for enumeration.

A processor supports Intel TSX suspend load address tracking if CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK
are available when this feature is present.

The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.

Detailed information on the instructions and CPUID feature flag TSXLDTRK
can be found in the latest Intel Architecture Instruction Set Extensions
and Future Features Programming Reference and Intel 64 and IA-32 Architectures Software Developer's Manual.

Signed-off-by Kyung Min Park <[email protected]>

Signed-off-by Cathy Zhang <[email protected]>

---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

arch/x86/include/asm/cpufeatures.h +0 -0

index adf45cf..34b66d7 100644
@@ -366,6 +366,7 @@
 #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU

buffers */
#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* ""
TSX_FORCE_ABORT */
#define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE
instruction */
+#define X86_FEATURE_TSX_LDTRK (18*32+16) /* TSX Suspend
Load Address Tracking */

#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* ""
Speculation Control (IBRS + IBPB) */
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single
Thread Indirect Branch Predictors */

Intel TSX suspend load tracking instructions aim to give a way to choose which memory accesses do not need to be tracked in the TSX read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK for enumeration.

A processor supports Intel TSX suspend load address tracking if CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK are available when this feature is present.

The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.

Detailed information on the instructions and CPUID feature flag TSXLDTRK can be found in the latest Intel Architecture Instruction Set Extensions and Future Features Programming Reference and Intel 64 and IA-32 Architectures Software Developer's Manual.

Signed-off-by Kyung Min Park <[email protected]>

Signed-off-by Cathy Zhang <[email protected]>

---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

arch/x86/include/asm/cpufeatures.h +0 -0

index adf45cf..34b66d7 100644

Quoted 27 lines · Cathy Zhang

Intel TSX suspend load tracking instructions aim to give a way to choose which memory accesses do not need to be tracked in the TSX read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK for enumeration.

A processor supports Intel TSX suspend load address tracking if CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK are available when this feature is present.

The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.

Detailed information on the instructions and CPUID feature flag TSXLDTRK can be found in the latest Intel Architecture Instruction Set Extensions and Future Features Programming Reference and Intel 64 and IA-32 Architectures Software Developer's Manual.

Signed-off-by Kyung Min Park <[email protected]>

Signed-off-by Cathy Zhang <[email protected]>

---
  arch/x86/include/asm/cpufeatures.h | 1 +
  1 file changed, 1 insertion(+)

arch/x86/include/asm/cpufeatures.h +0 -0

index adf45cf..34b66d7 100644

arch/x86/include/asm/cpufeatures.h line 369

Quoted 4 lines

arch/x86/include/asm/cpufeatures.h +1 -0

@@ -366,6 +366,7 @@
  #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
  #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
  #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
+#define X86_FEATURE_TSX_LDTRK           (18*32+16) /* TSX Suspend Load Address Tracking */

No tabs?

:(

SERIALIZE instruction is supported by intel processors, like Sapphire Rapids. Expose it in KVM supported cpuid.

Signed-off-by Cathy Zhang <[email protected]>

---
 arch/x86/kvm/cpuid.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

arch/x86/kvm/cpuid.c +2 -1

index 8a294f9..e603aeb 100644
@@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)
 	kvm_cpu_cap_mask(CPUID_7_EDX,
 		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
 		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
-		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM)
+		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
+		F(SERIALIZE)
 	);
 
 	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */

Signature · 1 line

1.8.3.1

Quoted 2 lines · Cathy Zhang

SERIALIZE instruction is supported by intel processors, like Sapphire Rapids. Expose it in KVM supported cpuid.

Providing at least a rough overview of the instruction, e.g. its enumeration, usage, fault rules, controls, etc... would be nice. In isolation, the changelog isn't remotely helpful in understanding the correctness of the patch.

Quoted 23 lines

Signed-off-by Cathy Zhang <[email protected]>

---
  arch/x86/kvm/cpuid.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

arch/x86/kvm/cpuid.c +2 -1

index 8a294f9..e603aeb 100644
@@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)
  	kvm_cpu_cap_mask(CPUID_7_EDX,
  		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
  		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
-		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM)
+		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
+		F(SERIALIZE)
  	);
 
  	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */

Signature · 1 line

1.8.3.1

Quoted 4 lines · Sean Christopherson

Quoted 2 lines · Cathy Zhang

SERIALIZE instruction is supported by intel processors, like Sapphire Rapids. Expose it in KVM supported cpuid.

Providing at least a rough overview of the instruction, e.g. its

enumeration,

Quoted 1 line

usage, fault rules, controls, etc... would be nice. In isolation,

the

Quoted 1 line

changelog isn't remotely helpful in understanding the correctness of

the

Quoted 1 line

patch.

Thanks Sean! Add it in the next version.

Quoted 19 lines

Quoted 19 lines

Signed-off-by Cathy Zhang <[email protected]>

---
  arch/x86/kvm/cpuid.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

arch/x86/kvm/cpuid.c +2 -1

index 8a294f9..e603aeb 100644
@@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)
  	kvm_cpu_cap_mask(CPUID_7_EDX,
  		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
  		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
-		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM)
+		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
+		F(SERIALIZE)
  	);
 

Quoted 4 lines

Quoted 4 lines

arch/x86/kvm/cpuid.c +0 -0

  	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */

Signature · 1 line

1.8.3.1

Quoted 30 lines · Cathy

Quoted 4 lines · Sean Christopherson

Quoted 2 lines · Cathy Zhang

SERIALIZE instruction is supported by intel processors, like Sapphire Rapids. Expose it in KVM supported cpuid.

Providing at least a rough overview of the instruction, e.g. its

enumeration,

Quoted 1 line

usage, fault rules, controls, etc... would be nice. In isolation,

the

Quoted 1 line

changelog isn't remotely helpful in understanding the correctness of

the

Quoted 1 line

patch.

Thanks Sean! Add it in the next version.

Quoted 18 lines

Quoted 18 lines

Signed-off-by Cathy Zhang <[email protected]>

---
   arch/x86/kvm/cpuid.c | 3 ++-
   1 file changed, 2 insertions(+), 1 deletion(-)

arch/x86/kvm/cpuid.c +2 -1

index 8a294f9..e603aeb 100644
@@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)
   	kvm_cpu_cap_mask(CPUID_7_EDX,
   		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
   		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
-		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM)
+		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
+		F(SERIALIZE)
   	);
 

Quoted 4 lines

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arch/x86/kvm/cpuid.c +0 -0

   	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */

Signature · 1 line

1.8.3.1

At least that one is easy: SERIALIZE is architecturally a NOP, but with hard serialization, like CPUID or IRET.

Quoted 1 line · On 7/15/2020 7:05 AM, [email protected] wrote:

On July 14, 2020 3:42:08 PM PDT, "Zhang, Cathy"

Quoted 9 lines · <[email protected]> wrote:

Quoted 9 lines · Sean Christopherson

Quoted 4 lines · Cathy Zhang

Quoted 2 lines

SERIALIZE instruction is supported by intel processors, like Sapphire Rapids. Expose it in KVM supported cpuid.

Providing at least a rough overview of the instruction, e.g. its

enumeration,

Quoted 1 line

usage, fault rules, controls, etc... would be nice. In isolation,

the

Quoted 1 line

changelog isn't remotely helpful in understanding the correctness

of

Quoted 21 lines

Quoted 21 lines

the

Quoted 1 line

patch.

Thanks Sean! Add it in the next version.

Quoted 18 lines

Quoted 18 lines

Signed-off-by Cathy Zhang <[email protected]>

---
   arch/x86/kvm/cpuid.c | 3 ++-
   1 file changed, 2 insertions(+), 1 deletion(-)

arch/x86/kvm/cpuid.c +2 -1

index 8a294f9..e603aeb 100644
@@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)
   	kvm_cpu_cap_mask(CPUID_7_EDX,
   		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
   		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
-		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM)
+		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
+		F(SERIALIZE)
   	);
 

Quoted 1 line

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arch/x86/kvm/cpuid.c void kvm_set_cpu_caps(void) · line 348

Quoted 1 line

arch/x86/kvm/cpuid.c +0 -0

   	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software.

*/

Quoted 4 lines

Quoted 3 lines

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Signature · 1 line

1.8.3.1

At least that one is easy: SERIALIZE is architecturally a NOP, but

with hard serialization, like CPUID or IRET.
SERIALIZE does not modify registers, arithmetic flags or memory, which is different with CPUID.

Cathy Zhang (2):
x86: Expose SERIALIZE for supported cpuid
x86: Expose TSX Suspend Load Address Tracking