DM644x: (2nd try) This patch removes all board specific code from the arch. part for DM644x (DaVinci) boards

PATCH New Pieter Voorthuijsen 3 participants 4 messages Mar 21, 2008 – Mar 25, 2008 Arm/actions semi architecture

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Pieter Voorthuijsen

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2008-03-21 11:24 UTC #0 lore raw

PATCH 1/1 DM644x: (2nd try) This patch removes all board specific code from the arch. part for DM644x (DaVinci) boards

Hello Jean-Christophe,

Thanks for looking into the code, unfortunatly I cannot use the git-send-email :( Outlook seems to only be able to wrap so I'll attach the pacthes as a file... I double checked for spaces and coding style..

Here's the original subject:

In the current implementation of the DM644x (DaVinci) achitecture there is a lot of code in the /cpu/arm926ejs/davinci folder that is meant to be board specific. I'm talking about EMIF timing/width configuration for NAND and NOR but also DRAM timing settings which are of course different for boards. This patch makes the board config files configure the architecture files (lowlevel_init.S and nand.c) with defines.

Also there is a small addition to add support for the DVEVM, the only difference is an Intel NOR instead of an AMD, so blocksizes are different.

This is tested with the Davinci EVM (Old and new one), the other boards (Sonata and Schmoogie) are building with these patches.

Best regards,
Pieter

Pieter Voorthuijsen
Prodrive B.V.
Science Park Eindhoven
P.O. box 28030
5602 JA Eindhoven
The Netherlands

Email pieter.voorthuijsen at prodrive.nl
Tel: +31-40-2676258
Fax: +31-40-2676201
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Jean-Christophe PLAGNIOL-VILLARD

2008-03-22 13:23 UTC #1 lore raw

PATCH 1/1 DM644x: (2nd try) This patch removes all board specific code from the arch. part for DM644x (DaVinci) boards

cpu/arm926ejs/davinci/lowlevel_init.S

Quoted 9 lines · Pieter Voorthuijsen

Hello Jean-Christophe,
Thanks for looking into the code, unfortunatly I cannot use the git-send-email :( Outlook seems to only be able to wrap so I'll attach the pacthes as a file... I double checked for spaces and coding style..
cpu/arm926ejs/davinci/lowlevel_init.S +0 -0
index a87c112..9b03628 100644

cpu/arm926ejs/davinci/lowlevel_init.S line 8

Quoted 9 lines

cpu/arm926ejs/davinci/lowlevel_init.S +3 -0

@@ -3,6 +3,11 @@
 *
 * Copyright (C) 2007 Sergey Kubushyn <[email protected]>
 *
+ * Copyright (C) 2008 Prodrive BV <[email protected]>
+ * Changed:
+ * Made board specific defines such as DDR timing and PLL

Whitespace please remove

include/configs/davinci_dvevm.h line 55

Quoted 13 lines

cpu/arm926ejs/davinci/lowlevel_init.S +2 -0

+ * dividers. These should be set in the board config file.
+ *
 * Partially based on TI sources, original copyrights follow:
 */

include/configs/davinci_dvevm.h +1 -0

index 8ecd059..f849be6 100644
@@ -52,6 +52,8 @@
 #define DV_EVM
 #define CFG_NAND_SMALLPAGE
 #define CFG_USE_NOR
+#define CFG_USE_INTEL_NOR	/* Define this when your DVEVM has Intel

Whitespace please remove

include/configs/davinci_dvevm.h line 56

Quoted 1 line

include/configs/davinci_dvevm.h +1 -0
+				 * flash instead of AMD flash */

and please use this style of comment

/*
* Comment
* Comment
*/

Quoted 8 lines

include/configs/davinci_dvevm.h +1 -0

 /*===================*/
 /* SoC Configuration */
 /*===================*/

@@ -60,6 +62,24 @@
 #define CFG_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CFG_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CFG_HZ			1000
+#define CFG_DAVINCI_PINMUX_0	0x00000c1f

include/configs/davinci_dvevm.h line 75

Quoted 10 lines

include/configs/davinci_dvevm.h +10 -0

+#define CFG_DAVINCI_WAITCFG	0x00000000
+#define CFG_DAVINCI_ACFG2	0x3ffffffd	/* CE configs */
+#define CFG_DAVINCI_ACFG3	0x3ffffffd
+#define CFG_DAVINCI_ACFG4	0x3ffffffd
+#define CFG_DAVINCI_ACFG5	0x3ffffffd
+#undef	CFG_DAVINCI_NANDCE			/* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL	0x50006405	/* DDR timing config */
+#define CFG_DAVINCI_SDREF	0x000005c3
+#define CFG_DAVINCI_SDCFG	0x00178632	/* 8 banks */
+/*#define CFG_DAVINCI_SDCFG	0x00178622*/	/* 4 banks */

if no need please remove it

include/configs/davinci_dvevm.h line 81

Quoted 6 lines

include/configs/davinci_dvevm.h +5 -0

+#define CFG_DAVINCI_SDTIM0	0x28923211
+#define CFG_DAVINCI_SDTIM1	0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0	0x00444400
+#define CFG_DAVINCI_PLL1_PLLM	0x15		/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_FLASH_USE_BUFFER_WRITE 1		/* use buffered writes (20x faster)     */
 #define PHYS_FLASH_1		0x02000000	/* CS2 Base address 	 */

Whitespace please remove

include/configs/davinci_dvevm.h line 83

Quoted 2 lines

include/configs/davinci_dvevm.h +0 -0

 #define CFG_FLASH_BASE		PHYS_FLASH_1	/* Flash Base for U-Boot */
 #define PHYS_FLASH_SIZE		0x2000000	/* Flash size 32MB 	 */

Whitespace please remove

Quoted 8 lines

#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
include/configs/davinci_dvevm.h +6 -0
+#ifdef CFG_USE_INTEL_NOR
+#define CFG_FLASH_SECT_SZ	0x20000		/* 128KB sect size INTEL Flash */
+#define CFG_FLASH_PROTECTION	1
+#else
+#define CFG_FLASH_SECT_SZ	0x10000		/* 64KB sect size AMD Flash */
+#endif

Quoted 5 lines

#endif
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */

Whitespace please remove

Quoted 11 lines

#define CONFIG_MISC_INIT_R

include/configs/davinci_dvevm.h +1 -1

-#undef CONFIG_BOOTDELAY
+#undef	CONFIG_BOOTDELAY

include/configs/davinci_schmoogie.h +0 -0

index 96c9a30..b28405e 100644
@@ -35,6 +35,24 @@
 #define CFG_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CFG_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CFG_HZ			1000

include/configs/davinci_schmoogie.h line 47

Quoted 10 lines

include/configs/davinci_schmoogie.h +10 -0

+#define CFG_DAVINCI_PINMUX_0	0x00000c1f
+#define CFG_DAVINCI_WAITCFG	0x00000000
+#define CFG_DAVINCI_ACFG2	0x0432229c	/* CE configs */
+#define CFG_DAVINCI_ACFG3	0x3ffffffd
+#define CFG_DAVINCI_ACFG4	0x3ffffffd
+#define CFG_DAVINCI_ACFG5	0x3ffffffd
+#define CFG_DAVINCI_NANDCE	2		/* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL	0x50006405	/* DDR timing config */
+#define CFG_DAVINCI_SDREF	0x000005c3
+/*#define CFG_DAVINCI_SDCFG	0x00178632*/	/* 8 banks */

if no need please remove it

Quoted 12 lines

include/configs/davinci_schmoogie.h +3 -0

+#define CFG_DAVINCI_SDCFG	0x00178622	/* 4 banks */
+#define CFG_DAVINCI_SDTIM0	0x28923211
+#define CFG_DAVINCI_SDTIM1	0x0016c722

include/configs/davinci_sonata.h +1 -0

index de8c4fa..5201a48 100644
@@ -60,6 +60,24 @@
 #define CFG_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CFG_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CFG_HZ			1000
+#define CFG_DAVINCI_PINMUX_0	0x00000c1f

include/configs/davinci_sonata.h line 73

Quoted 10 lines

include/configs/davinci_sonata.h +10 -0

+#define CFG_DAVINCI_WAITCFG	0x00000000
+#define CFG_DAVINCI_ACFG2	0x3ffffffd	/* CE configs */
+#define CFG_DAVINCI_ACFG3	0x3ffffffd
+#define CFG_DAVINCI_ACFG4	0x3ffffffd
+#define CFG_DAVINCI_ACFG5	0x3ffffffd
+#undef  CFG_DAVINCI_NANDCE			/* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL	0x50006405	/* DDR timing config */
+#define CFG_DAVINCI_SDREF	0x000005c3
+#define CFG_DAVINCI_SDCFG	0x00178632	/* 8 banks */
+/*#define CFG_DAVINCI_SDCFG	0x00178622*/	/* 4 banks */

if no need please remove it

include/configs/davinci_sonata.h line 75

Quoted 2 lines

include/configs/davinci_sonata.h +2 -0

+#define CFG_DAVINCI_SDTIM0	0x28923211
+#define CFG_DAVINCI_SDTIM1	0x0016c722

NB : please do not send patch as attechement

Best Regards,
J.

Pieter Voorthuijsen

author

2008-03-25 09:24 UTC #2 lore raw

PATCH 1/1 DM644x: (2nd try) This patch removes all boardspecific code from the arch. part for DM644x (DaVinci) boards

Almost there :)

Signed-off-by Pieter Voorthuijsen <[email protected]>

---
 cpu/arm926ejs/davinci/lowlevel_init.S   |   79 ++++++++++++++++++++-----------
 cpu/arm926ejs/davinci/nand.c            |   41 ++--------------
 include/asm-arm/arch-davinci/hardware.h |    2 +
 include/configs/davinci_dvevm.h         |   43 ++++++++++++++---
 include/configs/davinci_schmoogie.h     |   18 +++++++-
 include/configs/davinci_sonata.h        |   17 +++++++
 6 files changed, 127 insertions(+), 73 deletions(-)

cpu/arm926ejs/davinci/lowlevel_init.S +51 ~~-28~~

index a87c112..a5e3639 100644
@@ -3,6 +3,11 @@
  *
  * Copyright (C) 2007 Sergey Kubushyn <[email protected]>
  *
+ * Copyright (C) 2008 Prodrive BV <[email protected]>
+ * Changed:
+ * Made board specific defines such as DDR timing and PLL
+ * dividers. These should be set in the board config file
+ *
  * Partially based on TI sources, original copyrights follow:
  */

@@ -156,17 +161,17 @@ WaitPPL2Loop:
 
 	/* Program the PLL Multiplier */
 	ldr	r6, PLL2_PLLM
-	mov	r2, $0x17	/* 162 MHz */
+	mov	r2, $CFG_DAVINCI_PLL2_PLLM
 	str	r2, [r6]
 
 	/* Program the PLL2 Divisor Value */
 	ldr	r6, PLL2_DIV2
-	mov	r3, $0x01
+	mov	r3, $CFG_DAVINCI_PLL2_DIV2
 	str	r3, [r6]
 
 	/* Program the PLL2 Divisor Value */
 	ldr	r6, PLL2_DIV1
-	mov	r4, $0x0b	/* 54 MHz */
+	mov	r4, $CFG_DAVINCI_PLL2_DIV1
 	str	r4, [r6]
 
 	/* PLL2 DIV2 MMR */

@@ -273,7 +278,7 @@ checkDDRStatClkStop:
 	bne	checkDDRStatClkStop
 
 	/*------------------------------------------------------*
-	 * Program DDR2 MMRs for 162MHz Setting			*
+	 * Program DDR2 MMRs					*
 	 *------------------------------------------------------*/
 
 	/* Program PHY Control Register */

@@ -288,12 +293,12 @@ checkDDRStatClkStop:
 
 	/* Program SDRAM TIM-0 Config Register */
 	ldr	r6, SDTIM0
-	ldr	r7, SDTIM0_VAL_162MHz
+	ldr	r7, SDTIM0_VAL
 	str	r7, [r6]
 
 	/* Program SDRAM TIM-1 Config Register */
 	ldr	r6, SDTIM1
-	ldr	r7, SDTIM1_VAL_162MHz
+	ldr	r7, SDTIM1_VAL
 	str	r7, [r6]
 
 	/* Program the SDRAM Bank Config Control Register */

@@ -435,7 +440,7 @@ WaitLoop:
 
 	/* Program the PLL Multiplier */
 	ldr	r6, PLL1_PLLM
-	mov	r3, $0x15	/* For 594MHz */
+	mov	r3, $CFG_DAVINCI_PLL1_PLLM
 	str	r3, [r6]
 
 	/* Wait for PLL to Reset Properly */

@@ -467,7 +472,7 @@ PLL1Lock:
 	nop
 
 	/*------------------------------------------------------*
-	 * AEMIF configuration for NOR Flash (double check)     *
+	 * AEMIF configuration for NAND/NOR Flash		*
 	 *------------------------------------------------------*/
 	ldr	r0, _PINMUX0
 	ldr	r1, _DEV_SETTING

@@ -479,6 +484,12 @@ PLL1Lock:
 	orr	r2, r2, r1
 	str	r2, [r0]
 
+	ldr	r0, ACFG2
+	ldr	r1, ACFG2_VAL
+	ldr	r2, [r0]
+	and	r1, r2, r1
+	str	r1, [r0]
+
 	ldr	r0, ACFG3
 	ldr	r1, ACFG3_VAL
 	ldr	r2, [r0]

@@ -497,6 +508,12 @@ PLL1Lock:
 	and	r1, r2, r1
 	str	r1, [r0]
 
+	ldr	r0, NANDFCR
+	ldr	r1, NANDFCR_VAL
+	ldr	r2, [r0]
+	and	r1, r2, r1
+	str	r1, [r0]
+
 	/*--------------------------------------*
 	 * VTP manual Calibration               *
 	 *--------------------------------------*/

@@ -560,24 +577,36 @@ _PINMUX1:
 	.word	0x01c40004		/* Device Configuration Registers */
 
 _DEV_SETTING:
-	.word	0x00000c1f
+	.word	CFG_DAVINCI_PINMUX_0
 
 WAITCFG:
 	.word	0x01e00004
 WAITCFG_VAL:
-	.word	0
+	.word	CFG_DAVINCI_WAITCFG
+ACFG2:
+	.word	0x01e00010
+ACFG2_VAL:
+	.word	CFG_DAVINCI_ACFG2
 ACFG3:
 	.word	0x01e00014
 ACFG3_VAL:
-	.word	0x3ffffffd
+	.word	CFG_DAVINCI_ACFG3
 ACFG4:
 	.word	0x01e00018
 ACFG4_VAL:
-	.word	0x3ffffffd
+	.word	CFG_DAVINCI_ACFG4
 ACFG5:
 	.word	0x01e0001c
 ACFG5_VAL:
-	.word	0x3ffffffd
+	.word	CFG_DAVINCI_ACFG5
+NANDFCR:
+	.word	0x01e00060
+NANDFCR_VAL:
+#ifdef CFG_DAVINCI_NANDCE
+	.word	(1 << (CFG_DAVINCI_NANDCE - 2))
+#else
+	.word	0x00000000
+#endif
 
 MDCTL_DDR2:
 	.word	0x01c41a34

@@ -599,33 +628,27 @@ PSC_FLAG_CLEAR:
 PSC_GEM_FLAG_CLEAR:
 	.word	0xfffffeff
 
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
+/* DDR2 MMR & CONFIGURATION VALUES */
 DDRCTL:
 	.word	0x200000e4
 DDRCTL_VAL:
-	.word	0x50006405
+	.word	CFG_DAVINCI_DDRCTL
 SDREF:
 	.word	0x2000000c
 SDREF_VAL:
-	.word	0x000005c3
+	.word	CFG_DAVINCI_SDREF
 SDCFG:
 	.word	0x20000008
 SDCFG_VAL:
-#ifdef	DDR_4BANKS
-	.word	0x00178622
-#elif defined DDR_8BANKS
-	.word	0x00178632
-#else
-#error "Unknown DDR configuration!!!"
-#endif
+	.word	CFG_DAVINCI_SDCFG
 SDTIM0:
 	.word	0x20000010
-SDTIM0_VAL_162MHz:
-	.word	0x28923211
+SDTIM0_VAL:
+	.word	CFG_DAVINCI_SDTIM0
 SDTIM1:
 	.word	0x20000014
-SDTIM1_VAL_162MHz:
-	.word	0x0016c722
+SDTIM1_VAL:
+	.word	CFG_DAVINCI_SDTIM1
 VTPIOCR:
 	.word	0x200000f0	/* VTP IO Control register */
 DDRVTPR:

@@ -699,7 +722,7 @@ PLL2_DIV_MASK:
 MMARG_BRF0:
 	.word	0x01c42010	/* BRF margin mode 0 (R/W)*/
 MMARG_BRF0_VAL:
-	.word	0x00444400
+	.word	CFG_DAVINCI_MMARG_BRF0
 
 DDR2_START_ADDR:
 	.word	0x80000000

cpu/arm926ejs/davinci/nand.c +5 ~~-36~~

59 lines not on this page · raw message

include/asm-arm/arch-davinci/hardware.h +2 -0

index ebcdcfe..2b3eb90 100644
@@ -150,6 +150,8 @@ typedef volatile unsigned int *	dv_reg_p;
 
 #define VDD3P3V_PWDN			(0x01c40048)
 #define UART0_PWREMU_MGMT		(0x01c20030)
+#define UART1_PWREMU_MGMT		(0x01c20430)
+#define UART2_PWREMU_MGMT		(0x01c20830)
 
 #define PSC_SILVER_BULLET		(0x01c41a20)

include/configs/davinci_dvevm.h +35 -8

78 lines not on this page · raw message

include/configs/davinci_schmoogie.h +17 -1

index 96c9a30..2449522 100644
@@ -35,6 +35,23 @@
 #define CFG_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CFG_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CFG_HZ			1000
+#define CFG_DAVINCI_PINMUX_0	0x00000c1f
+#define CFG_DAVINCI_WAITCFG	0x00000000
+#define CFG_DAVINCI_ACFG2	0x0432229c	/* CE configs */
+#define CFG_DAVINCI_ACFG3	0x3ffffffd
+#define CFG_DAVINCI_ACFG4	0x3ffffffd
+#define CFG_DAVINCI_ACFG5	0x3ffffffd
+#define CFG_DAVINCI_NANDCE	2		/* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL	0x50006405	/* DDR timing config */
+#define CFG_DAVINCI_SDREF	0x000005c3
+#define CFG_DAVINCI_SDCFG	0x00178622	/* 4 banks */
+#define CFG_DAVINCI_SDTIM0	0x28923211
+#define CFG_DAVINCI_SDTIM1	0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0	0x00444400
+#define CFG_DAVINCI_PLL1_PLLM	0x15		/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL2_PLLM	0x17		/* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1	0x0b		/* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2	0x01
 /*=============*/
 /* Memory Info */
 /*=============*/

@@ -46,7 +63,6 @@
 #define CONFIG_STACKSIZE	(256*1024)	/* regular stack */
 #define PHYS_SDRAM_1		0x80000000	/* DDR Start */
 #define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
-#define DDR_4BANKS				/* 4-bank DDR2 (128MB) */
 /*====================*/
 /* Serial Driver info */
 /*====================*/

include/configs/davinci_sonata.h +17 -0

index de8c4fa..3436037 100644
@@ -60,6 +60,23 @@
 #define CFG_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CFG_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CFG_HZ			1000
+#define CFG_DAVINCI_PINMUX_0	0x00000c1f
+#define CFG_DAVINCI_WAITCFG	0x00000000
+#define CFG_DAVINCI_ACFG2	0x3ffffffd	/* CE configs */
+#define CFG_DAVINCI_ACFG3	0x3ffffffd
+#define CFG_DAVINCI_ACFG4	0x3ffffffd
+#define CFG_DAVINCI_ACFG5	0x3ffffffd
+#undef  CFG_DAVINCI_NANDCE			/* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL	0x50006405	/* DDR timing config */
+#define CFG_DAVINCI_SDREF	0x000005c3
+#define CFG_DAVINCI_SDCFG	0x00178632	/* 8 banks */
+#define CFG_DAVINCI_SDTIM0	0x28923211
+#define CFG_DAVINCI_SDTIM1	0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0	0x00444400
+#define CFG_DAVINCI_PLL1_PLLM	0x15		/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL2_PLLM	0x17		/* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1	0x0b		/* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2	0x01
 /*====================================================*/
 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */

Signature · 1 line

1.5.3.7

-----Original Message-----
From: Jean-Christophe PLAGNIOL-VILLARD [mailto:plagnioj at jcrosoft.com]
Sent: zaterdag 22 maart 2008 14:23
To: Pieter Voorthuijsen
Cc: u-boot-users at lists.sourceforge.net
Subject: Re: [PATCH] DM644x: (2nd try) This patch removes all boardspecific code from the arch. part for DM644x (DaVinci) boards

cpu/arm926ejs/davinci/lowlevel_init.S

Quoted 10 lines · Pieter Voorthuijsen

Hello Jean-Christophe,
Thanks for looking into the code, unfortunatly I cannot use the git-send-email :( Outlook seems to only be able to wrap so I'll attach the pacthes as a file... I double checked for spaces and coding style..
cpu/arm926ejs/davinci/lowlevel_init.S +0 -0
index a87c112..9b03628 100644

cpu/arm926ejs/davinci/lowlevel_init.S line 8

Quoted 9 lines

cpu/arm926ejs/davinci/lowlevel_init.S +3 -0

@@ -3,6 +3,11 @@
 *
 * Copyright (C) 2007 Sergey Kubushyn <[email protected]>
 *
+ * Copyright (C) 2008 Prodrive BV <[email protected]>
+ * Changed:
+ * Made board specific defines such as DDR timing and PLL

^ Whitespace please remove

include/configs/davinci_dvevm.h line 55

Quoted 13 lines

cpu/arm926ejs/davinci/lowlevel_init.S +2 -0
+ * dividers. These should be set in the board config file.
+ *
 * Partially based on TI sources, original copyrights follow:
 */
(quoted diff) +0 -0
b/include/configs/davinci_dvevm.h index 8ecd059..f849be6 100644
include/configs/davinci_dvevm.h +1 -0
@@ -52,6 +52,8 @@
 #define DV_EVM
 #define CFG_NAND_SMALLPAGE
 #define CFG_USE_NOR
+#define CFG_USE_INTEL_NOR	/* Define this when your DVEVM has Intel 

^ Whitespace please remove

include/configs/davinci_dvevm.h line 56

Quoted 1 line

include/configs/davinci_dvevm.h +1 -0
+				 * flash instead of AMD flash */

and please use this style of comment

/*
* Comment
* Comment
*/

Quoted 8 lines

include/configs/davinci_dvevm.h +1 -0

 /*===================*/
 /* SoC Configuration */
 /*===================*/

@@ -60,6 +62,24 @@
 #define CFG_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CFG_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CFG_HZ			1000
+#define CFG_DAVINCI_PINMUX_0	0x00000c1f

include/configs/davinci_dvevm.h line 75

Quoted 10 lines

include/configs/davinci_dvevm.h +10 -0

+#define CFG_DAVINCI_WAITCFG	0x00000000
+#define CFG_DAVINCI_ACFG2	0x3ffffffd	/* CE configs */
+#define CFG_DAVINCI_ACFG3	0x3ffffffd
+#define CFG_DAVINCI_ACFG4	0x3ffffffd
+#define CFG_DAVINCI_ACFG5	0x3ffffffd
+#undef	CFG_DAVINCI_NANDCE			/* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL	0x50006405	/* DDR timing config */
+#define CFG_DAVINCI_SDREF	0x000005c3
+#define CFG_DAVINCI_SDCFG	0x00178632	/* 8 banks */
+/*#define CFG_DAVINCI_SDCFG	0x00178622*/	/* 4 banks */

if no need please remove it

include/configs/davinci_dvevm.h line 81

Quoted 6 lines

include/configs/davinci_dvevm.h +5 -0

+#define CFG_DAVINCI_SDTIM0	0x28923211
+#define CFG_DAVINCI_SDTIM1	0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0	0x00444400
+#define CFG_DAVINCI_PLL1_PLLM	0x15		/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_FLASH_USE_BUFFER_WRITE 1		/* use buffered writes (20x faster)     */
 #define PHYS_FLASH_1		0x02000000	/* CS2 Base address 	 */

^ Whitespace please remove

include/configs/davinci_dvevm.h line 83

Quoted 2 lines

include/configs/davinci_dvevm.h +0 -0

 #define CFG_FLASH_BASE		PHYS_FLASH_1	/* Flash Base for U-Boot */
 #define PHYS_FLASH_SIZE		0x2000000	/* Flash size 32MB 	 */

^ Whitespace please remove

Quoted 8 lines

#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
include/configs/davinci_dvevm.h +6 -0
+#ifdef CFG_USE_INTEL_NOR
+#define CFG_FLASH_SECT_SZ	0x20000		/* 128KB sect size INTEL Flash */
+#define CFG_FLASH_PROTECTION	1
+#else
+#define CFG_FLASH_SECT_SZ	0x10000		/* 64KB sect size AMD Flash */
+#endif

Quoted 5 lines

#endif
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */

Whitespace please remove

Quoted 12 lines

#define CONFIG_MISC_INIT_R

include/configs/davinci_dvevm.h +1 -1

-#undef CONFIG_BOOTDELAY
+#undef	CONFIG_BOOTDELAY

include/configs/davinci_schmoogie.h +0 -0

index 96c9a30..b28405e 100644
@@ -35,6 +35,24 @@
 #define CFG_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CFG_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CFG_HZ			1000

include/configs/davinci_schmoogie.h line 47

Quoted 10 lines

include/configs/davinci_schmoogie.h +10 -0

+#define CFG_DAVINCI_PINMUX_0	0x00000c1f
+#define CFG_DAVINCI_WAITCFG	0x00000000
+#define CFG_DAVINCI_ACFG2	0x0432229c	/* CE configs */
+#define CFG_DAVINCI_ACFG3	0x3ffffffd
+#define CFG_DAVINCI_ACFG4	0x3ffffffd
+#define CFG_DAVINCI_ACFG5	0x3ffffffd
+#define CFG_DAVINCI_NANDCE	2		/* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL	0x50006405	/* DDR timing config */
+#define CFG_DAVINCI_SDREF	0x000005c3
+/*#define CFG_DAVINCI_SDCFG	0x00178632*/	/* 8 banks */

if no need please remove it

Quoted 13 lines

include/configs/davinci_schmoogie.h +3 -0

+#define CFG_DAVINCI_SDCFG	0x00178622	/* 4 banks */
+#define CFG_DAVINCI_SDTIM0	0x28923211
+#define CFG_DAVINCI_SDTIM1	0x0016c722

include/configs/davinci_sonata.h +1 -0

index de8c4fa..5201a48 100644
@@ -60,6 +60,24 @@
 #define CFG_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CFG_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CFG_HZ			1000
+#define CFG_DAVINCI_PINMUX_0	0x00000c1f

include/configs/davinci_sonata.h line 73

Quoted 10 lines

include/configs/davinci_sonata.h +10 -0

+#define CFG_DAVINCI_WAITCFG	0x00000000
+#define CFG_DAVINCI_ACFG2	0x3ffffffd	/* CE configs */
+#define CFG_DAVINCI_ACFG3	0x3ffffffd
+#define CFG_DAVINCI_ACFG4	0x3ffffffd
+#define CFG_DAVINCI_ACFG5	0x3ffffffd
+#undef  CFG_DAVINCI_NANDCE			/* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL	0x50006405	/* DDR timing config */
+#define CFG_DAVINCI_SDREF	0x000005c3
+#define CFG_DAVINCI_SDCFG	0x00178632	/* 8 banks */
+/*#define CFG_DAVINCI_SDCFG	0x00178622*/	/* 4 banks */

if no need please remove it

include/configs/davinci_sonata.h line 75

Quoted 2 lines

include/configs/davinci_sonata.h +2 -0

+#define CFG_DAVINCI_SDTIM0	0x28923211
+#define CFG_DAVINCI_SDTIM1	0x0016c722

NB : please do not send patch as attechement

Best Regards,
J.

Wolfgang Denk

2008-03-25 12:37 UTC #3 lore raw

PATCH 1/1 DM644x: (2nd try) This patch removes all boardspecific code from the arch. part for DM644x (DaVinci) boards

Quoted 4 lines · In message <[email protected]> you…

cpu/arm926ejs/davinci/lowlevel_init.S line 12

Quoted 10 lines

cpu/arm926ejs/davinci/lowlevel_init.S +5 -0

@@ -3,6 +3,11 @@
  *
  * Copyright (C) 2007 Sergey Kubushyn <[email protected]>
  *
+ * Copyright (C) 2008 Prodrive BV <[email protected]>
+ * Changed:
+ * Made board specific defines such as DDR timing and PLL
+ * dividers. These should be set in the board config file
+ *
  * Partially based on TI sources, original copyrights follow:
  */

Please don't add changelog information to source code.

Quoted 4 lines

cpu/arm926ejs/davinci/nand.c +0 -0
index 127be9f..3257f83 100644

...

cpu/arm926ejs/davinci/nand.c static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, i · line 316

Quoted 3 lines

cpu/arm926ejs/davinci/nand.c +3 -0

+	/* All EMIF initialization is done in lowlevel_init.S
+	 * and config values are in the board config files
+	 */

This is not the correct style for multi-line comments. The "/*" goes on a line for it's own.

include/configs/davinci_dvevm.h line 57

Quoted 11 lines

include/configs/davinci_dvevm.h +3 -0

index 8ecd059..5557723 100644
@@ -52,6 +52,9 @@
 #define DV_EVM
 #define CFG_NAND_SMALLPAGE
 #define CFG_USE_NOR
+#define CFG_USE_INTEL_NOR	/* Define this when your DVEVM has Intel
+				 * flash instead of AMD flash
+				 */

Ditto.

J. has commented on this before!!!

Quoted 6 lines

include/configs/davinci_dvevm.h +0 -1
-----Original Message-----
From: Jean-Christophe PLAGNIOL-VILLARD [mailto:plagnioj at jcrosoft.com]
Sent: zaterdag 22 maart 2008 14:23
To: Pieter Voorthuijsen
Cc: u-boot-users at lists.sourceforge.net
Subject: Re: [PATCH] DM644x: (2nd try) This patch removes all boardspecific code from the arch. part for DM644x (DaVinci) boards

And PLEASE - never top post full quote!!!!

Especially not when including patches!!!

Best regards,

Wolfgang Denk

Signature · 8 lines

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
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