ARM: rockchip: add smp functionality

The Rockchip SoCs need a special part of their sram for bringup of additional cores. Therefore the mapped area should be split into a special area for the smp code and a generic area that gets handled by mmio-sram.

Signed-off-by Heiko Stuebner <[email protected]>

---
 .../devicetree/bindings/arm/rockchip/smp-sram.txt  |   29 ++++++++++++++++++++
 arch/arm/boot/dts/rk3066a.dtsi                     |   14 ++++++++++
 2 files changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file +18 -0

new file mode 100644
index 0000000..9c81fac
@@ -0,0 +1,29 @@
+Rockchip SRAM for smp bringup:
+------------------------------
+
+Rockchip smp-capable SoCs use the first part of the sram for the bringup
+of the cores. Once the core gets powered up it executes the code that is
+residing at the very beginning of the sram.
+
+While the suspend also needs to have code in the sram that can be realized
+with the generic mmio-sram driver and only the smp specific part needs to
+be mapped specially in the smp code.
+
+Therefore split the sram mapping in a smp-specific part that gets used
+by the smp code exclusively and a bigger generic part for mmio-sram
+
+Required node properties:
+- compatible value : = "rockchip,rk3066-smp-sram";
+- reg : physical base address and the size of the registers window
+

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file +1 -0

+	};

arch/arm/boot/dts/rk3066a.dtsi +14 -0

index 26c4311..44eabd2 100644
@@ -53,6 +53,20 @@
 			reg = <0x1013c000 0x100>;
 		};
 
+		/*
+		 * the first part of the sram is needed for the smp
+		 * trampoline code during cpu bringup
+		 */
+		sram at 10080000 {
+			compatible = "rockchip,rk3066-smp-sram";
+			reg = <0x10080000 0x100>;
+		};
+
+		sram: sram at 10080100 {
+			compatible = "mmio-sram";
+			reg = <0x10080100 0x9900>;
+		};
+
 		gic: interrupt-controller at 1013d000 {
 			compatible = "arm,cortex-a9-gic";
 			interrupt-controller;

Quoted 39 lines

The Rockchip SoCs need a special part of their sram for bringup of additional cores. Therefore the mapped area should be split into a special area for the smp code and a generic area that gets handled by mmio-sram.

Signed-off-by Heiko Stuebner <[email protected]>

---

 .../devicetree/bindings/arm/rockchip/smp-sram.txt  |   29
 ++++++++++++++++++++ arch/arm/boot/dts/rk3066a.dtsi                    
 |   14 ++++++++++ 2 files changed, 43 insertions(+)
 create mode 100644

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt

(quoted diff) +0 -0

b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file mode 100644
index 0000000..9c81fac

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file +8 -0

@@ -0,0 +1,29 @@
+Rockchip SRAM for smp bringup:
+------------------------------
+
+Rockchip smp-capable SoCs use the first part of the sram for the bringup
+of the cores. Once the core gets powered up it executes the code that is
+residing at the very beginning of the sram.
+
+While the suspend also needs to have code in the sram that can be

realized +with the generic mmio-sram driver and only the smp specific part needs to +be mapped specially in the smp code.

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file +8 -0

+
+Therefore split the sram mapping in a smp-specific part that gets used
+by the smp code exclusively and a bigger generic part for mmio-sram
+
+Required node properties:
+- compatible value : = "rockchip,rk3066-smp-sram";
+- reg : physical base address and the size of the registers window
+

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt line 28

Quoted 10 lines

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file +10 -0

+Example:
+
+	sram at 10080000 {
+		compatible = "rockchip,rk3066-smp-sram";
+		reg = <0x10080000 0x100>;
+	};
+
+	sram: sram at 10080100 {
+		compatible = "mmio-sram";
+		reg = <0x10080100 0x9900>;

I think a better way would be to specify some portion of the sram as reserved rather than defining the s/w use of the sram in DT. Something like this:

mmio-sram-reserved = <base size base size>;

where base values are relative to reg property base.

Quoted 30 lines

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file +1 -0

+	};

(quoted diff) +0 -0

b/arch/arm/boot/dts/rk3066a.dtsi index 26c4311..44eabd2 100644

arch/arm/boot/dts/rk3066a.dtsi +14 -0

@@ -53,6 +53,20 @@
 
 			reg = <0x1013c000 0x100>;
 
 		};
 
+		/*
+		 * the first part of the sram is needed for the smp
+		 * trampoline code during cpu bringup
+		 */
+		sram at 10080000 {
+			compatible = "rockchip,rk3066-smp-sram";
+			reg = <0x10080000 0x100>;
+		};
+
+		sram: sram at 10080100 {
+			compatible = "mmio-sram";
+			reg = <0x10080100 0x9900>;
+		};
+
 

arch/arm/boot/dts/rk3066a.dtsi +0 -0

 		gic: interrupt-controller at 1013d000 {
 
 			compatible = "arm,cortex-a9-gic";
 			interrupt-controller;

Am Dienstag, 18. Juni 2013, 01:41:27 schrieb Rob Herring:

Quoted 55 lines · Heiko St?bner

Quoted 39 lines

The Rockchip SoCs need a special part of their sram for bringup of additional cores. Therefore the mapped area should be split into a special area for the smp code and a generic area that gets handled by mmio-sram.

Signed-off-by Heiko Stuebner <[email protected]>

---

 .../devicetree/bindings/arm/rockchip/smp-sram.txt  |   29
 ++++++++++++++++++++ arch/arm/boot/dts/rk3066a.dtsi                    
 |   14 ++++++++++ 2 files changed, 43 insertions(+)
 create mode 100644

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt

(quoted diff) +0 -0

b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file mode 100644
index 0000000..9c81fac

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file +8 -0

@@ -0,0 +1,29 @@
+Rockchip SRAM for smp bringup:
+------------------------------
+
+Rockchip smp-capable SoCs use the first part of the sram for the bringup
+of the cores. Once the core gets powered up it executes the code that is
+residing at the very beginning of the sram.
+
+While the suspend also needs to have code in the sram that can be

realized +with the generic mmio-sram driver and only the smp specific part needs to +be mapped specially in the smp code.

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file +8 -0

+
+Therefore split the sram mapping in a smp-specific part that gets used
+by the smp code exclusively and a bigger generic part for mmio-sram
+
+Required node properties:
+- compatible value : = "rockchip,rk3066-smp-sram";
+- reg : physical base address and the size of the registers window
+

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt line 28

Quoted 10 lines

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file +10 -0

+Example:
+
+	sram at 10080000 {
+		compatible = "rockchip,rk3066-smp-sram";
+		reg = <0x10080000 0x100>;
+	};
+
+	sram: sram at 10080100 {
+		compatible = "mmio-sram";
+		reg = <0x10080100 0x9900>;

I think a better way would be to specify some portion of the sram as reserved rather than defining the s/w use of the sram in DT. Something like this:

Quoted 3 lines

mmio-sram-reserved = <base size base size>;

where base values are relative to reg property base.

hmm, but I don't see how to get then access to the reserved part. As can be seen in patch 4 [which I've forgotton to cc you in, sorry] the smp-trampoline gets copied into this area for the core to execute after poweron, so I need to get the mapped representation of the reserved area.

Or do you mean

- let mmio-sram only allocate the non-reserved spaces for itself
- grab mmio-sram node in the smp code and map the necessary reserved space

This might actually work.

Thanks
Heiko

Quoted 30 lines

Quoted 30 lines

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file +1 -0

+	};

(quoted diff) +0 -0

b/arch/arm/boot/dts/rk3066a.dtsi index 26c4311..44eabd2 100644

arch/arm/boot/dts/rk3066a.dtsi +14 -0

@@ -53,6 +53,20 @@
 
 			reg = <0x1013c000 0x100>;
 
 		};
 
+		/*
+		 * the first part of the sram is needed for the smp
+		 * trampoline code during cpu bringup
+		 */
+		sram at 10080000 {
+			compatible = "rockchip,rk3066-smp-sram";
+			reg = <0x10080000 0x100>;
+		};
+
+		sram: sram at 10080100 {
+			compatible = "mmio-sram";
+			reg = <0x10080100 0x9900>;
+		};
+
 

arch/arm/boot/dts/rk3066a.dtsi +0 -0

 		gic: interrupt-controller at 1013d000 {
 
 			compatible = "arm,cortex-a9-gic";
 			interrupt-controller;

Quoted 61 lines

Am Dienstag, 18. Juni 2013, 01:41:27 schrieb Rob Herring:

Quoted 60 lines · Heiko St?bner

Quoted 42 lines

The Rockchip SoCs need a special part of their sram for bringup of additional cores. Therefore the mapped area should be split into a special area for the smp code and a generic area that gets handled by mmio-sram.

Signed-off-by Heiko Stuebner <[email protected]>

---

 .../devicetree/bindings/arm/rockchip/smp-sram.txt  |   29

++++++++++++++++++++ arch/arm/boot/dts/rk3066a.dtsi

| 14 ++++++++++ 2 files changed, 43 insertions(+)

 create mode 100644

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt

diff --git a/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file mode 100644
index 0000000..9c81fac

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file +4 -0

@@ -0,0 +1,29 @@
+Rockchip SRAM for smp bringup:
+------------------------------
+
+Rockchip smp-capable SoCs use the first part of the sram for the

bringup +of the cores. Once the core gets powered up it executes the code that is +residing at the very beginning of the sram.

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file +2 -0

+
+While the suspend also needs to have code in the sram that can be

realized +with the generic mmio-sram driver and only the smp specific part needs to +be mapped specially in the smp code.

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file +8 -0

+
+Therefore split the sram mapping in a smp-specific part that gets used
+by the smp code exclusively and a bigger generic part for mmio-sram
+
+Required node properties:
+- compatible value : = "rockchip,rk3066-smp-sram";
+- reg : physical base address and the size of the registers window
+

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt line 28

Quoted 10 lines

Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file +10 -0

+Example:
+
+	sram at 10080000 {
+		compatible = "rockchip,rk3066-smp-sram";
+		reg = <0x10080000 0x100>;
+	};
+
+	sram: sram at 10080100 {
+		compatible = "mmio-sram";
+		reg = <0x10080100 0x9900>;

I think a better way would be to specify some portion of the sram as reserved rather than defining the s/w use of the sram in DT. Something like this:

mmio-sram-reserved = <base size base size>;

Quoted 7 lines

Quoted 1 line

where base values are relative to reg property base.

hmm, but I don't see how to get then access to the reserved part. As can be seen in patch 4 [which I've forgotton to cc you in, sorry] the smp-trampoline gets copied into this area for the core to execute after poweron, so I need to get the mapped representation of the reserved area.

That's helpful to know.

Quoted 5 lines

Or do you mean

- let mmio-sram only allocate the non-reserved spaces for itself
- grab mmio-sram node in the smp code and map the necessary reserved space

That would work. Another alternative would be having a way in the kernel to reserve a specific region of sram.

If you have to know what to put in the sram and are putting that into the kernel, then having to know where to put it is not really much more kernel data. So I don't really see the point to put a "smp boot" area into device tree.

Seems like we're getting several platforms that are putting all their secondary core boot code into the kernel. I'm not sure this is something we want in the kernel. We may need to define the boot protocol for secondary cores just like the boot core and start pushing this into bootloaders.