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mx7sabresd: Set VLD04 output to 2.8V in PMIC initialization.

PATCH Superseded Gautam Bhat 3 participants 7 messages Jul 1, 2017 – Jul 5, 2017

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#0 lore raw

v2 cover mx7sabresd: Set VLD04 output to 2.8V in PMIC initialization.

This change sets the VLDO4 settings output to 2.8V in PMIC initialization. I accidentally noticed this when I was testing the DSI voltage input which was 3.3V. Not setting the proper voltage can harm some of the voltage sensitive peripheral.

Changes in v2:
- Removed extra parentheses for 0xF.
- Modified subject and commit messages as per the recommendation.

Gautam Bhat (1):
Set VLD04 output to 2.8V in PMIC initialization.

 board/freescale/mx7dsabresd/mx7dsabresd.c | 10 ++++++++++
 1 file changed, 10 insertions(+)
Signature · 1 line
2.11.0
#1 lore raw

PATCH v2 1/1 mx7sabresd: Set VLD04 output to 2.8V in PMIC initialization.

This change sets the VLDO4 settings output to 2.8V in PMIC initialization so that the MIPI DSI/CSI input voltage is 2.8V as per the schematics. The original code provides an output of 3.3V which violates the voltage mentioned in the schematics.

---

Changes in v2:
- Removed extra parentheses for 0xF.
- Modified subject and commit messages as per the recommendation.

 board/freescale/mx7dsabresd/mx7dsabresd.c | 10 ++++++++++
 1 file changed, 10 insertions(+)
board/freescale/mx7dsabresd/mx7dsabresd.c +10 -0
index ecea5a529a..c9ff2d8e40 100644
@@ -341,6 +341,7 @@ int power_init_board(void)
 {
 	struct udevice *dev;
 	int ret, dev_id, rev_id;
+	uint regval;
 
 	ret = pmic_get("pfuze3000", &dev);
 	if (ret == -ENODEV)
@@ -354,6 +355,15 @@ int power_init_board(void)
 
 	pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
 
+	/*
+	 * Set the voltage of VLDO4 output to 2.8V which feeds
+	 * the MIPI DSI and MIPI CSI inputs.
+	 */
+	regval = pmic_reg_read(dev, PFUZE3000_VLD4CTL);
+	regval &= ~0xF;
+	regval |= 0xA; /* Set to 2.8V */
+	pmic_reg_write(dev, PFUZE3000_VLD4CTL, regval);
+
 	return 0;
 }
 #endif
Signature · 1 line
2.11.0
#2 lore raw

PATCH v2 1/1 mx7sabresd: Set VLD04 output to 2.8V in PMIC initialization.

Hi Gautam,

Quoted 6 lines · Gautam Bhat

This change sets the VLDO4 settings output to 2.8V in PMIC initialization so that the MIPI DSI/CSI input voltage is 2.8V as per the schematics. The original code provides an output of 3.3V which violates the voltage mentioned in the schematics.

Please don't add an Acked-by unless you explicitly received it.

Quoted 15 lines

---

Changes in v2:
- Removed extra parentheses for 0xF.
- Modified subject and commit messages as per the recommendation.

 board/freescale/mx7dsabresd/mx7dsabresd.c | 10 ++++++++++
 1 file changed, 10 insertions(+)
board/freescale/mx7dsabresd/mx7dsabresd.c +0 -0
index ecea5a529a..c9ff2d8e40 100644

board/freescale/mx7dsabresd/mx7dsabresd.c int power_init_board(void) · line 344

Quoted 4 lines
board/freescale/mx7dsabresd/mx7dsabresd.c +1 -0
@@ -341,6 +341,7 @@ int power_init_board(void)
 {
        struct udevice *dev;
        int ret, dev_id, rev_id;
+       uint regval;

unsigned int regval;

to make it consistent with other usage in this file.

Quoted 5 lines
board/freescale/mx7dsabresd/mx7dsabresd.c +0 -0
        ret = pmic_get("pfuze3000", &dev);
        if (ret == -ENODEV)
@@ -354,6 +355,15 @@ int power_init_board(void)
 

board/freescale/mx7dsabresd/mx7dsabresd.c int power_init_board(void) · line 365

Quoted 10 lines
board/freescale/mx7dsabresd/mx7dsabresd.c +8 -0
        pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
 
+       /*
+        * Set the voltage of VLDO4 output to 2.8V which feeds
+        * the MIPI DSI and MIPI CSI inputs.
+        */
+       regval = pmic_reg_read(dev, PFUZE3000_VLD4CTL);
+       regval &= ~0xF;
+       regval |= 0xA; /* Set to 2.8V */
+       pmic_reg_write(dev, PFUZE3000_VLD4CTL, regval);

Please use pmic_clrsetbits for consistency.

Thanks

#3 lore raw

v3 cover mx7dsabresd: Set VLD04 output to 2.8V in PMIC initialization.

This change sets the VLDO4 settings output to 2.8V in PMIC initialization. I accidentally noticed this when I was testing the DSI voltage input which was 3.3V. Not setting the proper voltage can harm some of the voltage sensitive peripheral.

Changes in v3:
- Used pmic_clrsetbits for consistency.

Gautam Bhat (1):
Set VLD04 output to 2.8V in PMIC initialization.

 board/freescale/mx7dsabresd/mx7dsabresd.c | 6 ++++++
 1 file changed, 6 insertions(+)
Signature · 1 line
2.11.0
#4 lore raw

PATCH v3 1/1 mx7dsabresd: Set VLD04 output to 2.8V in PMIC initialization.

This change sets the VLDO4 settings output to 2.8V in PMIC initialization so that the MIPI DSI/CSI input voltage is 2.8V as per the schematics. The original code provides an output of 3.3V which violates the voltage mentioned in the schematics.

---

Changes in v3:
- Used pmic_clrsetbits for consistency.

 board/freescale/mx7dsabresd/mx7dsabresd.c | 6 ++++++
 1 file changed, 6 insertions(+)
board/freescale/mx7dsabresd/mx7dsabresd.c +6 -0
index ecea5a529a..7d22501d26 100644
@@ -354,6 +354,12 @@ int power_init_board(void)
 
 	pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
 
+	/*
+	 * Set the voltage of VLDO4 output to 2.8V which feeds
+	 * the MIPI DSI and MIPI CSI inputs.
+	 */
+	pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA);
+
 	return 0;
 }
 #endif
Signature · 1 line
2.11.0
#5 lore raw

PATCH v3 1/1 mx7dsabresd: Set VLD04 output to 2.8V in PMIC initialization.

Quoted 6 lines · Gautam Bhat

This change sets the VLDO4 settings output to 2.8V in PMIC initialization so that the MIPI DSI/CSI input voltage is 2.8V as per the schematics. The original code provides an output of 3.3V which violates the voltage mentioned in the schematics.

#6 lore raw

PATCH v3 1/1 mx7dsabresd: Set VLD04 output to 2.8V in PMIC initialization.

Quoted 10 lines · Fabio Estevam
Quoted 6 lines · Gautam Bhat

This change sets the VLDO4 settings output to 2.8V in PMIC initialization so that the MIPI DSI/CSI input voltage is 2.8V as per the schematics. The original code provides an output of 3.3V which violates the voltage mentioned in the schematics.

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

Signature · 5 lines
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