NVIDIA Tegra AHB DMA controller driver

AHB DMA presents on Tegra20/30. Add missing entries, so that driver for AHB DMA could be implemented.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/clk/tegra/clk-id.h           | 1 +
 drivers/clk/tegra/clk-tegra-periph.c | 1 +
 drivers/clk/tegra/clk-tegra20.c      | 6 ++++++
 drivers/clk/tegra/clk-tegra30.c      | 2 ++
 4 files changed, 10 insertions(+)

drivers/clk/tegra/clk-id.h +1 -0

index 689f344377a7..c1661b47bbda 100644
@@ -12,6 +12,7 @@ enum clk_id {
 	tegra_clk_amx,
 	tegra_clk_amx1,
 	tegra_clk_apb2ape,
+	tegra_clk_ahbdma,
 	tegra_clk_apbdma,
 	tegra_clk_apbif,
 	tegra_clk_ape,

drivers/clk/tegra/clk-tegra-periph.c +0 -0

index 848255cc0209..95a3d8c95f06 100644

Quoted 26 lines · Dmitry Osipenko

AHB DMA presents on Tegra20/30. Add missing entries, so that driver for AHB DMA could be implemented.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/clk/tegra/clk-id.h           | 1 +
 drivers/clk/tegra/clk-tegra-periph.c | 1 +
 drivers/clk/tegra/clk-tegra20.c      | 6 ++++++
 drivers/clk/tegra/clk-tegra30.c      | 2 ++
 4 files changed, 10 insertions(+)

drivers/clk/tegra/clk-id.h +1 -0

index 689f344377a7..c1661b47bbda 100644
@@ -12,6 +12,7 @@ enum clk_id {
 	tegra_clk_amx,
 	tegra_clk_amx1,
 	tegra_clk_apb2ape,
+	tegra_clk_ahbdma,
 	tegra_clk_apbdma,
 	tegra_clk_apbif,
 	tegra_clk_ape,

drivers/clk/tegra/clk-tegra-periph.c +0 -1

index 848255cc0209..95a3d8c95f06 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c

drivers/clk/tegra/clk-tegra-periph.c static struct tegra_periph_init_data gate_clks[] = { · line 826

Quoted 6 lines

+++ b/drivers/clk/tegra/clk-tegra-periph.c

drivers/clk/tegra/clk-tegra-periph.c +1 -0

@@ -823,6 +823,7 @@ static struct tegra_periph_init_data gate_clks[] = {
 	GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
 	GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
 	GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
+	GATE("ahbdma", "clk_m", 33, 0, tegra_clk_ahbdma, 0),

Parent for this should be hclk on Tegra30 and later chips as well..

Quoted 6 lines

drivers/clk/tegra/clk-tegra-periph.c +0 -0

 	GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
 	GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
 	GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),

drivers/clk/tegra/clk-tegra20.c +0 -1

index 837e5cbd60e9..e76c0d292ca7 100644
--- a/drivers/clk/tegra/clk-tegra20.c

drivers/clk/tegra/clk-tegra20.c static struct tegra_devclk devclks[] __initdata = { · line 452

Quoted 6 lines

+++ b/drivers/clk/tegra/clk-tegra20.c

drivers/clk/tegra/clk-tegra20.c +1 -0

@@ -449,6 +449,7 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },
 	{ .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },
 	{ .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
+	{ .dev_id = "tegra-ahbdma", .dt_id = TEGRA20_CLK_AHBDMA },

This isn't needed if you use DT bindings to get the clock handle.

Quoted 7 lines

drivers/clk/tegra/clk-tegra20.c +0 -0

 	{ .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
 	{ .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
 	{ .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER },

@@ -806,6 +807,11 @@ static void __init tegra20_periph_clk_init(void)
 				    clk_base, 0, 3, periph_clk_enb_refcnt);
 	clks[TEGRA20_CLK_AC97] = clk;
 

drivers/clk/tegra/clk-tegra20.c static void __init tegra20_periph_clk_init(void) · line 814

Quoted 5 lines

drivers/clk/tegra/clk-tegra20.c +5 -0

+	/* ahbdma */
+	clk = tegra_clk_register_periph_gate("ahbdma", "hclk", 0, clk_base,
+				    0, 33, periph_clk_enb_refcnt);
+	clks[TEGRA20_CLK_AHBDMA] = clk;
+

You can use the generic definition here if you correct the entry above.

drivers/clk/tegra/clk-tegra30.c static struct tegra_devclk devclks[] __initdata = { · line 615

Quoted 12 lines

drivers/clk/tegra/clk-tegra20.c +0 -0

 	/* apbdma */
 	clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
 				    0, 34, periph_clk_enb_refcnt);

drivers/clk/tegra/clk-tegra30.c +1 -0

index a2d163f759b4..e99701557f29 100644
@@ -612,6 +612,7 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
 	{ .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
 	{ .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
+	{ .dev_id = "tegra-ahbdma", .dt_id = TEGRA30_CLK_AHBDMA },

Same as for Tegra20.

drivers/clk/tegra/clk-tegra30.c static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = { · line 795

Quoted 11 lines

drivers/clk/tegra/clk-tegra30.c +1 -0

 	{ .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
 	{ .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
 	{ .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },

@@ -788,6 +789,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
 	[tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
 	[tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
+	[tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true },
 	[tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
 	[tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
 	[tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },

Cheers,

Peter.

Quoted 27 lines · Peter De Schrijver

Quoted 26 lines · Dmitry Osipenko

AHB DMA presents on Tegra20/30. Add missing entries, so that driver for AHB DMA could be implemented.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/clk/tegra/clk-id.h           | 1 +
 drivers/clk/tegra/clk-tegra-periph.c | 1 +
 drivers/clk/tegra/clk-tegra20.c      | 6 ++++++
 drivers/clk/tegra/clk-tegra30.c      | 2 ++
 4 files changed, 10 insertions(+)

drivers/clk/tegra/clk-id.h +1 -0

index 689f344377a7..c1661b47bbda 100644
@@ -12,6 +12,7 @@ enum clk_id {
 	tegra_clk_amx,
 	tegra_clk_amx1,
 	tegra_clk_apb2ape,
+	tegra_clk_ahbdma,
 	tegra_clk_apbdma,
 	tegra_clk_apbif,
 	tegra_clk_ape,

drivers/clk/tegra/clk-tegra-periph.c +0 -1

index 848255cc0209..95a3d8c95f06 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c

Quoted 9 lines

drivers/clk/tegra/clk-tegra-periph.c static struct tegra_periph_init_data gate_clks[] = { · line 826

Quoted 6 lines

+++ b/drivers/clk/tegra/clk-tegra-periph.c

drivers/clk/tegra/clk-tegra-periph.c +1 -0

@@ -823,6 +823,7 @@ static struct tegra_periph_init_data gate_clks[] = {
 	GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
 	GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
 	GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
+	GATE("ahbdma", "clk_m", 33, 0, tegra_clk_ahbdma, 0),

Parent for this should be hclk on Tegra30 and later chips as well..

It looks like other clocks have a wrong parent too here, aren't they? Like for example "apbdma" should have "pclk" as a parent, isn't it?

Quoted 6 lines

Quoted 6 lines

drivers/clk/tegra/clk-tegra-periph.c +0 -0

 	GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
 	GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
 	GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),

drivers/clk/tegra/clk-tegra20.c +0 -1

index 837e5cbd60e9..e76c0d292ca7 100644
--- a/drivers/clk/tegra/clk-tegra20.c

Quoted 9 lines

drivers/clk/tegra/clk-tegra20.c static struct tegra_devclk devclks[] __initdata = { · line 452

Quoted 6 lines

+++ b/drivers/clk/tegra/clk-tegra20.c

drivers/clk/tegra/clk-tegra20.c +1 -0

@@ -449,6 +449,7 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },
 	{ .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },
 	{ .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
+	{ .dev_id = "tegra-ahbdma", .dt_id = TEGRA20_CLK_AHBDMA },

This isn't needed if you use DT bindings to get the clock handle.

Yes, I added it for consistency. Shouldn't we get rid of that all legacy stuff already?

Quoted 7 lines

Quoted 7 lines

drivers/clk/tegra/clk-tegra20.c +0 -0

 	{ .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
 	{ .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
 	{ .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER },

@@ -806,6 +807,11 @@ static void __init tegra20_periph_clk_init(void)
 				    clk_base, 0, 3, periph_clk_enb_refcnt);
 	clks[TEGRA20_CLK_AC97] = clk;
 

Quoted 8 lines

drivers/clk/tegra/clk-tegra20.c static void __init tegra20_periph_clk_init(void) · line 814

Quoted 5 lines

drivers/clk/tegra/clk-tegra20.c +5 -0

+	/* ahbdma */
+	clk = tegra_clk_register_periph_gate("ahbdma", "hclk", 0, clk_base,
+				    0, 33, periph_clk_enb_refcnt);
+	clks[TEGRA20_CLK_AHBDMA] = clk;
+

You can use the generic definition here if you correct the entry above.

Good point, same applies to "apbdma". Thank you for the suggestion.

Quoted 38 lines · Dmitry Osipenko

Quoted 36 lines · Peter De Schrijver

Quoted 28 lines · Dmitry Osipenko

AHB DMA presents on Tegra20/30. Add missing entries, so that driver for AHB DMA could be implemented.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/clk/tegra/clk-id.h           | 1 +
 drivers/clk/tegra/clk-tegra-periph.c | 1 +
 drivers/clk/tegra/clk-tegra20.c      | 6 ++++++
 drivers/clk/tegra/clk-tegra30.c      | 2 ++
 4 files changed, 10 insertions(+)

drivers/clk/tegra/clk-id.h +1 -0

index 689f344377a7..c1661b47bbda 100644
@@ -12,6 +12,7 @@ enum clk_id {
 	tegra_clk_amx,
 	tegra_clk_amx1,
 	tegra_clk_apb2ape,
+	tegra_clk_ahbdma,
 	tegra_clk_apbdma,
 	tegra_clk_apbif,
 	tegra_clk_ape,

drivers/clk/tegra/clk-tegra-periph.c +0 -0

index 848255cc0209..95a3d8c95f06 100644

drivers/clk/tegra/clk-tegra-periph.c static struct tegra_periph_init_data gate_clks[] = { · line 826

Quoted 4 lines

drivers/clk/tegra/clk-tegra-periph.c +1 -0

@@ -823,6 +823,7 @@ static struct tegra_periph_init_data gate_clks[] = {
 	GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
 	GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
 	GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
+	GATE("ahbdma", "clk_m", 33, 0, tegra_clk_ahbdma, 0),

Parent for this should be hclk on Tegra30 and later chips as well..

Quoted 3 lines

It looks like other clocks have a wrong parent too here, aren't they? Like for example "apbdma" should have "pclk" as a parent, isn't it?

Yes. That is correct.

Quoted 16 lines

Quoted 15 lines

drivers/clk/tegra/clk-tegra20.c static struct tegra_devclk devclks[] __initdata = { · line 452

Quoted 12 lines

drivers/clk/tegra/clk-tegra-periph.c +0 -0

 	GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
 	GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
 	GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),

drivers/clk/tegra/clk-tegra20.c +1 -0

index 837e5cbd60e9..e76c0d292ca7 100644
@@ -449,6 +449,7 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },
 	{ .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },
 	{ .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
+	{ .dev_id = "tegra-ahbdma", .dt_id = TEGRA20_CLK_AHBDMA },

This isn't needed if you use DT bindings to get the clock handle.

Quoted 3 lines

Yes, I added it for consistency. Shouldn't we get rid of that all legacy stuff already?

We probably should, but we can start by not adding more :)

Quoted 16 lines

Quoted 7 lines

Quoted 7 lines

drivers/clk/tegra/clk-tegra20.c +0 -0

 	{ .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
 	{ .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
 	{ .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER },

@@ -806,6 +807,11 @@ static void __init tegra20_periph_clk_init(void)
 				    clk_base, 0, 3, periph_clk_enb_refcnt);
 	clks[TEGRA20_CLK_AC97] = clk;
 

Quoted 8 lines

drivers/clk/tegra/clk-tegra20.c static void __init tegra20_periph_clk_init(void) · line 814

Quoted 5 lines

drivers/clk/tegra/clk-tegra20.c +5 -0

+	/* ahbdma */
+	clk = tegra_clk_register_periph_gate("ahbdma", "hclk", 0, clk_base,
+				    0, 33, periph_clk_enb_refcnt);
+	clks[TEGRA20_CLK_AHBDMA] = clk;
+

You can use the generic definition here if you correct the entry above.

Quoted 2 lines

Good point, same applies to "apbdma". Thank you for the suggestion.

Indeed.

AHB DMA is a running on 1/2 of SCLK rate, APB on 1/4. Increasing SCLK rate results in an increased DMA transfer rate.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/clk/tegra/clk-tegra20.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/clk/tegra/clk-tegra20.c +1 -1

index e76c0d292ca7..c511716093e2 100644
@@ -1031,7 +1031,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
 	{ TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
 	{ TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1 },
-	{ TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1 },
+	{ TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
 	{ TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1 },
 	{ TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1 },

Signature · 1 line

2.14.1

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +2 -0

new file mode 100644
index 000000000000..2af9aa76ae11
@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+

Quoted 21 lines · Dmitry Osipenko

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

new file mode 100644
index 000000000000..2af9aa76ae11
@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:	Must be "nvidia,tegra20-ahbdma"
+- reg:		Should contain registers base address and length.
+- interrupts:	Should contain one entry, DMA controller interrupt.

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt line 12

Quoted 6 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

+- clocks:	Should contain one entry, DMA controller clock.
+- resets :	Should contain one entry, DMA controller reset.
+- #dma-cells:	Should be <1>. The cell represents DMA request select value
+		for the peripheral. For more details consult the Tegra TRM's
+		documentation, in particular AHB DMA channel control register
+		REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as well?

Quoted 21 lines · Dmitry Osipenko

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

new file mode 100644
index 000000000000..2af9aa76ae11
@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:	Must be "nvidia,tegra20-ahbdma"
+- reg:		Should contain registers base address and length.
+- interrupts:	Should contain one entry, DMA controller interrupt.

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt line 12

Quoted 6 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

+- clocks:	Should contain one entry, DMA controller clock.
+- resets :	Should contain one entry, DMA controller reset.
+- #dma-cells:	Should be <1>. The cell represents DMA request select value
+		for the peripheral. For more details consult the Tegra TRM's
+		documentation, in particular AHB DMA channel control register
+		REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as well?

Quoted 23 lines · Jon Hunter

Quoted 21 lines · Dmitry Osipenko

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

new file mode 100644
index 000000000000..2af9aa76ae11
@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:	Must be "nvidia,tegra20-ahbdma"
+- reg:		Should contain registers base address and length.
+- interrupts:	Should contain one entry, DMA controller interrupt.

Quoted 9 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt line 12

Quoted 6 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

+- clocks:	Should contain one entry, DMA controller clock.
+- resets :	Should contain one entry, DMA controller reset.
+- #dma-cells:	Should be <1>. The cell represents DMA request select value
+		for the peripheral. For more details consult the Tegra TRM's
+		documentation, in particular AHB DMA channel control register
+		REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as well?

Actually, DMA transfer trigger isn't related a hardware description. It's up to software to decide what trigger to select. So it shouldn't be in the binding.

And I think the same applies to requester... any objections?

Quoted 34 lines · Dmitry Osipenko

Quoted 32 lines · Jon Hunter

Quoted 17 lines · Dmitry Osipenko

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +2 -0

new file mode 100644
index 000000000000..2af9aa76ae11
@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt line 12

Quoted 10 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +10 -0

+Required properties:
+- compatible:	Must be "nvidia,tegra20-ahbdma"
+- reg:		Should contain registers base address and length.
+- interrupts:	Should contain one entry, DMA controller interrupt.
+- clocks:	Should contain one entry, DMA controller clock.
+- resets :	Should contain one entry, DMA controller reset.
+- #dma-cells:	Should be <1>. The cell represents DMA request select value
+		for the peripheral. For more details consult the Tegra TRM's
+		documentation, in particular AHB DMA channel control register
+		REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as well?

Quoted 2 lines

Actually, DMA transfer trigger isn't related a hardware description. It's up to software to decide what trigger to select. So it shouldn't be in the binding.

I think it could be, if say a board wanted a GPIO to trigger a transfer.

Quoted 1 line

And I think the same applies to requester... any objections?

Well, the REQ_SEL should definitely be in the binding.

Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks like we never bothered with it for the APB DMA and so maybe no ones uses this.

Quoted 36 lines · Jon Hunter

Quoted 34 lines · Dmitry Osipenko

Quoted 32 lines · Jon Hunter

Quoted 17 lines · Dmitry Osipenko

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +2 -0

new file mode 100644
index 000000000000..2af9aa76ae11
@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt line 12

Quoted 10 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +10 -0

+Required properties:
+- compatible:	Must be "nvidia,tegra20-ahbdma"
+- reg:		Should contain registers base address and length.
+- interrupts:	Should contain one entry, DMA controller interrupt.
+- clocks:	Should contain one entry, DMA controller clock.
+- resets :	Should contain one entry, DMA controller reset.
+- #dma-cells:	Should be <1>. The cell represents DMA request select value
+		for the peripheral. For more details consult the Tegra TRM's
+		documentation, in particular AHB DMA channel control register
+		REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as well?

Quoted 5 lines

Quoted 2 lines

Actually, DMA transfer trigger isn't related a hardware description. It's up to software to decide what trigger to select. So it shouldn't be in the binding.

I think it could be, if say a board wanted a GPIO to trigger a transfer.

GPIO isn't a very good example, there is no "GPIO" trigger. To me all triggers are software-defined, so that software could create transfer chains.

Quoted 43 lines · Dmitry Osipenko

Quoted 41 lines · Jon Hunter

Quoted 34 lines · Dmitry Osipenko

Quoted 23 lines · Jon Hunter

Quoted 21 lines · Dmitry Osipenko

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

new file mode 100644
index 000000000000..2af9aa76ae11
@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:	Must be "nvidia,tegra20-ahbdma"
+- reg:		Should contain registers base address and length.
+- interrupts:	Should contain one entry, DMA controller interrupt.

Quoted 9 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt line 12

Quoted 6 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

+- clocks:	Should contain one entry, DMA controller clock.
+- resets :	Should contain one entry, DMA controller reset.
+- #dma-cells:	Should be <1>. The cell represents DMA request select value
+		for the peripheral. For more details consult the Tegra TRM's
+		documentation, in particular AHB DMA channel control register
+		REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as well?

Quoted 2 lines

Actually, DMA transfer trigger isn't related a hardware description. It's up to software to decide what trigger to select. So it shouldn't be in the binding.

I think it could be, if say a board wanted a GPIO to trigger a transfer.

Quoted 2 lines

GPIO isn't a very good example, there is no "GPIO" trigger. To me all triggers are software-defined, so that software could create transfer chains.

TRM shows the following in the APBDMA_TRIG_REG_0 ...

"XRQ_A: XRQ.A (GPIOA) (Hardware initiated DMA request)"

Quoted 45 lines · Jon Hunter

Quoted 43 lines · Dmitry Osipenko

Quoted 41 lines · Jon Hunter

Quoted 34 lines · Dmitry Osipenko

Quoted 23 lines · Jon Hunter

Quoted 21 lines · Dmitry Osipenko

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

new file mode 100644
index 000000000000..2af9aa76ae11
@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:	Must be "nvidia,tegra20-ahbdma"
+- reg:		Should contain registers base address and length.
+- interrupts:	Should contain one entry, DMA controller interrupt.

Quoted 9 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt line 12

Quoted 6 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

+- clocks:	Should contain one entry, DMA controller clock.
+- resets :	Should contain one entry, DMA controller reset.
+- #dma-cells:	Should be <1>. The cell represents DMA request select value
+		for the peripheral. For more details consult the Tegra TRM's
+		documentation, in particular AHB DMA channel control register
+		REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as well?

Quoted 2 lines

Actually, DMA transfer trigger isn't related a hardware description. It's up to software to decide what trigger to select. So it shouldn't be in the binding.

I think it could be, if say a board wanted a GPIO to trigger a transfer.

Quoted 6 lines

Quoted 2 lines

GPIO isn't a very good example, there is no "GPIO" trigger. To me all triggers are software-defined, so that software could create transfer chains.

TRM shows the following in the APBDMA_TRIG_REG_0 ...

"XRQ_A: XRQ.A (GPIOA) (Hardware initiated DMA request)"

Furthermore there are timer and hw-semaphore triggers as well.

Well, the REQ_SEL should definitely be in the binding.

Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks

Quoted 5 lines · Jon Hunter

Well, the REQ_SEL should definitely be in the binding.

Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks

Wrong Stephen?

Quoted 34 lines · Dmitry Osipenko

Quoted 23 lines · Jon Hunter

Quoted 21 lines · Dmitry Osipenko

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
  .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
  1 file changed, 23 insertions(+)

create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

new file mode 100644
index 000000000000..2af9aa76ae11
@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:	Must be "nvidia,tegra20-ahbdma"
+- reg:		Should contain registers base address and length.
+- interrupts:	Should contain one entry, DMA controller interrupt.

Quoted 9 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt line 12

Quoted 6 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

+- clocks:	Should contain one entry, DMA controller clock.
+- resets :	Should contain one entry, DMA controller reset.
+- #dma-cells:	Should be <1>. The cell represents DMA request select value
+		for the peripheral. For more details consult the Tegra TRM's
+		documentation, in particular AHB DMA channel control register
+		REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as well?

Quoted 2 lines

Actually, DMA transfer trigger isn't related a hardware description. It's up to software to decide what trigger to select. So it shouldn't be in the binding.

I think it could be, if say a board wanted a GPIO to trigger a transfer.

Quoted 1 line

And I think the same applies to requester... any objections?

Well, the REQ_SEL should definitely be in the binding.

Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks like we never bothered with it for the APB DMA and so maybe no ones uses this.

Quoted 45 lines · Jon Hunter

Quoted 38 lines · Dmitry Osipenko

Quoted 27 lines · Jon Hunter

Quoted 25 lines · Dmitry Osipenko

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
  .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23
++++++++++++++++++++++

  1 file changed, 23 insertions(+)

  create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file mode 100644
index 000000000000..2af9aa76ae11

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:    Must be "nvidia,tegra20-ahbdma"
+- reg:        Should contain registers base address and length.
+- interrupts:    Should contain one entry, DMA controller interrupt.

Quoted 9 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt line 12

Quoted 6 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

+- clocks:    Should contain one entry, DMA controller clock.
+- resets :    Should contain one entry, DMA controller reset.
+- #dma-cells:    Should be <1>. The cell represents DMA request select value
+        for the peripheral. For more details consult the Tegra TRM's
+        documentation, in particular AHB DMA channel control register
+        REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as well?

Quoted 2 lines

Actually, DMA transfer trigger isn't related a hardware description. It's up to software to decide what trigger to select. So it shouldn't be in the binding.

I think it could be, if say a board wanted a GPIO to trigger a transfer.

Quoted 7 lines

Quoted 1 line

And I think the same applies to requester... any objections?

Well, the REQ_SEL should definitely be in the binding.

Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks like we never bothered with it for the APB DMA and so maybe no ones uses this.

I don't think TRIG_SEL should be in the binding, at least at present. While TRIG_SEL certainly is something used to configure the transfer, I believe the semantics of the current DMA binding only cover DMA transfers that are initiated when SW desires, rather than being a combination of after SW programs the transfer plus some other HW event. So, we always use a default/hard-coded TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's certainly no known use-case that requires a non-default TRIG_SEL value at present. We could add an extra #dma-cells value later if we find a use for it, and the semantics of that use-case make sense to add it to the DMA specifier, rather than some other separate higher-level property/driver/...

Quoted 54 lines · Stephen Warren

Quoted 45 lines · Jon Hunter

Quoted 38 lines · Dmitry Osipenko

Quoted 27 lines · Jon Hunter

Quoted 25 lines · Dmitry Osipenko

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
   .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23
++++++++++++++++++++++
   1 file changed, 23 insertions(+)

  create mode 100644
Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file mode 100644
index 000000000000..2af9aa76ae11

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:    Must be "nvidia,tegra20-ahbdma"
+- reg:        Should contain registers base address and length.
+- interrupts:    Should contain one entry, DMA controller interrupt.

Quoted 9 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt line 12

Quoted 6 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

+- clocks:    Should contain one entry, DMA controller clock.
+- resets :    Should contain one entry, DMA controller reset.
+- #dma-cells:    Should be <1>. The cell represents DMA request select value
+        for the peripheral. For more details consult the Tegra TRM's
+        documentation, in particular AHB DMA channel control register
+        REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as well?

Quoted 2 lines

Actually, DMA transfer trigger isn't related a hardware description. It's up to software to decide what trigger to select. So it shouldn't be in the binding.

I think it could be, if say a board wanted a GPIO to trigger a transfer.

Quoted 7 lines

Quoted 1 line

And I think the same applies to requester... any objections?

Well, the REQ_SEL should definitely be in the binding.

Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks like we never bothered with it for the APB DMA and so maybe no ones uses this.

Quoted 10 lines

I don't think TRIG_SEL should be in the binding, at least at present. While TRIG_SEL certainly is something used to configure the transfer, I believe the semantics of the current DMA binding only cover DMA transfers that are initiated when SW desires, rather than being a combination of after SW programs the transfer plus some other HW event. So, we always use a default/hard-coded TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's certainly no known use-case that requires a non-default TRIG_SEL value at present. We could add an extra #dma-cells value later if we find a use for it, and the semantics of that use-case make sense to add it to the DMA specifier, rather than some other separate higher-level property/driver/...

Thank you for the comment. If we'd want to extend the binding further with the trigger, how to differentiate trigger from the requester in a case of a single #data-cell?

Of course realistically a chance that the further extension would be needed is very-very low, so we may defer the efforts to solve that question and for now make driver aware of the potential #dma-cells extension.

Quoted 68 lines · Dmitry Osipenko

Quoted 56 lines · Stephen Warren

Quoted 47 lines · Jon Hunter

Quoted 39 lines · Dmitry Osipenko

Quoted 28 lines · Jon Hunter

Quoted 26 lines · Dmitry Osipenko

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
   .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23
++++++++++++++++++++++

   1 file changed, 23 insertions(+)

   create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file mode 100644
index 000000000000..2af9aa76ae11

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +7 -0

@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:    Must be "nvidia,tegra20-ahbdma"
+- reg:        Should contain registers base address and length.
+- interrupts:    Should contain one entry, DMA controller interrupt.
+- clocks:    Should contain one entry, DMA controller clock.

Quoted 9 lines

Quoted 6 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +2 -0

+- resets :    Should contain one entry, DMA controller reset.
+- #dma-cells:    Should be <1>. The cell represents DMA request select

value
+        for the peripheral. For more details consult the Tegra TRM's +        documentation, in particular AHB DMA channel control register +        REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as well?

Quoted 3 lines

Actually, DMA transfer trigger isn't related a hardware description. It's up to
software to decide what trigger to select. So it shouldn't be in the binding.

I think it could be, if say a board wanted a GPIO to trigger a transfer.

Quoted 7 lines

Quoted 1 line

And I think the same applies to requester... any objections?

Well, the REQ_SEL should definitely be in the binding.

Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks like we never bothered with it for the APB DMA and so maybe no ones uses this.

Quoted 10 lines

I don't think TRIG_SEL should be in the binding, at least at present. While TRIG_SEL certainly is something used to configure the transfer, I believe the semantics of the current DMA binding only cover DMA transfers that are initiated when SW desires, rather than being a combination of after SW programs the transfer plus some other HW event. So, we always use a default/hard-coded TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's certainly no known use-case that requires a non-default TRIG_SEL value at present. We could add an extra #dma-cells value later if we find a use for it, and the semantics of that use-case make sense to add it to the DMA specifier, rather than some other separate higher-level property/driver/...

Quoted 7 lines

Thank you for the comment. If we'd want to extend the binding further with the trigger, how to differentiate trigger from the requester in a case of a single #data-cell?

Of course realistically a chance that the further extension would be needed is very-very low, so we may defer the efforts to solve that question and for now make driver aware of the potential #dma-cells extension.

The request selector cell isn't optional, so is always present. If we later add an optional trig_sel cell, we'll either have:

#dma-cells=<1>: req_sel

or:

#dma-cells=<2>: req_sel, trig_sel

Quoted 9 lines · Stephen Warren

Quoted 8 lines · Dmitry Osipenko

Quoted 7 lines · Stephen Warren

Quoted 6 lines · Jon Hunter

Quoted 4 lines · Dmitry Osipenko

Quoted 3 lines · Jon Hunter

Quoted 1 line · Dmitry Osipenko

Document DT bindings for NVIDIA Tegra AHB DMA controller that pres=

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on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
=C2=A0=C2=A0 .../bindings/dma/nvidia,tegra20-ahbdma.txt=C2=A0=C2=

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++++++++++++++++++++++
=C2=A0=C2=A0 1 file changed, 23 insertions(+) =C2=A0=C2=A0 create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.=

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diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file mode 100644
index 000000000000..2af9aa76ae11

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.= new file +0 -0

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.= line 5

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.= new file +5 -0

@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:=C2=A0=C2=A0=C2=A0 Must be "nvidia,tegra20-ahbdma"
+- reg:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Should contain r=

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.= line 6

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.= new file +1 -0

+- interrupts:=C2=A0=C2=A0=C2=A0 Should contain one entry, DMA con=

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.= line 7

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.= new file +1 -0

+- clocks:=C2=A0=C2=A0=C2=A0 Should contain one entry, DMA control=

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.= line 8

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.= new file +1 -0

+- resets :=C2=A0=C2=A0=C2=A0 Should contain one entry, DMA contro=

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.= line 9

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.= new file +1 -0

+- #dma-cells:=C2=A0=C2=A0=C2=A0 Should be <1>. The cell represent=

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value
+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 for the peripheral. Fo=

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+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 documentation, in part=

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+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as we=

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Actually, DMA transfer trigger isn't related a hardware description.=

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up to
software to decide what trigger to select. So it shouldn't be in the=

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I think it could be, if say a board wanted a GPIO to trigger a transf=

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And I think the same applies to requester... any objections?

Well, the REQ_SEL should definitely be in the binding.

Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks like we never bothered with it for the APB DMA and so maybe no ones u=

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this.

I don't think TRIG_SEL should be in the binding, at least at present. =

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TRIG_SEL certainly is something used to configure the transfer, I beli=

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semantics of the current DMA binding only cover DMA transfers that are=

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when SW desires, rather than being a combination of after SW programs =

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transfer plus some other HW event. So, we always use a default/hard-co=

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TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. T=

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certainly no known use-case that requires a non-default TRIG_SEL value=

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present. We could add an extra #dma-cells value later if we find a use=

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and the semantics of that use-case make sense to add it to the DMA spe=

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rather than some other separate higher-level property/driver/...

Thank you for the comment. If we'd want to extend the binding further w=

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trigger, how to differentiate trigger from the requester in a case of a=

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#data-cell?

Of course realistically a chance that the further extension would be ne=

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very-very low, so we may defer the efforts to solve that question and f=

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make driver aware of the potential #dma-cells extension.

The request selector cell isn't optional, so is always present. If we la=

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an optional trig_sel cell, we'll either have:

#dma-cells=3D<1>: req_sel

or:

#dma-cells=3D<2>: req_sel, trig_sel

=20
Why request sel. couldn't be optional? Could you please elaborate a bit m=

=20
I think possible options are:
=20
#dma-cells=3D<1>: req_sel
#dma-cells=3D<1>: trig_sel

#dma-cells=3D<2>: req_sel, trig_sel
=20
The only difference between request and trigger is that trigger issues th=

transfer, while request only a single burst. Isn't it possible to have a =

HW for the "trigger-only" option? If not or it's a rareness, then I agree=

REQ_SEL must be mandatory.

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Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
   .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23
++++++++++++++++++++++

   1 file changed, 23 insertions(+)

   create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file mode 100644
index 000000000000..2af9aa76ae11

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +7 -0

@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:    Must be "nvidia,tegra20-ahbdma"
+- reg:        Should contain registers base address and length.
+- interrupts:    Should contain one entry, DMA controller interrupt.
+- clocks:    Should contain one entry, DMA controller clock.

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +2 -0

+- resets :    Should contain one entry, DMA controller reset.
+- #dma-cells:    Should be <1>. The cell represents DMA request select

value
+        for the peripheral. For more details consult the Tegra TRM's +        documentation, in particular AHB DMA channel control register +        REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as well?

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Actually, DMA transfer trigger isn't related a hardware description. It's up to
software to decide what trigger to select. So it shouldn't be in the binding.

I think it could be, if say a board wanted a GPIO to trigger a transfer.

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And I think the same applies to requester... any objections?

Well, the REQ_SEL should definitely be in the binding.

Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks like we never bothered with it for the APB DMA and so maybe no ones uses this.

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I don't think TRIG_SEL should be in the binding, at least at present. While TRIG_SEL certainly is something used to configure the transfer, I believe the semantics of the current DMA binding only cover DMA transfers that are initiated when SW desires, rather than being a combination of after SW programs the transfer plus some other HW event. So, we always use a default/hard-coded TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's certainly no known use-case that requires a non-default TRIG_SEL value at present. We could add an extra #dma-cells value later if we find a use for it, and the semantics of that use-case make sense to add it to the DMA specifier, rather than some other separate higher-level property/driver/...

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Thank you for the comment. If we'd want to extend the binding further with the trigger, how to differentiate trigger from the requester in a case of a single #data-cell?

Of course realistically a chance that the further extension would be needed is very-very low, so we may defer the efforts to solve that question and for now make driver aware of the potential #dma-cells extension.

The request selector cell isn't optional, so is always present. If we later add an optional trig_sel cell, we'll either have:

#dma-cells=<1>: req_sel

or:

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#dma-cells=<2>: req_sel, trig_sel

Why request sel. couldn't be optional? Could you please elaborate a bit more?

I think possible options are:

#dma-cells=<1>: req_sel
#dma-cells=<1>: trig_sel

With the above, how would you know that it is the req_sel or trig_sel that is specified?

Quoted 6 lines

#dma-cells=<2>: req_sel, trig_sel

The only difference between request and trigger is that trigger issues the whole transfer, while request only a single burst. Isn't it possible to have a case in HW for the "trigger-only" option? If not or it's a rareness, then I agree that REQ_SEL must be mandatory.

I think that what Stephen is proposing is that for now we go with '#dma-cells=<1>' and if we ever need to support the trigger cell we could add support for '#dma-cells=<2>'. So with this proposal the 'req_sel' would always be required for both '#dma-cells=<1>' and '#dma-cells=<2>'. Even if the req_sel is not actually used but the 'trig_sel' is, the user would have to set 'req_sel' to some pre-defined value (eg. -1) where we know to ignore it.

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Quoted 1 line · Stephen Warren

On 09/29/2017 09:11 PM, Dmitry Osipenko wrote:

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Document DT bindings for NVIDIA Tegra AHB DMA controller that pr=

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on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
=C2=A0=C2=A0 .../bindings/dma/nvidia,tegra20-ahbdma.txt=C2=A0=C2=

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++++++++++++++++++++++
=C2=A0=C2=A0 1 file changed, 23 insertions(+) =C2=A0=C2=A0 create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.tx=

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b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.tx=

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdm=

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new file mode 100644
index 000000000000..2af9aa76ae11

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdm= new file +0 -0

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdm= line 5

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdm= new file +5 -0

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+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:=C2=A0=C2=A0=C2=A0 Must be "nvidia,tegra20-ahbdma"
+- reg:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Should contain=

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdm= line 6

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdm= new file +1 -0

+- interrupts:=C2=A0=C2=A0=C2=A0 Should contain one entry, DMA c=

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdm= line 7

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdm= new file +1 -0

+- clocks:=C2=A0=C2=A0=C2=A0 Should contain one entry, DMA contr=

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdm= line 8

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdm= new file +1 -0

+- resets :=C2=A0=C2=A0=C2=A0 Should contain one entry, DMA cont=

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdm= line 9

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdm= new file +1 -0

+- #dma-cells:=C2=A0=C2=A0=C2=A0 Should be <1>. The cell represe=

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value
+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 for the peripheral. =

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+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 documentation, in pa=

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+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as =

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Actually, DMA transfer trigger isn't related a hardware descriptio=

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up to
software to decide what trigger to select. So it shouldn't be in t=

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I think it could be, if say a board wanted a GPIO to trigger a tran=

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And I think the same applies to requester... any objections?

Well, the REQ_SEL should definitely be in the binding.

Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Look=

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like we never bothered with it for the APB DMA and so maybe no ones=

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this.

I don't think TRIG_SEL should be in the binding, at least at present=

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TRIG_SEL certainly is something used to configure the transfer, I be=

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semantics of the current DMA binding only cover DMA transfers that a=

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when SW desires, rather than being a combination of after SW program=

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transfer plus some other HW event. So, we always use a default/hard-=

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TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT.=

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certainly no known use-case that requires a non-default TRIG_SEL val=

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present. We could add an extra #dma-cells value later if we find a u=

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and the semantics of that use-case make sense to add it to the DMA s=

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rather than some other separate higher-level property/driver/...

Thank you for the comment. If we'd want to extend the binding further=

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trigger, how to differentiate trigger from the requester in a case of=

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#data-cell?

Of course realistically a chance that the further extension would be =

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very-very low, so we may defer the efforts to solve that question and=

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make driver aware of the potential #dma-cells extension.

The request selector cell isn't optional, so is always present. If we =

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an optional trig_sel cell, we'll either have:

#dma-cells=3D<1>: req_sel

or:

#dma-cells=3D<2>: req_sel, trig_sel

Why request sel. couldn't be optional? Could you please elaborate a bit=

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I think possible options are:

#dma-cells=3D<1>: req_sel
#dma-cells=3D<1>: trig_sel

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With the above, how would you know that it is the req_sel or trig_sel that is specified?

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#dma-cells=3D<2>: req_sel, trig_sel

The only difference between request and trigger is that trigger issues =

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transfer, while request only a single burst. Isn't it possible to have =

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HW for the "trigger-only" option? If not or it's a rareness, then I agr=

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REQ_SEL must be mandatory.

I think that what Stephen is proposing is that for now we go with '#dma-cells=3D<1>' and if we ever need to support the trigger cell we could add support for '#dma-cells=3D<2>'. So with this proposal the 'req_sel' would always be required for both '#dma-cells=3D<1>' and '#dma-cells=3D<2>'. Even if the req_sel is not actually used but the 'trig_sel' is, the user would have to set 'req_sel' to some pre-defined value (eg. -1) where we know to ignore it.

=20
Okay, I see now. Thank you for the clarification, but then we should have=

pre-defined value declared in the binding?

Quoted 81 lines · Dmitry Osipenko

Quoted 80 lines · Stephen Warren

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Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
    .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23
++++++++++++++++++++++
    1 file changed, 23 insertions(+)

   create mode 100644
Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file mode 100644
index 000000000000..2af9aa76ae11

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +7 -0

@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:    Must be "nvidia,tegra20-ahbdma"
+- reg:        Should contain registers base address and length.
+- interrupts:    Should contain one entry, DMA controller interrupt.
+- clocks:    Should contain one entry, DMA controller clock.

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +2 -0

+- resets :    Should contain one entry, DMA controller reset.
+- #dma-cells:    Should be <1>. The cell represents DMA request select

value
+        for the peripheral. For more details consult the Tegra TRM's +        documentation, in particular AHB DMA channel control register +        REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as well?

Quoted 3 lines

Actually, DMA transfer trigger isn't related a hardware description. It's up to
software to decide what trigger to select. So it shouldn't be in the binding.

I think it could be, if say a board wanted a GPIO to trigger a transfer.

Quoted 7 lines

Quoted 1 line

And I think the same applies to requester... any objections?

Well, the REQ_SEL should definitely be in the binding.

Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks like we never bothered with it for the APB DMA and so maybe no ones uses this.

Quoted 10 lines

I don't think TRIG_SEL should be in the binding, at least at present. While TRIG_SEL certainly is something used to configure the transfer, I believe the semantics of the current DMA binding only cover DMA transfers that are initiated when SW desires, rather than being a combination of after SW programs the transfer plus some other HW event. So, we always use a default/hard-coded TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's certainly no known use-case that requires a non-default TRIG_SEL value at present. We could add an extra #dma-cells value later if we find a use for it, and the semantics of that use-case make sense to add it to the DMA specifier, rather than some other separate higher-level property/driver/...

Quoted 7 lines

Thank you for the comment. If we'd want to extend the binding further with the trigger, how to differentiate trigger from the requester in a case of a single #data-cell?

Of course realistically a chance that the further extension would be needed is very-very low, so we may defer the efforts to solve that question and for now make driver aware of the potential #dma-cells extension.

The request selector cell isn't optional, so is always present. If we later add an optional trig_sel cell, we'll either have:

Quoted 7 lines

Quoted 5 lines

#dma-cells=<1>: req_sel

or:

#dma-cells=<2>: req_sel, trig_sel

Why request sel. couldn't be optional? Could you please elaborate a bit more?

Quoted 4 lines

I think possible options are:

#dma-cells=<1>: req_sel
#dma-cells=<1>: trig_sel

With the above, how would you know that it is the req_sel or trig_sel that is specified?

Quoted 87 lines · Jon Hunter

Quoted 84 lines · Dmitry Osipenko

Quoted 83 lines · Stephen Warren

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Quoted 57 lines · Stephen Warren

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Quoted 26 lines · Dmitry Osipenko

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
    .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23
++++++++++++++++++++++

    1 file changed, 23 insertions(+)

    create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file mode 100644
index 000000000000..2af9aa76ae11

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +7 -0

@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:    Must be "nvidia,tegra20-ahbdma"
+- reg:        Should contain registers base address and length.
+- interrupts:    Should contain one entry, DMA controller interrupt.
+- clocks:    Should contain one entry, DMA controller clock.

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Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +2 -0

+- resets :    Should contain one entry, DMA controller reset.
+- #dma-cells:    Should be <1>. The cell represents DMA request select

value
+        for the peripheral. For more details consult the Tegra TRM's +        documentation, in particular AHB DMA channel control register +        REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as well?

Quoted 4 lines

Actually, DMA transfer trigger isn't related a hardware description. It's up to
software to decide what trigger to select. So it shouldn't be in the binding.

I think it could be, if say a board wanted a GPIO to trigger a transfer.

Quoted 7 lines

Quoted 1 line

And I think the same applies to requester... any objections?

Well, the REQ_SEL should definitely be in the binding.

Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks like we never bothered with it for the APB DMA and so maybe no ones uses this.

Quoted 12 lines

I don't think TRIG_SEL should be in the binding, at least at present. While TRIG_SEL certainly is something used to configure the transfer, I believe the semantics of the current DMA binding only cover DMA transfers that are initiated
when SW desires, rather than being a combination of after SW programs the transfer plus some other HW event. So, we always use a default/hard-coded TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's certainly no known use-case that requires a non-default TRIG_SEL value at present. We could add an extra #dma-cells value later if we find a use for it,
and the semantics of that use-case make sense to add it to the DMA specifier, rather than some other separate higher-level property/driver/...

Quoted 7 lines

Thank you for the comment. If we'd want to extend the binding further with the trigger, how to differentiate trigger from the requester in a case of a single #data-cell?

Of course realistically a chance that the further extension would be needed is very-very low, so we may defer the efforts to solve that question and for now make driver aware of the potential #dma-cells extension.

The request selector cell isn't optional, so is always present. If we later add an optional trig_sel cell, we'll either have:

Quoted 7 lines

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#dma-cells=<1>: req_sel

or:

#dma-cells=<2>: req_sel, trig_sel

Why request sel. couldn't be optional? Could you please elaborate a bit more?

The documentation currently says it's mandatory, and DT bindings must be evolved in a backwards-compatible fashion.

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I think possible options are:

#dma-cells=<1>: req_sel
#dma-cells=<1>: trig_sel

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With the above, how would you know that it is the req_sel or trig_sel that is specified?

Also, if req_sel were optional, then it'd be impossible to distinguish between those cases, so we can't design a binding like that. In general, when adding extra optional cells to an #xxx-cells style binding, then whenever cell N is present, all cells before cell N must be present even if optional.

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

new file mode 100644
index 000000000000..2af9aa76ae11
@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:	Must be "nvidia,tegra20-ahbdma"
+- reg:		Should contain registers base address and length.
+- interrupts:	Should contain one entry, DMA controller interrupt.

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +7 -0

+	compatible = "nvidia,tegra20-ahbdma";
+	reg = <0x60008000 0x2000>;
+	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&tegra_car TEGRA20_CLK_AHBDMA>;
+	resets = <&tegra_car 33>;
+	#dma-cells = <1>;
+};

Signature · 1 line

2.14.1

Quoted 25 lines · Dmitry Osipenko

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +10 -0

new file mode 100644
index 000000000000..2af9aa76ae11
@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:	Must be "nvidia,tegra20-ahbdma"
+- reg:		Should contain registers base address and length.
+- interrupts:	Should contain one entry, DMA controller interrupt.
+- clocks:	Should contain one entry, DMA controller clock.
+- resets :	Should contain one entry, DMA controller reset.
+- #dma-cells:	Should be <1>. The cell represents DMA request select value
+		for the peripheral. For more details consult the Tegra TRM's

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt line 16

Quoted 6 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +6 -0

+		documentation, in particular AHB DMA channel control register
+		REQ_SEL field.
+
+Example:
+
+ahbdma: ahbdma@60008000  {

Use standard node names. dma-controller in this case.

Quoted 10 lines

Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt new file +7 -0

+	compatible = "nvidia,tegra20-ahbdma";
+	reg = <0x60008000 0x2000>;
+	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&tegra_car TEGRA20_CLK_AHBDMA>;
+	resets = <&tegra_car 33>;
+	#dma-cells = <1>;
+};

Signature · 1 line

2.14.1

AHB DMA controller presents on Tegra20/30 SoC's, it supports transfers memory <-> AHB bus peripherals as well as mem-to-mem transfers. Driver doesn't yet implement transfers larger than 64K and scatter-gather transfers that have NENT > 1, HW doesn't have native support for these cases.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/dma/Kconfig           |   9 +
 drivers/dma/Makefile          |   1 +
 drivers/dma/tegra20-ahb-dma.c | 679 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 689 insertions(+)
 create mode 100644 drivers/dma/tegra20-ahb-dma.c

drivers/dma/tegra20-ahb-dma.c new file +61 -0

new file mode 100644
index 000000000000..8316d64e35e1
@@ -0,0 +1,679 @@
+/*
+ * Copyright 2017 Dmitry Osipenko <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include "dmaengine.h"
+
+#define TEGRA_AHBDMA_CMD			0x0
+#define TEGRA_AHBDMA_CMD_ENABLE			BIT(31)
+
+#define TEGRA_AHBDMA_IRQ_ENB_MASK		0x20
+#define TEGRA_AHBDMA_IRQ_ENB_CH(ch)		BIT(ch)
+
+#define TEGRA_AHBDMA_CHANNEL_BASE(ch)		(0x1000 + (ch) * 0x20)
+
+#define TEGRA_AHBDMA_CHANNEL_CSR		0x0
+#define TEGRA_AHBDMA_CHANNEL_ADDR_WRAP		BIT(18)
+#define TEGRA_AHBDMA_CHANNEL_FLOW		BIT(24)
+#define TEGRA_AHBDMA_CHANNEL_ONCE		BIT(26)
+#define TEGRA_AHBDMA_CHANNEL_DIR_TO_XMB		BIT(27)
+#define TEGRA_AHBDMA_CHANNEL_IE_EOC		BIT(30)
+#define TEGRA_AHBDMA_CHANNEL_ENABLE		BIT(31)
+#define TEGRA_AHBDMA_CHANNEL_REQ_SEL_SHIFT	16
+#define TEGRA_AHBDMA_CHANNEL_WCOUNT_MASK	0xFFFC
+
+#define TEGRA_AHBDMA_CHANNEL_STA		0x4
+#define TEGRA_AHBDMA_CHANNEL_IS_EOC		BIT(30)
+
+#define TEGRA_AHBDMA_CHANNEL_AHB_PTR		0x10
+
+#define TEGRA_AHBDMA_CHANNEL_AHB_SEQ		0x14
+#define TEGRA_AHBDMA_CHANNEL_INTR_ENB		BIT(31)
+#define TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT	24
+#define TEGRA_AHBDMA_CHANNEL_AHB_BURST_1	2
+#define TEGRA_AHBDMA_CHANNEL_AHB_BURST_4	3
+#define TEGRA_AHBDMA_CHANNEL_AHB_BURST_8	4
+
+#define TEGRA_AHBDMA_CHANNEL_XMB_PTR		0x18

drivers/dma/tegra20-ahb-dma.c new file +427 -0

+	enum dma_transfer_direction dir;
+	dma_addr_t mem_paddr;
+	unsigned long flags;
+	size_t size;
+	bool in_fly;
+	bool cyclic;
+};
+
+struct tegra_ahbdma_chan {
+	struct dma_chan dma_chan;
+	struct list_head active_list;
+	struct list_head pending_list;
+	struct completion idling;
+	void __iomem *regs;
+	spinlock_t lock;
+	unsigned int id;
+};
+
+struct tegra_ahbdma {
+	struct tegra_ahbdma_chan channels[4];
+	struct dma_device dma_dev;
+	struct reset_control *rst;
+	struct clk *clk;
+	void __iomem *regs;
+};
+
+static inline struct tegra_ahbdma *to_ahbdma(struct dma_device *dev)
+{
+	return container_of(dev, struct tegra_ahbdma, dma_dev);
+}
+
+static inline struct tegra_ahbdma_chan *to_ahbdma_chan(struct dma_chan *chan)
+{
+	return container_of(chan, struct tegra_ahbdma_chan, dma_chan);
+}
+
+static inline struct tegra_ahbdma_tx_desc *to_ahbdma_tx_desc(
+				struct dma_async_tx_descriptor *tx)
+{
+	return container_of(tx, struct tegra_ahbdma_tx_desc, desc);
+}
+
+static void tegra_ahbdma_submit_tx(struct tegra_ahbdma_chan *chan,
+				   struct tegra_ahbdma_tx_desc *tx)
+{
+	u32 csr;
+
+	writel_relaxed(tx->mem_paddr,
+		       chan->regs + TEGRA_AHBDMA_CHANNEL_XMB_PTR);
+
+	csr = readl_relaxed(chan->regs + TEGRA_AHBDMA_CHANNEL_CSR);
+
+	csr &= ~TEGRA_AHBDMA_CHANNEL_WCOUNT_MASK;
+	csr &= ~TEGRA_AHBDMA_CHANNEL_DIR_TO_XMB;
+	csr |= TEGRA_AHBDMA_CHANNEL_ENABLE;
+	csr |= TEGRA_AHBDMA_CHANNEL_IE_EOC;
+	csr |= tx->size - sizeof(u32);
+
+	if (tx->dir == DMA_DEV_TO_MEM)
+		csr |= TEGRA_AHBDMA_CHANNEL_DIR_TO_XMB;
+
+	if (!tx->cyclic)
+		csr |= TEGRA_AHBDMA_CHANNEL_ONCE;
+
+	writel_relaxed(csr, chan->regs + TEGRA_AHBDMA_CHANNEL_CSR);
+
+	tx->in_fly = true;
+}
+
+static void tegra_ahbdma_tasklet(unsigned long data)
+{
+	struct tegra_ahbdma_tx_desc *tx = (struct tegra_ahbdma_tx_desc *)data;
+	struct dma_async_tx_descriptor *desc = &tx->desc;
+
+	dmaengine_desc_get_callback_invoke(desc, NULL);
+
+	if (!tx->cyclic && !dmaengine_desc_test_reuse(desc))
+		kfree(tx);
+}
+
+static bool tegra_ahbdma_tx_completed(struct tegra_ahbdma_chan *chan,
+				      struct tegra_ahbdma_tx_desc *tx)
+{
+	struct dma_async_tx_descriptor *desc = &tx->desc;
+	bool reuse = dmaengine_desc_test_reuse(desc);
+	bool interrupt = tx->flags & DMA_PREP_INTERRUPT;
+	bool completed = !tx->cyclic;
+
+	if (completed)
+		dma_cookie_complete(desc);
+
+	if (interrupt)
+		tasklet_schedule(&tx->tasklet);
+
+	if (completed) {
+		list_del(&tx->node);
+
+		if (reuse)
+			tx->in_fly = false;
+
+		if (!interrupt && !reuse)
+			kfree(tx);
+	}
+
+	return completed;
+}
+
+static bool tegra_ahbdma_next_tx_issued(struct tegra_ahbdma_chan *chan)
+{
+	struct tegra_ahbdma_tx_desc *tx;
+
+	tx = list_first_entry_or_null(&chan->active_list,
+				      struct tegra_ahbdma_tx_desc,
+				      node);
+	if (tx)
+		tegra_ahbdma_submit_tx(chan, tx);
+
+	return !!tx;
+}
+
+static void tegra_ahbdma_handle_channel(struct tegra_ahbdma_chan *chan)
+{
+	struct tegra_ahbdma_tx_desc *tx;
+	unsigned long flags;
+	u32 status;
+
+	status = readl_relaxed(chan->regs + TEGRA_AHBDMA_CHANNEL_STA);
+	if (!(status & TEGRA_AHBDMA_CHANNEL_IS_EOC))
+		return;
+
+	writel_relaxed(TEGRA_AHBDMA_CHANNEL_IS_EOC,
+		       chan->regs + TEGRA_AHBDMA_CHANNEL_STA);
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	if (!completion_done(&chan->idling)) {
+		tx = list_first_entry(&chan->active_list,
+				      struct tegra_ahbdma_tx_desc,
+				      node);
+
+		if (tegra_ahbdma_tx_completed(chan, tx) &&
+		    !tegra_ahbdma_next_tx_issued(chan))
+			complete_all(&chan->idling);
+	}
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+static irqreturn_t tegra_ahbdma_isr(int irq, void *dev_id)
+{
+	struct tegra_ahbdma *tdma = dev_id;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(tdma->channels); i++)
+		tegra_ahbdma_handle_channel(&tdma->channels[i]);
+
+	return IRQ_HANDLED;
+}
+
+static dma_cookie_t tegra_ahbdma_tx_submit(struct dma_async_tx_descriptor *desc)
+{
+	struct tegra_ahbdma_tx_desc *tx = to_ahbdma_tx_desc(desc);
+	struct tegra_ahbdma_chan *chan = to_ahbdma_chan(desc->chan);
+	dma_cookie_t cookie;
+
+	cookie = dma_cookie_assign(desc);
+
+	spin_lock_irq(&chan->lock);
+	list_add_tail(&tx->node, &chan->pending_list);
+	spin_unlock_irq(&chan->lock);
+
+	return cookie;
+}
+
+static int tegra_ahbdma_tx_desc_free(struct dma_async_tx_descriptor *desc)
+{
+	kfree(to_ahbdma_tx_desc(desc));
+
+	return 0;
+}
+
+static struct dma_async_tx_descriptor *tegra_ahbdma_prep_slave_sg(
+					struct dma_chan *chan,
+					struct scatterlist *sgl,
+					unsigned int sg_len,
+					enum dma_transfer_direction dir,
+					unsigned long flags,
+					void *context)
+{
+	struct tegra_ahbdma_tx_desc *tx;
+
+	/* unimplemented */
+	if (sg_len != 1 || sg_dma_len(sgl) > SZ_64K)
+		return NULL;
+
+	tx = kzalloc(sizeof(*tx), GFP_KERNEL);
+	if (!tx)
+		return NULL;
+
+	dma_async_tx_descriptor_init(&tx->desc, chan);
+
+	tx->desc.tx_submit	= tegra_ahbdma_tx_submit;
+	tx->desc.desc_free	= tegra_ahbdma_tx_desc_free;
+	tx->mem_paddr		= sg_dma_address(sgl);
+	tx->size		= sg_dma_len(sgl);
+	tx->flags		= flags;
+	tx->dir			= dir;
+
+	tasklet_init(&tx->tasklet, tegra_ahbdma_tasklet, (unsigned long)tx);
+
+	return &tx->desc;
+}
+
+static struct dma_async_tx_descriptor *tegra_ahbdma_prep_dma_cyclic(
+					struct dma_chan *chan,
+					dma_addr_t buf_addr,
+					size_t buf_len,
+					size_t period_len,
+					enum dma_transfer_direction dir,
+					unsigned long flags)
+{
+	struct tegra_ahbdma_tx_desc *tx;
+
+	/* unimplemented */
+	if (buf_len != period_len || buf_len > SZ_64K)
+		return NULL;
+
+	tx = kzalloc(sizeof(*tx), GFP_KERNEL);
+	if (!tx)
+		return NULL;
+
+	dma_async_tx_descriptor_init(&tx->desc, chan);
+
+	tx->desc.tx_submit	= tegra_ahbdma_tx_submit;
+	tx->mem_paddr		= buf_addr;
+	tx->size		= buf_len;
+	tx->flags		= flags;
+	tx->cyclic		= true;
+	tx->dir			= dir;
+
+	tasklet_init(&tx->tasklet, tegra_ahbdma_tasklet, (unsigned long)tx);
+
+	return &tx->desc;
+}
+
+static void tegra_ahbdma_issue_pending(struct dma_chan *chan)
+{
+	struct tegra_ahbdma_chan *ahbdma_chan = to_ahbdma_chan(chan);
+	struct tegra_ahbdma_tx_desc *tx;
+	struct list_head *entry, *tmp;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ahbdma_chan->lock, flags);
+
+	list_for_each_safe(entry, tmp, &ahbdma_chan->pending_list)
+		list_move_tail(entry, &ahbdma_chan->active_list);
+
+	if (completion_done(&ahbdma_chan->idling)) {
+		tx = list_first_entry_or_null(&ahbdma_chan->active_list,
+					      struct tegra_ahbdma_tx_desc,
+					      node);
+		if (tx) {
+			tegra_ahbdma_submit_tx(ahbdma_chan, tx);
+			reinit_completion(&ahbdma_chan->idling);
+		}
+	}
+
+	spin_unlock_irqrestore(&ahbdma_chan->lock, flags);
+}
+
+static enum dma_status tegra_ahbdma_tx_status(struct dma_chan *chan,
+					      dma_cookie_t cookie,
+					      struct dma_tx_state *state)
+{
+	struct tegra_ahbdma_chan *ahbdma_chan = to_ahbdma_chan(chan);
+	struct tegra_ahbdma_tx_desc *tx;
+	enum dma_status cookie_status;
+	unsigned long flags;
+	size_t residual;
+	u32 status;
+
+	spin_lock_irqsave(&ahbdma_chan->lock, flags);
+
+	cookie_status = dma_cookie_status(chan, cookie, state);
+	if (cookie_status != DMA_COMPLETE) {
+		list_for_each_entry(tx, &ahbdma_chan->active_list, node) {
+			if (tx->desc.cookie == cookie)
+				goto found;
+		}
+	}
+
+	goto unlock;
+
+found:
+	if (tx->in_fly) {
+		status = readl_relaxed(
+			ahbdma_chan->regs + TEGRA_AHBDMA_CHANNEL_STA);
+		status  &= TEGRA_AHBDMA_CHANNEL_WCOUNT_MASK;
+
+		residual = status;
+	} else
+		residual = tx->size;
+
+	dma_set_residue(state, residual);
+
+unlock:
+	spin_unlock_irqrestore(&ahbdma_chan->lock, flags);
+
+	return cookie_status;
+}
+
+static int tegra_ahbdma_terminate_all(struct dma_chan *chan)
+{
+	struct tegra_ahbdma_chan *ahbdma_chan = to_ahbdma_chan(chan);
+	struct tegra_ahbdma_tx_desc *tx;
+	struct list_head *entry, *tmp;
+	u32 csr;
+
+	spin_lock_irq(&ahbdma_chan->lock);
+
+	csr = readl_relaxed(ahbdma_chan->regs + TEGRA_AHBDMA_CHANNEL_CSR);
+	csr &= ~TEGRA_AHBDMA_CHANNEL_ENABLE;
+
+	writel_relaxed(csr, ahbdma_chan->regs + TEGRA_AHBDMA_CHANNEL_CSR);
+
+	list_for_each_safe(entry, tmp, &ahbdma_chan->active_list) {
+		tx = list_entry(entry, struct tegra_ahbdma_tx_desc, node);
+		list_del(entry);
+		kfree(tx);
+	}
+
+	list_for_each_safe(entry, tmp, &ahbdma_chan->pending_list) {
+		tx = list_entry(entry, struct tegra_ahbdma_tx_desc, node);
+		list_del(entry);
+		kfree(tx);
+	}
+
+	complete_all(&ahbdma_chan->idling);
+
+	spin_unlock_irq(&ahbdma_chan->lock);
+
+	return 0;
+}
+
+static int tegra_ahbdma_config(struct dma_chan *chan,
+			       struct dma_slave_config *sconfig)
+{
+	struct tegra_ahbdma_chan *ahbdma_chan = to_ahbdma_chan(chan);
+	enum dma_transfer_direction dir = sconfig->direction;
+	u32 burst, ahb_seq, ahb_addr;
+
+	if (sconfig->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES ||
+	    sconfig->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
+		return -EINVAL;
+
+	if (dir == DMA_DEV_TO_MEM) {
+		burst    = sconfig->src_maxburst;
+		ahb_addr = sconfig->src_addr;
+	} else {
+		burst    = sconfig->dst_maxburst;
+		ahb_addr = sconfig->dst_addr;
+	}
+
+	switch (burst) {
+	case 1: burst = TEGRA_AHBDMA_CHANNEL_AHB_BURST_1; break;
+	case 4: burst = TEGRA_AHBDMA_CHANNEL_AHB_BURST_4; break;
+	case 8: burst = TEGRA_AHBDMA_CHANNEL_AHB_BURST_8; break;
+	default:
+		return -EINVAL;
+	}
+
+	ahb_seq  = burst << TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT;
+	ahb_seq |= TEGRA_AHBDMA_CHANNEL_ADDR_WRAP;
+	ahb_seq |= TEGRA_AHBDMA_CHANNEL_INTR_ENB;
+
+	writel_relaxed(ahb_seq,
+		       ahbdma_chan->regs + TEGRA_AHBDMA_CHANNEL_AHB_SEQ);
+
+	writel_relaxed(ahb_addr,
+		       ahbdma_chan->regs + TEGRA_AHBDMA_CHANNEL_AHB_PTR);
+
+	return 0;
+}
+
+static void tegra_ahbdma_synchronize(struct dma_chan *chan)
+{
+	wait_for_completion(&to_ahbdma_chan(chan)->idling);
+}
+
+static void tegra_ahbdma_free_chan_resources(struct dma_chan *chan)
+{
+	struct tegra_ahbdma_chan *ahbdma_chan = to_ahbdma_chan(chan);
+	struct tegra_ahbdma_tx_desc *tx;
+	struct list_head *entry, *tmp;
+
+	list_for_each_safe(entry, tmp, &ahbdma_chan->pending_list) {
+		tx = list_entry(entry, struct tegra_ahbdma_tx_desc, node);
+		list_del(entry);
+		kfree(tx);
+	}
+}
+
+static void tegra_ahbdma_init_channel(struct tegra_ahbdma *tdma,
+				      unsigned int chan_id)
+{
+	struct tegra_ahbdma_chan *ahbdma_chan = &tdma->channels[chan_id];
+	struct dma_chan *dma_chan = &ahbdma_chan->dma_chan;
+	struct dma_device *dma_dev = &tdma->dma_dev;
+
+	INIT_LIST_HEAD(&ahbdma_chan->active_list);
+	INIT_LIST_HEAD(&ahbdma_chan->pending_list);
+	init_completion(&ahbdma_chan->idling);
+	spin_lock_init(&ahbdma_chan->lock);
+	complete(&ahbdma_chan->idling);
+
+	ahbdma_chan->regs = tdma->regs + TEGRA_AHBDMA_CHANNEL_BASE(chan_id);
+	ahbdma_chan->id = chan_id;
+
+	dma_cookie_init(dma_chan);
+	dma_chan->device = dma_dev;
+
+	list_add_tail(&dma_chan->device_node, &dma_dev->channels);
+}
+
+static struct dma_chan *tegra_ahbdma_of_xlate(struct of_phandle_args *dma_spec,
+					      struct of_dma *ofdma)
+{

drivers/dma/tegra20-ahb-dma.c new file +32 -0

+
+		writel_relaxed(csr,
+			to_ahbdma_chan(chan)->regs + TEGRA_AHBDMA_CHANNEL_CSR);
+	}
+	
+	return chan;
+}
+
+static int tegra_ahbdma_init_hw(struct tegra_ahbdma *tdma, struct device *dev)
+{
+	int err;
+
+	err = reset_control_assert(tdma->rst);
+	if (err) {
+		dev_err(dev, "Failed to assert reset: %d\n", err);
+		return err;
+	}
+
+	err = clk_prepare_enable(tdma->clk);
+	if (err) {
+		dev_err(dev, "Failed to enable clock: %d\n", err);
+		return err;
+	}
+
+	usleep_range(1000, 2000);
+
+	err = reset_control_deassert(tdma->rst);
+	if (err) {
+		dev_err(dev, "Failed to deassert reset: %d\n", err);
+		return err;
+	}
+

drivers/dma/tegra20-ahb-dma.c new file +39 -0

+static int tegra_ahbdma_probe(struct platform_device *pdev)
+{
+	struct dma_device *dma_dev;
+	struct tegra_ahbdma *tdma;
+	struct resource *res_regs;
+	unsigned int i;
+	int irq;
+	int err;
+
+	tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma), GFP_KERNEL);
+	if (!tdma)
+		return -ENOMEM;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "Failed to get IRQ\n");
+		return irq;
+	}
+
+	err = devm_request_irq(&pdev->dev, irq, tegra_ahbdma_isr, 0,
+			       dev_name(&pdev->dev), tdma);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to request IRQ\n");
+		return -ENODEV;
+	}
+
+	res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res_regs)
+		return -ENODEV;
+
+	tdma->regs = devm_ioremap_resource(&pdev->dev, res_regs);
+	if (IS_ERR(tdma->regs))
+		return PTR_ERR(tdma->regs);
+
+	tdma->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(tdma->clk)) {
+		dev_err(&pdev->dev, "Failed to get AHB-DMA clock\n");
+		return PTR_ERR(tdma->clk);
+	}

drivers/dma/tegra20-ahb-dma.c new file +57 -0

+	dma_dev = &tdma->dma_dev;
+
+	INIT_LIST_HEAD(&dma_dev->channels);
+
+	for (i = 0; i < ARRAY_SIZE(tdma->channels); i++)
+		tegra_ahbdma_init_channel(tdma, i);
+
+	dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
+	dma_cap_set(DMA_CYCLIC, dma_dev->cap_mask);
+	dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
+
+	dma_dev->max_burst		= 8;
+	dma_dev->directions		= TEGRA_AHBDMA_DIRECTIONS;
+	dma_dev->src_addr_widths	= TEGRA_AHBDMA_BUS_WIDTH;
+	dma_dev->dst_addr_widths	= TEGRA_AHBDMA_BUS_WIDTH;
+	dma_dev->descriptor_reuse	= true;
+	dma_dev->residue_granularity	= DMA_RESIDUE_GRANULARITY_BURST;
+	dma_dev->device_free_chan_resources = tegra_ahbdma_free_chan_resources;
+	dma_dev->device_prep_slave_sg	= tegra_ahbdma_prep_slave_sg;
+	dma_dev->device_prep_dma_cyclic	= tegra_ahbdma_prep_dma_cyclic;
+	dma_dev->device_terminate_all	= tegra_ahbdma_terminate_all;
+	dma_dev->device_issue_pending	= tegra_ahbdma_issue_pending;
+	dma_dev->device_tx_status	= tegra_ahbdma_tx_status;
+	dma_dev->device_config		= tegra_ahbdma_config;
+	dma_dev->device_synchronize	= tegra_ahbdma_synchronize;
+	dma_dev->dev			= &pdev->dev;
+
+	err = dma_async_device_register(dma_dev);
+	if (err) {
+		dev_err(&pdev->dev, "Device registration failed %d\n", err);
+		return err;
+	}
+
+	err = of_dma_controller_register(pdev->dev.of_node,
+					 tegra_ahbdma_of_xlate, tdma);
+	if (err) {
+		dev_err(&pdev->dev, "OF registration failed %d\n", err);
+		dma_async_device_unregister(dma_dev);
+		return err;
+	}
+
+	platform_set_drvdata(pdev, tdma);
+
+	return 0;
+}
+
+static int tegra_ahbdma_remove(struct platform_device *pdev)
+{
+	struct tegra_ahbdma *tdma = platform_get_drvdata(pdev);
+
+	of_dma_controller_free(pdev->dev.of_node);
+	dma_async_device_unregister(&tdma->dma_dev);
+	clk_disable_unprepare(tdma->clk);
+
+	return 0;
+}
+

Hi Dmitry,

Quoted 13 lines · Dmitry Osipenko

AHB DMA controller presents on Tegra20/30 SoC's, it supports transfers memory <-> AHB bus peripherals as well as mem-to-mem transfers. Driver doesn't yet implement transfers larger than 64K and scatter-gather transfers that have NENT > 1, HW doesn't have native support for these cases.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/dma/Kconfig           |   9 +
 drivers/dma/Makefile          |   1 +
 drivers/dma/tegra20-ahb-dma.c | 679 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 689 insertions(+)
 create mode 100644 drivers/dma/tegra20-ahb-dma.c

...

Quoted 72 lines

drivers/dma/tegra20-ahb-dma.c new file +66 -0

new file mode 100644
index 000000000000..8316d64e35e1
@@ -0,0 +1,679 @@
+/*
+ * Copyright 2017 Dmitry Osipenko <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include "dmaengine.h"
+
+#define TEGRA_AHBDMA_CMD			0x0
+#define TEGRA_AHBDMA_CMD_ENABLE			BIT(31)
+
+#define TEGRA_AHBDMA_IRQ_ENB_MASK		0x20
+#define TEGRA_AHBDMA_IRQ_ENB_CH(ch)		BIT(ch)
+
+#define TEGRA_AHBDMA_CHANNEL_BASE(ch)		(0x1000 + (ch) * 0x20)
+
+#define TEGRA_AHBDMA_CHANNEL_CSR		0x0
+#define TEGRA_AHBDMA_CHANNEL_ADDR_WRAP		BIT(18)
+#define TEGRA_AHBDMA_CHANNEL_FLOW		BIT(24)
+#define TEGRA_AHBDMA_CHANNEL_ONCE		BIT(26)
+#define TEGRA_AHBDMA_CHANNEL_DIR_TO_XMB		BIT(27)
+#define TEGRA_AHBDMA_CHANNEL_IE_EOC		BIT(30)
+#define TEGRA_AHBDMA_CHANNEL_ENABLE		BIT(31)
+#define TEGRA_AHBDMA_CHANNEL_REQ_SEL_SHIFT	16
+#define TEGRA_AHBDMA_CHANNEL_WCOUNT_MASK	0xFFFC
+
+#define TEGRA_AHBDMA_CHANNEL_STA		0x4
+#define TEGRA_AHBDMA_CHANNEL_IS_EOC		BIT(30)
+
+#define TEGRA_AHBDMA_CHANNEL_AHB_PTR		0x10
+
+#define TEGRA_AHBDMA_CHANNEL_AHB_SEQ		0x14
+#define TEGRA_AHBDMA_CHANNEL_INTR_ENB		BIT(31)
+#define TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT	24
+#define TEGRA_AHBDMA_CHANNEL_AHB_BURST_1	2
+#define TEGRA_AHBDMA_CHANNEL_AHB_BURST_4	3
+#define TEGRA_AHBDMA_CHANNEL_AHB_BURST_8	4
+
+#define TEGRA_AHBDMA_CHANNEL_XMB_PTR		0x18
+
+#define TEGRA_AHBDMA_BUS_WIDTH			BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+
+#define TEGRA_AHBDMA_DIRECTIONS			BIT(DMA_DEV_TO_MEM) | \
+						BIT(DMA_MEM_TO_DEV)

drivers/dma/tegra20-ahb-dma.c line 71

Quoted 5 lines

drivers/dma/tegra20-ahb-dma.c new file +5 -0

+
+struct tegra_ahbdma_tx_desc {
+	struct dma_async_tx_descriptor desc;
+	struct tasklet_struct tasklet;
+	struct list_head node;

Any reason why we cannot use the virt-dma framework for this driver? I would hope it would simplify the driver a bit.

Quoted 432 lines

drivers/dma/tegra20-ahb-dma.c new file +432 -0

+	enum dma_transfer_direction dir;
+	dma_addr_t mem_paddr;
+	unsigned long flags;
+	size_t size;
+	bool in_fly;
+	bool cyclic;
+};
+
+struct tegra_ahbdma_chan {
+	struct dma_chan dma_chan;
+	struct list_head active_list;
+	struct list_head pending_list;
+	struct completion idling;
+	void __iomem *regs;
+	spinlock_t lock;
+	unsigned int id;
+};
+
+struct tegra_ahbdma {
+	struct tegra_ahbdma_chan channels[4];
+	struct dma_device dma_dev;
+	struct reset_control *rst;
+	struct clk *clk;
+	void __iomem *regs;
+};
+
+static inline struct tegra_ahbdma *to_ahbdma(struct dma_device *dev)
+{
+	return container_of(dev, struct tegra_ahbdma, dma_dev);
+}
+
+static inline struct tegra_ahbdma_chan *to_ahbdma_chan(struct dma_chan *chan)
+{
+	return container_of(chan, struct tegra_ahbdma_chan, dma_chan);
+}
+
+static inline struct tegra_ahbdma_tx_desc *to_ahbdma_tx_desc(
+				struct dma_async_tx_descriptor *tx)
+{
+	return container_of(tx, struct tegra_ahbdma_tx_desc, desc);
+}
+
+static void tegra_ahbdma_submit_tx(struct tegra_ahbdma_chan *chan,
+				   struct tegra_ahbdma_tx_desc *tx)
+{
+	u32 csr;
+
+	writel_relaxed(tx->mem_paddr,
+		       chan->regs + TEGRA_AHBDMA_CHANNEL_XMB_PTR);
+
+	csr = readl_relaxed(chan->regs + TEGRA_AHBDMA_CHANNEL_CSR);
+
+	csr &= ~TEGRA_AHBDMA_CHANNEL_WCOUNT_MASK;
+	csr &= ~TEGRA_AHBDMA_CHANNEL_DIR_TO_XMB;
+	csr |= TEGRA_AHBDMA_CHANNEL_ENABLE;
+	csr |= TEGRA_AHBDMA_CHANNEL_IE_EOC;
+	csr |= tx->size - sizeof(u32);
+
+	if (tx->dir == DMA_DEV_TO_MEM)
+		csr |= TEGRA_AHBDMA_CHANNEL_DIR_TO_XMB;
+
+	if (!tx->cyclic)
+		csr |= TEGRA_AHBDMA_CHANNEL_ONCE;
+
+	writel_relaxed(csr, chan->regs + TEGRA_AHBDMA_CHANNEL_CSR);
+
+	tx->in_fly = true;
+}
+
+static void tegra_ahbdma_tasklet(unsigned long data)
+{
+	struct tegra_ahbdma_tx_desc *tx = (struct tegra_ahbdma_tx_desc *)data;
+	struct dma_async_tx_descriptor *desc = &tx->desc;
+
+	dmaengine_desc_get_callback_invoke(desc, NULL);
+
+	if (!tx->cyclic && !dmaengine_desc_test_reuse(desc))
+		kfree(tx);
+}
+
+static bool tegra_ahbdma_tx_completed(struct tegra_ahbdma_chan *chan,
+				      struct tegra_ahbdma_tx_desc *tx)
+{
+	struct dma_async_tx_descriptor *desc = &tx->desc;
+	bool reuse = dmaengine_desc_test_reuse(desc);
+	bool interrupt = tx->flags & DMA_PREP_INTERRUPT;
+	bool completed = !tx->cyclic;
+
+	if (completed)
+		dma_cookie_complete(desc);
+
+	if (interrupt)
+		tasklet_schedule(&tx->tasklet);
+
+	if (completed) {
+		list_del(&tx->node);
+
+		if (reuse)
+			tx->in_fly = false;
+
+		if (!interrupt && !reuse)
+			kfree(tx);
+	}
+
+	return completed;
+}
+
+static bool tegra_ahbdma_next_tx_issued(struct tegra_ahbdma_chan *chan)
+{
+	struct tegra_ahbdma_tx_desc *tx;
+
+	tx = list_first_entry_or_null(&chan->active_list,
+				      struct tegra_ahbdma_tx_desc,
+				      node);
+	if (tx)
+		tegra_ahbdma_submit_tx(chan, tx);
+
+	return !!tx;
+}
+
+static void tegra_ahbdma_handle_channel(struct tegra_ahbdma_chan *chan)
+{
+	struct tegra_ahbdma_tx_desc *tx;
+	unsigned long flags;
+	u32 status;
+
+	status = readl_relaxed(chan->regs + TEGRA_AHBDMA_CHANNEL_STA);
+	if (!(status & TEGRA_AHBDMA_CHANNEL_IS_EOC))
+		return;
+
+	writel_relaxed(TEGRA_AHBDMA_CHANNEL_IS_EOC,
+		       chan->regs + TEGRA_AHBDMA_CHANNEL_STA);
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	if (!completion_done(&chan->idling)) {
+		tx = list_first_entry(&chan->active_list,
+				      struct tegra_ahbdma_tx_desc,
+				      node);
+
+		if (tegra_ahbdma_tx_completed(chan, tx) &&
+		    !tegra_ahbdma_next_tx_issued(chan))
+			complete_all(&chan->idling);
+	}
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+static irqreturn_t tegra_ahbdma_isr(int irq, void *dev_id)
+{
+	struct tegra_ahbdma *tdma = dev_id;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(tdma->channels); i++)
+		tegra_ahbdma_handle_channel(&tdma->channels[i]);
+
+	return IRQ_HANDLED;
+}
+
+static dma_cookie_t tegra_ahbdma_tx_submit(struct dma_async_tx_descriptor *desc)
+{
+	struct tegra_ahbdma_tx_desc *tx = to_ahbdma_tx_desc(desc);
+	struct tegra_ahbdma_chan *chan = to_ahbdma_chan(desc->chan);
+	dma_cookie_t cookie;
+
+	cookie = dma_cookie_assign(desc);
+
+	spin_lock_irq(&chan->lock);
+	list_add_tail(&tx->node, &chan->pending_list);
+	spin_unlock_irq(&chan->lock);
+
+	return cookie;
+}
+
+static int tegra_ahbdma_tx_desc_free(struct dma_async_tx_descriptor *desc)
+{
+	kfree(to_ahbdma_tx_desc(desc));
+
+	return 0;
+}
+
+static struct dma_async_tx_descriptor *tegra_ahbdma_prep_slave_sg(
+					struct dma_chan *chan,
+					struct scatterlist *sgl,
+					unsigned int sg_len,
+					enum dma_transfer_direction dir,
+					unsigned long flags,
+					void *context)
+{
+	struct tegra_ahbdma_tx_desc *tx;
+
+	/* unimplemented */
+	if (sg_len != 1 || sg_dma_len(sgl) > SZ_64K)
+		return NULL;
+
+	tx = kzalloc(sizeof(*tx), GFP_KERNEL);
+	if (!tx)
+		return NULL;
+
+	dma_async_tx_descriptor_init(&tx->desc, chan);
+
+	tx->desc.tx_submit	= tegra_ahbdma_tx_submit;
+	tx->desc.desc_free	= tegra_ahbdma_tx_desc_free;
+	tx->mem_paddr		= sg_dma_address(sgl);
+	tx->size		= sg_dma_len(sgl);
+	tx->flags		= flags;
+	tx->dir			= dir;
+
+	tasklet_init(&tx->tasklet, tegra_ahbdma_tasklet, (unsigned long)tx);
+
+	return &tx->desc;
+}
+
+static struct dma_async_tx_descriptor *tegra_ahbdma_prep_dma_cyclic(
+					struct dma_chan *chan,
+					dma_addr_t buf_addr,
+					size_t buf_len,
+					size_t period_len,
+					enum dma_transfer_direction dir,
+					unsigned long flags)
+{
+	struct tegra_ahbdma_tx_desc *tx;
+
+	/* unimplemented */
+	if (buf_len != period_len || buf_len > SZ_64K)
+		return NULL;
+
+	tx = kzalloc(sizeof(*tx), GFP_KERNEL);
+	if (!tx)
+		return NULL;
+
+	dma_async_tx_descriptor_init(&tx->desc, chan);
+
+	tx->desc.tx_submit	= tegra_ahbdma_tx_submit;
+	tx->mem_paddr		= buf_addr;
+	tx->size		= buf_len;
+	tx->flags		= flags;
+	tx->cyclic		= true;
+	tx->dir			= dir;
+
+	tasklet_init(&tx->tasklet, tegra_ahbdma_tasklet, (unsigned long)tx);
+
+	return &tx->desc;
+}
+
+static void tegra_ahbdma_issue_pending(struct dma_chan *chan)
+{
+	struct tegra_ahbdma_chan *ahbdma_chan = to_ahbdma_chan(chan);
+	struct tegra_ahbdma_tx_desc *tx;
+	struct list_head *entry, *tmp;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ahbdma_chan->lock, flags);
+
+	list_for_each_safe(entry, tmp, &ahbdma_chan->pending_list)
+		list_move_tail(entry, &ahbdma_chan->active_list);
+
+	if (completion_done(&ahbdma_chan->idling)) {
+		tx = list_first_entry_or_null(&ahbdma_chan->active_list,
+					      struct tegra_ahbdma_tx_desc,
+					      node);
+		if (tx) {
+			tegra_ahbdma_submit_tx(ahbdma_chan, tx);
+			reinit_completion(&ahbdma_chan->idling);
+		}
+	}
+
+	spin_unlock_irqrestore(&ahbdma_chan->lock, flags);
+}
+
+static enum dma_status tegra_ahbdma_tx_status(struct dma_chan *chan,
+					      dma_cookie_t cookie,
+					      struct dma_tx_state *state)
+{
+	struct tegra_ahbdma_chan *ahbdma_chan = to_ahbdma_chan(chan);
+	struct tegra_ahbdma_tx_desc *tx;
+	enum dma_status cookie_status;
+	unsigned long flags;
+	size_t residual;
+	u32 status;
+
+	spin_lock_irqsave(&ahbdma_chan->lock, flags);
+
+	cookie_status = dma_cookie_status(chan, cookie, state);
+	if (cookie_status != DMA_COMPLETE) {
+		list_for_each_entry(tx, &ahbdma_chan->active_list, node) {
+			if (tx->desc.cookie == cookie)
+				goto found;
+		}
+	}
+
+	goto unlock;
+
+found:
+	if (tx->in_fly) {
+		status = readl_relaxed(
+			ahbdma_chan->regs + TEGRA_AHBDMA_CHANNEL_STA);
+		status  &= TEGRA_AHBDMA_CHANNEL_WCOUNT_MASK;
+
+		residual = status;
+	} else
+		residual = tx->size;
+
+	dma_set_residue(state, residual);
+
+unlock:
+	spin_unlock_irqrestore(&ahbdma_chan->lock, flags);
+
+	return cookie_status;
+}
+
+static int tegra_ahbdma_terminate_all(struct dma_chan *chan)
+{
+	struct tegra_ahbdma_chan *ahbdma_chan = to_ahbdma_chan(chan);
+	struct tegra_ahbdma_tx_desc *tx;
+	struct list_head *entry, *tmp;
+	u32 csr;
+
+	spin_lock_irq(&ahbdma_chan->lock);
+
+	csr = readl_relaxed(ahbdma_chan->regs + TEGRA_AHBDMA_CHANNEL_CSR);
+	csr &= ~TEGRA_AHBDMA_CHANNEL_ENABLE;
+
+	writel_relaxed(csr, ahbdma_chan->regs + TEGRA_AHBDMA_CHANNEL_CSR);
+
+	list_for_each_safe(entry, tmp, &ahbdma_chan->active_list) {
+		tx = list_entry(entry, struct tegra_ahbdma_tx_desc, node);
+		list_del(entry);
+		kfree(tx);
+	}
+
+	list_for_each_safe(entry, tmp, &ahbdma_chan->pending_list) {
+		tx = list_entry(entry, struct tegra_ahbdma_tx_desc, node);
+		list_del(entry);
+		kfree(tx);
+	}
+
+	complete_all(&ahbdma_chan->idling);
+
+	spin_unlock_irq(&ahbdma_chan->lock);
+
+	return 0;
+}
+
+static int tegra_ahbdma_config(struct dma_chan *chan,
+			       struct dma_slave_config *sconfig)
+{
+	struct tegra_ahbdma_chan *ahbdma_chan = to_ahbdma_chan(chan);
+	enum dma_transfer_direction dir = sconfig->direction;
+	u32 burst, ahb_seq, ahb_addr;
+
+	if (sconfig->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES ||
+	    sconfig->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
+		return -EINVAL;
+
+	if (dir == DMA_DEV_TO_MEM) {
+		burst    = sconfig->src_maxburst;
+		ahb_addr = sconfig->src_addr;
+	} else {
+		burst    = sconfig->dst_maxburst;
+		ahb_addr = sconfig->dst_addr;
+	}
+
+	switch (burst) {
+	case 1: burst = TEGRA_AHBDMA_CHANNEL_AHB_BURST_1; break;
+	case 4: burst = TEGRA_AHBDMA_CHANNEL_AHB_BURST_4; break;
+	case 8: burst = TEGRA_AHBDMA_CHANNEL_AHB_BURST_8; break;
+	default:
+		return -EINVAL;
+	}
+
+	ahb_seq  = burst << TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT;
+	ahb_seq |= TEGRA_AHBDMA_CHANNEL_ADDR_WRAP;
+	ahb_seq |= TEGRA_AHBDMA_CHANNEL_INTR_ENB;
+
+	writel_relaxed(ahb_seq,
+		       ahbdma_chan->regs + TEGRA_AHBDMA_CHANNEL_AHB_SEQ);
+
+	writel_relaxed(ahb_addr,
+		       ahbdma_chan->regs + TEGRA_AHBDMA_CHANNEL_AHB_PTR);
+
+	return 0;
+}
+
+static void tegra_ahbdma_synchronize(struct dma_chan *chan)
+{
+	wait_for_completion(&to_ahbdma_chan(chan)->idling);
+}
+
+static void tegra_ahbdma_free_chan_resources(struct dma_chan *chan)
+{
+	struct tegra_ahbdma_chan *ahbdma_chan = to_ahbdma_chan(chan);
+	struct tegra_ahbdma_tx_desc *tx;
+	struct list_head *entry, *tmp;
+
+	list_for_each_safe(entry, tmp, &ahbdma_chan->pending_list) {
+		tx = list_entry(entry, struct tegra_ahbdma_tx_desc, node);
+		list_del(entry);
+		kfree(tx);
+	}
+}
+
+static void tegra_ahbdma_init_channel(struct tegra_ahbdma *tdma,
+				      unsigned int chan_id)
+{
+	struct tegra_ahbdma_chan *ahbdma_chan = &tdma->channels[chan_id];
+	struct dma_chan *dma_chan = &ahbdma_chan->dma_chan;
+	struct dma_device *dma_dev = &tdma->dma_dev;
+
+	INIT_LIST_HEAD(&ahbdma_chan->active_list);
+	INIT_LIST_HEAD(&ahbdma_chan->pending_list);
+	init_completion(&ahbdma_chan->idling);
+	spin_lock_init(&ahbdma_chan->lock);
+	complete(&ahbdma_chan->idling);
+
+	ahbdma_chan->regs = tdma->regs + TEGRA_AHBDMA_CHANNEL_BASE(chan_id);
+	ahbdma_chan->id = chan_id;
+
+	dma_cookie_init(dma_chan);
+	dma_chan->device = dma_dev;
+
+	list_add_tail(&dma_chan->device_node, &dma_dev->channels);
+}
+
+static struct dma_chan *tegra_ahbdma_of_xlate(struct of_phandle_args *dma_spec,
+					      struct of_dma *ofdma)
+{
+	struct tegra_ahbdma *tdma = ofdma->of_dma_data;
+	struct dma_chan *chan;
+	u32 csr;
+
+	chan = dma_get_any_slave_channel(&tdma->dma_dev);