Add device tree support for sc7180
Subsystems (7)
v4 cover Add device tree support for sc7180
Changes in v4:
* Rebased on top of Rob;s for-next
* reorderd patches to take care of pdc dependency
* Updated pdc binding to use a soc specific and soc independent compatible
* Other updates based on v3 feedback, changes listed in each patch
Changes in v3:
* PATCH 2/11: Updated the qup and uart lables to be consistent with the naming convention followed in sdm845 as suggested by Matthias
* Dropped 2 patches from v2 which added the new compatible and binding updates for sc7180 pdc and reused sdm845 compatible instead as suggested by Marc Z
This series adds DT support for basic peripherals on qualcomm's sc7180 SoC, drivers for which are already upstream.
The series has a dependency on gcc clock driver patches [1] to merge first
[1] https://www.spinics.net/lists/linux-clk/msg41851.html
Kiran Gunda (3):
arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals
arm64: dts: qcom: sc7180-idp: Add RPMh regulators
Maulik Shah (3):
arm64: dts: qcom: sc7180: Add cmd_db reserved area
arm64: dts: qcom: sc7180: Add rpmh-rsc node
arm64: dts: qcom: sc7180: Add pdc interrupt controller
Rajendra Nayak (5):
dt-bindings: qcom: Add SC7180 bindings
arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
dt-bindings: arm-smmu: update binding for qcom sc7180 SoC
drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
dt-bindings: qcom,pdc: Add compatible for sc7180
Roja Rani Yarubandi (1):
arm64: dts: sc7180: Add qupv3_0 and qupv3_1
Taniya Das (1):
arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver
Vivek Gautam (1):
arm64: dts: sc7180: Add device node for apps_smmu
.../devicetree/bindings/arm/qcom.yaml | 6 + .../interrupt-controller/qcom,pdc.txt | 3 +- .../devicetree/bindings/iommu/arm,smmu.yaml | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/pm6150.dtsi | 72 ++ arch/arm64/boot/dts/qcom/pm6150l.dtsi | 31 + arch/arm64/boot/dts/qcom/sc7180-idp.dts | 402 ++++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 1133 +++++++++++++++++ drivers/irqchip/qcom-pdc.c | 2 +- 9 files changed, 1649 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/pm6150.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pm6150l.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7180-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180.dtsi
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PATCH v4 1/14 dt-bindings: qcom: Add SC7180 bindings
Add a SoC string 'sc7180' for the qualcomm SC7180 SoC. Also add a new board type 'idp'
---
v4: Added schema for sc7180 IDP board
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+)
Documentation/devicetree/bindings/arm/qcom.yaml +6 -0
@@ -36,6 +36,7 @@ description: | mdm9615 ipq8074 sdm845 + sc7180 The 'board' element must be one of the following strings:
@@ -46,6 +47,7 @@ description: | sbc hk01 qrd + idp The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor> where the minor number may be omitted when it's zero, i.e. v1.0 is the same
@@ -144,4 +146,8 @@ properties: - qcom,ipq8074-hk01 - const: qcom,ipq8074 + - items: + - enum: + - qcom,sc7180-idp + - const: qcom,sc7180 ...
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Re: [PATCH v4 01/14] dt-bindings: qcom: Add SC7180 bindings
Quoted 11 lines · Rajendra Nayak
Add a SoC string 'sc7180' for the qualcomm SC7180 SoC. Also add a new board type 'idp'
Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Vinod Koul <[email protected]>---
v4: Added schema for sc7180 IDP boardDocumentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+)
Re: [PATCH v4 01/14] dt-bindings: qcom: Add SC7180 bindings
In reply to Rajendra NayakQuoting Rajendra Nayak (2019-11-05 22:50:04)
Quoted 6 lines
Add a SoC string 'sc7180' for the qualcomm SC7180 SoC. Also add a new board type 'idp'
Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Vinod Koul <[email protected]>---
I see that it isn't sorted but o well!
Re: [PATCH v4 01/14] dt-bindings: qcom: Add SC7180 bindings
Quoted 11 lines · Stephen Boyd
Quoting Rajendra Nayak (2019-11-05 22:50:04)
Quoted 6 lines
Add a SoC string 'sc7180' for the qualcomm SC7180 SoC. Also add a new board type 'idp'
Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Vinod Koul <[email protected]>---
Reviewed-by Stephen Boyd <[email protected]>I see that it isn't sorted but o well!
Well, it wasn't sorted to begin with, so I left it unsorted ¯\_(ツ)_/¯
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PATCH v4 2/14 arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
In reply to Rajendra NayakAdd skeletal sc7180 SoC dtsi and idp board dts files.
---
v4:
* renamed uart10 to uart8
* dropped clock-output-names for xo_board
arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc7180-idp.dts | 47 ++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 299 ++++++++++++++++++++++++ 3 files changed, 347 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180.dtsi
arch/arm64/boot/dts/qcom/Makefile +1 -0
@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
arch/arm64/boot/dts/qcom/sc7180-idp.dts new file +47 -0
47 lines not on this page · raw message
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +299 -0
299 lines not on this page · raw message
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Re: [PATCH v4 02/14] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
Quoting Rajendra Nayak (2019-11-05 22:50:05)
Quoted 25 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +19
-0@@ -0,0 +1,299 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SC7180 SoC device tree source + * + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include <dt-bindings/clock/qcom,gcc-sc7180.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks {
arch/arm64/boot/dts/qcom/sc7180.dtsi line 29
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +10
-0+ xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + clock-output-names = "sleep_clk";
Remove this one too?
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +4
-0+ #clock-cells = <0>; + }; + }; +
[...]
Quoted 61 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +61
-0+ memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sc7180"; + reg = <0 0x00100000 0 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x00ac0000 0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart8: serial@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart8_default>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + tlmm: pinctrl@3500000 { + compatible = "qcom,sc7180-pinctrl"; + reg = <0 0x03500000 0 0x300000>, + <0 0x03900000 0 0x300000>, + <0 0x03d00000 0 0x300000>; + reg-names = "west", "north", "south"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
arch/arm64/boot/dts/qcom/sc7180.dtsi line 208
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +10
-0+ gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 120>; + + qup_uart8_default: qup-uart8-default { + pinmux { + pins = "gpio44", "gpio45"; + function = "qup12";
That looks weird to have qup12 function on uart8. It's right?
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +4
-0+ }; + }; + }; +
Re: [PATCH v4 02/14] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
Quoted 30 lines · Stephen Boyd
Quoting Rajendra Nayak (2019-11-05 22:50:05)
Quoted 29 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +23
-0@@ -0,0 +1,299 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SC7180 SoC device tree source + * + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include <dt-bindings/clock/qcom,gcc-sc7180.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>;
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi line 29
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +6
-0+ }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + clock-output-names = "sleep_clk";Remove this one too?
ah, yes. Not sure how I missed that :/
Quoted 71 lines
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +4
-0+ #clock-cells = <0>; + }; + }; +[...]
Quoted 65 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +65
-0+ memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sc7180"; + reg = <0 0x00100000 0 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x00ac0000 0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart8: serial@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart8_default>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + tlmm: pinctrl@3500000 { + compatible = "qcom,sc7180-pinctrl"; + reg = <0 0x03500000 0 0x300000>, + <0 0x03900000 0 0x300000>, + <0 0x03d00000 0 0x300000>; + reg-names = "west", "north", "south"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>;
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi line 208
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +6
-0+ gpio-ranges = <&tlmm 0 0 120>; + + qup_uart8_default: qup-uart8-default { + pinmux { + pins = "gpio44", "gpio45"; + function = "qup12";That looks weird to have qup12 function on uart8. It's right?
So we have 2 qup instances each with 6 SEs on sc7180.
So the i2c/uart/spi SE instances are numbered from 0 to 5 in the first qup and 6 to 11 in the next.
The pinctrl functions however have it named qup0 to 5 for first and qup10 to 15 for the next which is weird. Now all data in the pinctrl driver is autogenerated using hw description so its coming from that.
Just for comparison, on sdm845 we had 2 qup instances with 8 SE's and the function names were qup0 to 8 for first and 9 to 15 for the second.
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Re: [PATCH v4 02/14] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
Quoting Rajendra Nayak (2019-11-07 19:48:57)
Quoted 17 lines · Stephen Boyd
Quoted 7 lines
Quoting Rajendra Nayak (2019-11-05 22:50:05)
arch/arm64/boot/dts/qcom/sc7180.dtsi line 208
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +4
-0+ qup_uart8_default: qup-uart8-default { + pinmux { + pins = "gpio44", "gpio45"; + function = "qup12";That looks weird to have qup12 function on uart8. It's right?
So we have 2 qup instances each with 6 SEs on sc7180.
So the i2c/uart/spi SE instances are numbered from 0 to 5 in the first qup and 6 to 11 in the next.
The pinctrl functions however have it named qup0 to 5 for first and qup10 to 15 for the next which is weird. Now all data in the pinctrl driver is autogenerated using hw description so its coming from that.
Quoted 4 lines
Just for comparison, on sdm845 we had 2 qup instances with 8 SE's and the function names were qup0 to 8 for first and 9 to 15 for the second.
Alright. Good to know the hardware description is all messed up.
PATCH v4 3/14 dt-bindings: arm-smmu: update binding for qcom sc7180 SoC
In reply to Rajendra NayakAdd the soc specific compatible for sc7180 smmu-500
---
v4: Updated yaml, sorted.
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/iommu/arm,smmu.yaml +1 -0
@@ -34,6 +34,7 @@ properties: - description: Qcom SoCs implementing "arm,mmu-500" items: - enum: + - qcom,sc7180-smmu-500 - qcom,sdm845-smmu-500 - const: arm,mmu-500 - items:
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Rob Herring
maintainerRe: [PATCH v4 03/14] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC
Quoted 11 lines · Rajendra Nayak
Add the soc specific compatible for sc7180 smmu-500
Signed-off-by Rajendra Nayak <[email protected]>Cc Joerg Roedel <[email protected]>Cc Mark Rutland <[email protected]>---
v4: Updated yaml, sorted.Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+)
As this one is dependent on my tree, I've applied it.
Rob
Re: [PATCH v4 03/14] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC
In reply to Rajendra NayakQuoting Rajendra Nayak (2019-11-05 22:50:06)
Quoted 6 lines
Add the soc specific compatible for sc7180 smmu-500
Signed-off-by Rajendra Nayak <[email protected]>Cc Joerg Roedel <[email protected]>Cc Mark Rutland <[email protected]>---
PATCH v4 4/14 arm64: dts: sc7180: Add device node for apps_smmu
In reply to Rajendra NayakFrom: Vivek Gautam <[email protected]>
Adding device node for APPS SMMU that is connected to devices such as display, video, usb, mmc, etc. on SC7180 chipset.
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 88 ++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +88 -0
@@ -210,6 +210,94 @@ }; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #address-cells = <2>;
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Re: [PATCH v4 04/14] arm64: dts: sc7180: Add device node for apps_smmu
Quoting Rajendra Nayak (2019-11-05 22:50:07)
Quoted 9 lines
From: Vivek Gautam <[email protected]>
Adding device node for APPS SMMU that is connected to devices such as display, video, usb, mmc, etc. on SC7180 chipset.
Signed-off-by Vivek Gautam <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
PATCH v4 5/14 arm64: dts: qcom: sc7180: Add cmd_db reserved area
In reply to Rajendra NayakFrom: Maulik Shah <[email protected]>
Command_db provides mapping for resource key and address managed by remote processor. Add cmd_db reserved memory area.
---
v4: updated label to aop_cmd_db_mem
arch/arm64/boot/dts/qcom/sc7180.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +12 -0
@@ -31,6 +31,18 @@ }; }; + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + aop_cmd_db_mem: memory@80820000 { + reg = <0x0 0x80820000 0x0 0x20000>; + compatible = "qcom,cmd-db"; + no-map; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>;
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Re: [PATCH v4 05/14] arm64: dts: qcom: sc7180: Add cmd_db reserved area
Quoting Rajendra Nayak (2019-11-05 22:50:08)
Quoted 8 lines
From: Maulik Shah <[email protected]>
Command_dbprovides mapping for resource key and address managed by remote processor. Addcmd_dbreserved memory area.Signed-off-by Maulik Shah <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
PATCH v4 6/14 arm64: dts: qcom: sc7180: Add rpmh-rsc node
In reply to Rajendra NayakFrom: Maulik Shah <[email protected]>
Add device bindings for the application processor's rsc. The rsc contains the TCS that are used for communicating with the hardened resource accelerators on Qualcomm Technologies, Inc. (QTI) SoCs.
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +19 -0
@@ -7,6 +7,7 @@ #include <dt-bindings/clock/qcom,gcc-sc7180.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> / { interrupt-parent = <&intc>;
@@ -387,6 +388,24 @@ status = "disabled"; }; }; + + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0 0x18200000 0 0x10000>, + <0 0x18210000 0 0x10000>, + <0 0x18220000 0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 2>, + <SLEEP_TCS 3>, + <WAKE_TCS 3>, + <CONTROL_TCS 1>; + }; }; timer {
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Re: [PATCH v4 06/14] arm64: dts: qcom: sc7180: Add rpmh-rsc node
Quoting Rajendra Nayak (2019-11-05 22:50:09)
arch/arm64/boot/dts/qcom/sc7180.dtsi line 392
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +2
-0@@ -387,6 +388,24 @@ status = "disabled"; }; }; + + apps_rsc: rsc@18200000 {
The node name is non-standard. This has been a problem since sdm845 though so it would be nice if we can invent some new name for this that is standard at some point in the future.
arch/arm64/boot/dts/qcom/sc7180.dtsi line 393
Quoted 1 line
arch/arm64/boot/dts/qcom/sc7180.dtsi +1
-0+ label = "apps_rsc";
Can we remove this property? The value seems minimal given that we can use the dev_name() and get the address in there instead of using a label.
Re: [PATCH v4 06/14] arm64: dts: qcom: sc7180: Add rpmh-rsc node
Quoted 16 lines · Stephen Boyd
Quoting Rajendra Nayak (2019-11-05 22:50:09)
arch/arm64/boot/dts/qcom/sc7180.dtsi line 392
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +2
-0@@ -387,6 +388,24 @@ status = "disabled"; }; }; + + apps_rsc: rsc@18200000 {The node name is non-standard. This has been a problem since sdm845 though so it would be nice if we can invent some new name for this that is standard at some point in the future.
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi line 393
Quoted 1 line
arch/arm64/boot/dts/qcom/sc7180.dtsi +1
-0+ label = "apps_rsc";Can we remove this property? The value seems minimal given that we can use the
dev_name()and get the address in there instead of using a label.
Sure, i'll remove it.
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Re: [PATCH v4 06/14] arm64: dts: qcom: sc7180: Add rpmh-rsc node
In reply to Rajendra NayakQuoting Rajendra Nayak (2019-11-05 22:50:09)
Quoted 9 lines
From: Maulik Shah <[email protected]>
Add device bindings for the application processor's rsc. The rsc contains the TCS that are used for communicating with the hardened resource accelerators on Qualcomm Technologies, Inc. (QTI) SoCs.
Signed-off-by Maulik Shah <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
PATCH v4 7/14 drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
In reply to Rajendra NayakRemove the sdm845 SoC specific compatible to make the driver easily reusable across other SoC's with the same IP block. This will reduce further churn adding any SoC specific compatibles unless really needed.
--- drivers/irqchip/qcom-pdc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/irqchip/qcom-pdc.c +1 -1
@@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent)return ret; } -IRQCHIP_DECLARE (pdc_sdm845,"qcom,sdm845-pdc" , qcom_pdc_init); +IRQCHIP_DECLARE (qcom_pdc,"qcom,pdc" , qcom_pdc_init);
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Re: [PATCH v4 07/14] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
Quoted 8 lines · Rajendra Nayak
Remove the sdm845 SoC specific compatible to make the driver easily reusable across other SoC's with the same IP block. This will reduce further churn adding any SoC specific compatibles unless really needed.
Signed-off-by Rajendra Nayak <[email protected]>Cc Lina Iyer <[email protected]>Cc Marc Zyngier <[email protected]>
Quoted 18 lines
---
drivers/irqchip/qcom-pdc.c| 2 +-1 file changed, 1 insertion(+), 1 deletion(-)drivers/irqchip/qcom-pdviewed-by: Lina Iyer <[email protected]> renamed from drivers/irqchip/qcom-pdc.c +1
-2@@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent) return ret; } -IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init); +IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init); --QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v4 07/14] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
In reply to Rajendra NayakQuoting Rajendra Nayak (2019-11-05 22:50:10)
Quoted 9 lines
Remove the sdm845 SoC specific compatible to make the driver easily reusable across other SoC's with the same IP block. This will reduce further churn adding any SoC specific compatibles unless really needed.
Signed-off-by Rajendra Nayak <[email protected]>Cc Lina Iyer <[email protected]>Cc Marc Zyngier <[email protected]>---
PATCH v4 8/14 dt-bindings: qcom,pdc: Add compatible for sc7180
In reply to Rajendra NayakAdd the compatible string for sc7180 SoC from Qualcomm.
--- .../devicetree/bindings/interrupt-controller/qcom,pdc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +2 -1
@@ -17,7 +17,8 @@ Properties: - compatible: Usage: required Value type: <string> - Definition: Should contain "qcom,<soc>-pdc" + Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc" + - "qcom,sc7180-pdc": For SC7180 - "qcom,sdm845-pdc": For SDM845 - reg:
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Rob Herring
maintainerRe: [PATCH v4 08/14] dt-bindings: qcom,pdc: Add compatible for sc7180
Quoted 9 lines · Rajendra Nayak
Add the compatible string for sc7180 SoC from Qualcomm.
Signed-off-by Rajendra Nayak <[email protected]>Cc Lina Iyer <[email protected]>Cc Marc Zyngier <[email protected]>--- .../devicetree/bindings/interrupt-controller/qcom,pdc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
Re: [PATCH v4 08/14] dt-bindings: qcom,pdc: Add compatible for sc7180
Quoted 11 lines · Rob Herring
Quoted 9 lines · Rajendra Nayak
Add the compatible string for sc7180 SoC from Qualcomm.
Signed-off-by Rajendra Nayak <[email protected]>Cc Lina Iyer <[email protected]>Cc Marc Zyngier <[email protected]>--- .../devicetree/bindings/interrupt-controller/qcom,pdc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
Quoted 5 lines
Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
Sorry I missed mentioning the delta and the reason for not including your Acked-by. The previous patch was proposing using just a SoC specific compatible, and this one adds a SoC independent one along with the SoC specific one as discussed here [1]
[1] https://lkml.org/lkml/2019/11/4/73
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Re: [PATCH v4 08/14] dt-bindings: qcom,pdc: Add compatible for sc7180
Quoted 19 lines · Rajendra Nayak
Quoted 15 lines · Rob Herring
Quoted 9 lines · Rajendra Nayak
Add the compatible string for sc7180 SoC from Qualcomm.
Signed-off-by Rajendra Nayak <[email protected]>Cc Lina Iyer <[email protected]>Cc Marc Zyngier <[email protected]>--- .../devicetree/bindings/interrupt-controller/qcom,pdc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply.
Quoted 5 lines
Quoted 1 line
If a tag was not added on purpose, please state why and what changed.
Sorry I missed mentioning the delta and the reason for not including your Acked-by. The previous patch was proposing using just a SoC specific compatible, and this one adds a SoC independent one along with the SoC specific one as discussed here [1]
Okay.
Re: [PATCH v4 08/14] dt-bindings: qcom,pdc: Add compatible for sc7180
In reply to Rajendra NayakQuoting Rajendra Nayak (2019-11-05 22:50:11)
Quoted 6 lines
Add the compatible string for sc7180 SoC from Qualcomm.
Signed-off-by Rajendra Nayak <[email protected]>Cc Lina Iyer <[email protected]>Cc Marc Zyngier <[email protected]>---
PATCH v4 9/14 arm64: dts: qcom: sc7180: Add pdc interrupt controller
In reply to Rajendra NayakFrom: Maulik Shah <[email protected]>
Add pdc interrupt controller for sc7180
---
v4: Updated compatible string
arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +10 -0
@@ -202,6 +202,16 @@ }; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,sc7180-pdc", "qcom,pdc"; + reg = <0 0xb220000 0 0x30000>; + qcom,pdc-ranges = <0 480 15>, <17 497 98>, + <119 634 4>, <124 639 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + tlmm: pinctrl@3500000 { compatible = "qcom,sc7180-pinctrl"; reg = <0 0x03500000 0 0x300000>,
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Re: [PATCH v4 09/14] arm64: dts: qcom: sc7180: Add pdc interrupt controller
Quoting Rajendra Nayak (2019-11-05 22:50:12)
Quoted 7 lines
From: Maulik Shah <[email protected]>
Add pdc interrupt controller for sc7180
Signed-off-by Maulik Shah <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
PATCH v4 10/14 arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
In reply to Rajendra NayakFrom: Kiran Gunda <[email protected]>
Add SPMI PMIC arbiter device to communicate with PMICs attached to SPMI bus.
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +19 -0
@@ -233,6 +233,25 @@ }; }; + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x0c440000 0 0x1100>, + <0 0x0c600000 0 0x2000000>, + <0 0x0e600000 0 0x100000>, + <0 0x0e700000 0 0xa0000>, + <0 0x0c40a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>;
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Re: [PATCH v4 10/14] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
Quoting Rajendra Nayak (2019-11-05 22:50:13)
Quoted 8 lines
From: Kiran Gunda <[email protected]>
Add SPMI PMIC arbiter device to communicate with PMICs attached to SPMI bus.
Signed-off-by Kiran Gunda <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
PATCH v4 11/14 arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals
In reply to Rajendra NayakFrom: Kiran Gunda <[email protected]>
Add PM6150/PM6150L peripherals such as PON, GPIOs, ADC and other PMIC infra modules.
---
v4: Updated pm6150_gpio and pm6150l_gpio to use gpio-ranges
arch/arm64/boot/dts/qcom/pm6150.dtsi | 72 +++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/pm6150l.dtsi | 31 +++++++++++ arch/arm64/boot/dts/qcom/sc7180-idp.dts | 2 + 3 files changed, 105 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm6150.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pm6150l.dtsi
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +72 -0
@@ -0,0 +1,72 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2019, The Linux Foundation. All rights reserved. + +#include <dt-bindings/iio/qcom,spmi-vadc.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/thermal/thermal.h> + +&spmi_bus { + pm6150_lsid0: pmic@0 { + compatible = "qcom,pm6150", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm6150_pon: pon@800 { + compatible = "qcom,pm8998-pon"; + reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = <KEY_POWER>; + }; + }; + + pm6150_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm6150_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm6150_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc-chan@ADC5_DIE_TEMP { + reg = <ADC5_DIE_TEMP>; + label = "die_temp"; + }; + }; + + pm6150_gpio: gpios@c000 { + compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm6150_gpio 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm6150_lsid1: pmic@1 { + compatible = "qcom,pm6150", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +};
arch/arm64/boot/dts/qcom/pm6150l.dtsi new file +31 -0
@@ -0,0 +1,31 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2019, The Linux Foundation. All rights reserved. + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +&spmi_bus { + pm6150l_lsid4: pmic@4 { + compatible = "qcom,pm6150l", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm6150l_gpio: gpios@c000 { + compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm6150l_gpio 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm6150l_lsid5: pmic@5 { + compatible = "qcom,pm6150l", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +};
arch/arm64/boot/dts/qcom/sc7180-idp.dts +2 -0
@@ -8,6 +8,8 @@ /dts-v1/; #include "sc7180.dtsi" +#include "pm6150.dtsi" +#include "pm6150l.dtsi" / { model = "Qualcomm Technologies, Inc. SC7180 IDP";
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Re: [PATCH v4 11/14] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals
Quoting Rajendra Nayak (2019-11-05 22:50:14)
Quoted 8 lines
From: Kiran Gunda <[email protected]>
Add PM6150/PM6150L peripherals such as PON, GPIOs, ADC and other PMIC infra modules.
Signed-off-by Kiran Gunda <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
PATCH v4 12/14 arm64: dts: qcom: sc7180-idp: Add RPMh regulators
In reply to Rajendra NayakFrom: Kiran Gunda <[email protected]>
Add the rpmh regulators for the sc7180 idp platform. This platform consists of PMIC PM6150 and PM6150l
--- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 207 ++++++++++++++++++++++++ 1 file changed, 207 insertions(+)
arch/arm64/boot/dts/qcom/sc7180-idp.dts +207 -0
@@ -7,6 +7,7 @@ /dts-v1/; +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sc7180.dtsi" #include "pm6150.dtsi" #include "pm6150l.dtsi"
@@ -24,6 +25,212 @@ }; }; +&apps_rsc { + pm6150-rpmh-regulators { + compatible = "qcom,pm6150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s1a_1p1: smps1 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_s4a_1p0: smps4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt = <1744000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_l1a_1p2: ldo1 { + regulator-min-microvolt = <1178000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l2a_1p0: ldo2 { + regulator-min-microvolt = <944000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <968000>; + regulator-max-microvolt = <1064000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l4a_0p8: ldo4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l5a_2p7: ldo5 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l6a_0p6: ldo6 { + regulator-min-microvolt = <568000>; + regulator-max-microvolt = <648000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l9a_0p6: ldo9 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1832000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l11a_1p8: ldo11 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1952000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1728000>; + regulator-max-microvolt = <1832000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l17a_3p0: ldo17 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l18a_2p8: ldo18 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l19a_2p9: ldo19 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + }; + + pm6150l-rpmh-regulators { + compatible = "qcom,pm6150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s8c_1p3: smps8 { + regulator-min-microvolt = <1120000>; + regulator-max-microvolt = <1408000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <1984000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1168000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l6c_2p9: ldo6 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l9c_2p9: ldo9 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + }; + }; +}; + &qupv3_id_1 { status = "okay"; };
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QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v4 13/14 arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver
In reply to Rajendra NayakFrom: Taniya Das <[email protected]>
Add node for rpmhcc clock driver.
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +11 -0
@@ -6,6 +6,7 @@ */ #include <dt-bindings/clock/qcom,gcc-sc7180.h> +#include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -174,6 +175,9 @@ gcc: clock-controller@100000 { compatible = "qcom,gcc-sc7180"; reg = <0 0x00100000 0 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>; + clock-names = "bi_tcxo", "bi_tcxo_ao"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;
@@ -434,6 +438,13 @@ <SLEEP_TCS 3>, <WAKE_TCS 3>, <CONTROL_TCS 1>; + + rpmhcc: clock-controller { + compatible = "qcom,sc7180-rpmh-clk"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; }; };
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QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v4 13/14] arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver
Quoting Rajendra Nayak (2019-11-05 22:50:16)
Quoted 7 lines
From: Taniya Das <[email protected]>
Add node for rpmhcc clock driver.
Signed-off-by Taniya Das <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
PATCH v4 14/14 arm64: dts: sc7180: Add qupv3_0 and qupv3_1
In reply to Rajendra NayakFrom: Roja Rani Yarubandi <[email protected]>
Add QUP SE instances configuration for sc7180.
---
v4:
* dropped the uart8/10 hunks
* Fixed qup06/07/08/09/10 functions as qup10/11/12/13/14
arch/arm64/boot/dts/qcom/sc7180-idp.dts | 146 +++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 675 ++++++++++++++++++++++++ 2 files changed, 821 insertions(+)
arch/arm64/boot/dts/qcom/sc7180-idp.dts +146 -0
@@ -17,6 +17,7 @@ compatible = "qcom,sc7180-idp"; aliases { + hsuart0 = &uart3; serial0 = &uart8; };
@@ -231,16 +232,100 @@ }; }; +&qupv3_id_0 { + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; +&uart3 { + status = "okay"; +}; + &uart8 { status = "okay"; }; /* PINCTRL - additions to nodes defined in sc7180.dtsi */ +&qup_i2c2_default { + pinconf { + pins = "gpio15", "gpio16"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_i2c4_default { + pinconf { + pins = "gpio115", "gpio116"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_i2c7_default { + pinconf { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_i2c9_default { + pinconf { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_uart3_default { + pinconf-cts { + /* + * Configure a pull-down on 38 (CTS) to match the pull of + * the Bluetooth module. + */ + pins = "gpio38"; + bias-pull-down; + output-high; + }; + + pinconf-rts { + /* We'll drive 39 (RTS), so no pull */ + pins = "gpio39"; + drive-strength = <2>; + bias-disable; + }; + + pinconf-tx { + /* We'll drive 40 (TX), so no pull */ + pins = "gpio40"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + pinconf-rx { + /* + * Configure a pull-up on 41 (RX). This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + pins = "gpio41"; + bias-pull-up; + }; +}; + &qup_uart8_default { pinconf-tx { pins = "gpio44";
@@ -254,3 +339,64 @@ bias-pull-up; }; }; + +&qup_spi0_default { + pinconf { + pins = "gpio34", "gpio35", "gpio36", "gpio37"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_spi6_default { + pinconf { + pins = "gpio59", "gpio60", "gpio61", "gpio62"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_spi10_default { + pinconf { + pins = "gpio86", "gpio87", "gpio88", "gpio89"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + +&qspi_cs0 { + pinconf { + pins = "gpio68"; + bias-disable; + }; +}; + +&qspi_clk { + pinconf { + pins = "gpio63"; + bias-disable; + }; +}; + +&qspi_data01 { + pinconf { + pins = "gpio64", "gpio65"; + + /* High-Z when no transfers; nice to park the lines */ + bias-pull-up; + }; +};
arch/arm64/boot/dts/qcom/sc7180.dtsi +675 -0
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QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v4 14/14] arm64: dts: sc7180: Add qupv3_0 and qupv3_1
Quoting Rajendra Nayak (2019-11-05 22:50:17)
Quoted 7 lines
From: Roja Rani Yarubandi <[email protected]>
Add QUP SE instances configuration for sc7180.
Signed-off-by Roja Rani Yarubandi <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
It has the weird qup numbering too, but I guess it's correct somehow.
Re: [PATCH v4 14/14] arm64: dts: sc7180: Add qupv3_0 and qupv3_1
Quoted 5 lines · Stephen Boyd
Quoting Rajendra Nayak (2019-11-05 22:50:17)
Quoted 4 lines
From: Roja Rani Yarubandi <[email protected]>
Add QUP SE instances configuration for sc7180.
Quoted 7 lines
Quoted 3 lines
Signed-off-by Roja Rani Yarubandi <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
Reviewed-by Stephen Boyd <[email protected]>It has the weird qup numbering too, but I guess it's correct somehow.
I responded to PATCH 2/14 as to why its weird.
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